source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ cccd60c3

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since cccd60c3 was cccd60c3, checked in by Jiri Svoboda <jiri@…>, 8 years ago

hw_res_enable_interrupt should allow enabling individual interrupts.
  • Property mode set to 100644
File size: 21.7 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <byteorder.h>
41#include <stdio.h>
42#include <errno.h>
43#include <stdbool.h>
44#include <fibril_synch.h>
45#include <str.h>
46#include <ctype.h>
47#include <macros.h>
48#include <str_error.h>
49
50#include <ddf/driver.h>
51#include <ddf/log.h>
52#include <ipc/dev_iface.h>
53#include <irc.h>
54#include <ops/hw_res.h>
55#include <device/hw_res.h>
56#include <ops/pio_window.h>
57#include <device/pio_window.h>
58#include <ddi.h>
59#include <pci_dev_iface.h>
60
61#include "pci.h"
62
63#define NAME "pciintel"
64
65#define CONF_ADDR_ENABLE (1 << 31)
66#define CONF_ADDR(bus, dev, fn, reg) \
67 ((bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
68
69/** Obtain PCI function soft-state from DDF function node */
70static pci_fun_t *pci_fun(ddf_fun_t *fnode)
71{
72 return ddf_fun_data_get(fnode);
73}
74
75/** Obtain PCI bus soft-state from DDF device node */
76#if 0
77static pci_bus_t *pci_bus(ddf_dev_t *dnode)
78{
79 return ddf_dev_data_get(dnode);
80}
81#endif
82
83/** Obtain PCI bus soft-state from function soft-state */
84static pci_bus_t *pci_bus_from_fun(pci_fun_t *fun)
85{
86 return fun->busptr;
87}
88
89/** Max is 47, align to something nice. */
90#define ID_MAX_STR_LEN 50
91
92static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
93{
94 pci_fun_t *fun = pci_fun(fnode);
95
96 if (fun == NULL)
97 return NULL;
98 return &fun->hw_resources;
99}
100
101static int pciintel_enable_interrupt(ddf_fun_t *fnode, int irq)
102{
103 pci_fun_t *dev_data = pci_fun(fnode);
104
105 size_t i;
106 hw_resource_list_t *res = &dev_data->hw_resources;
107 bool found = false;
108
109 found = false;
110 for (i = 0; i < res->count; i++) {
111 if (res->resources[i].type == INTERRUPT) {
112 found = true;
113 break;
114 }
115 }
116
117 if (!found)
118 return EINVAL;
119
120 return irc_enable_interrupt(irq);
121}
122
123static pio_window_t *pciintel_get_pio_window(ddf_fun_t *fnode)
124{
125 pci_fun_t *fun = pci_fun(fnode);
126
127 if (fun == NULL)
128 return NULL;
129 return &fun->pio_window;
130}
131
132
133static int config_space_write_32(ddf_fun_t *fun, uint32_t address,
134 uint32_t data)
135{
136 if (address > 252)
137 return EINVAL;
138 pci_conf_write_32(pci_fun(fun), address, data);
139 return EOK;
140}
141
142static int config_space_write_16(
143 ddf_fun_t *fun, uint32_t address, uint16_t data)
144{
145 if (address > 254)
146 return EINVAL;
147 pci_conf_write_16(pci_fun(fun), address, data);
148 return EOK;
149}
150
151static int config_space_write_8(
152 ddf_fun_t *fun, uint32_t address, uint8_t data)
153{
154 if (address > 255)
155 return EINVAL;
156 pci_conf_write_8(pci_fun(fun), address, data);
157 return EOK;
158}
159
160static int config_space_read_32(
161 ddf_fun_t *fun, uint32_t address, uint32_t *data)
162{
163 if (address > 252)
164 return EINVAL;
165 *data = pci_conf_read_32(pci_fun(fun), address);
166 return EOK;
167}
168
169static int config_space_read_16(
170 ddf_fun_t *fun, uint32_t address, uint16_t *data)
171{
172 if (address > 254)
173 return EINVAL;
174 *data = pci_conf_read_16(pci_fun(fun), address);
175 return EOK;
176}
177
178static int config_space_read_8(
179 ddf_fun_t *fun, uint32_t address, uint8_t *data)
180{
181 if (address > 255)
182 return EINVAL;
183 *data = pci_conf_read_8(pci_fun(fun), address);
184 return EOK;
185}
186
187static hw_res_ops_t pciintel_hw_res_ops = {
188 .get_resource_list = &pciintel_get_resources,
189 .enable_interrupt = &pciintel_enable_interrupt,
190};
191
192static pio_window_ops_t pciintel_pio_window_ops = {
193 .get_pio_window = &pciintel_get_pio_window
194};
195
196static pci_dev_iface_t pci_dev_ops = {
197 .config_space_read_8 = &config_space_read_8,
198 .config_space_read_16 = &config_space_read_16,
199 .config_space_read_32 = &config_space_read_32,
200 .config_space_write_8 = &config_space_write_8,
201 .config_space_write_16 = &config_space_write_16,
202 .config_space_write_32 = &config_space_write_32
203};
204
205static ddf_dev_ops_t pci_fun_ops = {
206 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
207 .interfaces[PIO_WINDOW_DEV_IFACE] = &pciintel_pio_window_ops,
208 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
209};
210
211static int pci_dev_add(ddf_dev_t *);
212static int pci_fun_online(ddf_fun_t *);
213static int pci_fun_offline(ddf_fun_t *);
214
215/** PCI bus driver standard operations */
216static driver_ops_t pci_ops = {
217 .dev_add = &pci_dev_add,
218 .fun_online = &pci_fun_online,
219 .fun_offline = &pci_fun_offline,
220};
221
222/** PCI bus driver structure */
223static driver_t pci_driver = {
224 .name = NAME,
225 .driver_ops = &pci_ops
226};
227
228static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
229{
230 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
231 pci_bus_t *bus = pci_bus_from_fun(fun);
232 uint32_t val;
233
234 fibril_mutex_lock(&bus->conf_mutex);
235
236 if (bus->conf_addr_reg) {
237 pio_write_32(bus->conf_addr_reg,
238 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
239 /*
240 * Always read full 32-bits from the PCI conf_data_port
241 * register and get the desired portion of it afterwards. Some
242 * architectures do not support shorter PIO reads offset from
243 * this register.
244 */
245 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
246 } else {
247 val = uint32_t_le2host(pio_read_32(
248 &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
249 }
250
251 switch (len) {
252 case 1:
253 *buf = (uint8_t) (val >> ((reg & 3) * 8));
254 break;
255 case 2:
256 *((uint16_t *) buf) = (uint16_t) (val >> ((reg & 3)) * 8);
257 break;
258 case 4:
259 *((uint32_t *) buf) = (uint32_t) val;
260 break;
261 }
262
263 fibril_mutex_unlock(&bus->conf_mutex);
264}
265
266static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
267{
268 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
269 pci_bus_t *bus = pci_bus_from_fun(fun);
270 uint32_t val;
271
272 fibril_mutex_lock(&bus->conf_mutex);
273
274 /*
275 * Prepare to write full 32-bits to the PCI conf_data_port register.
276 * Some architectures do not support shorter PIO writes offset from this
277 * register.
278 */
279
280 if (len < 4) {
281 /*
282 * We have fewer than full 32-bits, so we need to read the
283 * missing bits first.
284 */
285 if (bus->conf_addr_reg) {
286 pio_write_32(bus->conf_addr_reg,
287 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
288 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
289 } else {
290 val = uint32_t_le2host(pio_read_32(
291 &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
292 }
293 }
294
295 switch (len) {
296 case 1:
297 val &= ~(0xffU << ((reg & 3) * 8));
298 val |= *buf << ((reg & 3) * 8);
299 break;
300 case 2:
301 val &= ~(0xffffU << ((reg & 3) * 8));
302 val |= *((uint16_t *) buf) << ((reg & 3) * 8);
303 break;
304 case 4:
305 val = *((uint32_t *) buf);
306 break;
307 }
308
309 if (bus->conf_addr_reg) {
310 pio_write_32(bus->conf_addr_reg,
311 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
312 pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
313 } else {
314 pio_write_32(&bus->conf_space[conf_addr / sizeof(ioport32_t)],
315 host2uint32_t_le(val));
316 }
317
318 fibril_mutex_unlock(&bus->conf_mutex);
319}
320
321uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
322{
323 uint8_t res;
324 pci_conf_read(fun, reg, &res, 1);
325 return res;
326}
327
328uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
329{
330 uint16_t res;
331 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
332 return res;
333}
334
335uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
336{
337 uint32_t res;
338 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
339 return res;
340}
341
342void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
343{
344 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
345}
346
347void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
348{
349 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
350}
351
352void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
353{
354 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
355}
356
357void pci_fun_create_match_ids(pci_fun_t *fun)
358{
359 int rc;
360 char match_id_str[ID_MAX_STR_LEN];
361
362 /* Vendor ID & Device ID, length(incl \0) 22 */
363 rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04"
364 PRIx16 "&dev=%04" PRIx16, fun->vendor_id, fun->device_id);
365 if (rc < 0) {
366 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
367 str_error(rc));
368 }
369
370 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
371 if (rc != EOK) {
372 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
373 }
374
375 /* Class, subclass, prog IF, revision, length(incl \0) 47 */
376 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
377 "pci/class=%02x&subclass=%02x&progif=%02x&revision=%02x",
378 fun->class_code, fun->subclass_code, fun->prog_if, fun->revision);
379 if (rc < 0) {
380 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
381 str_error(rc));
382 }
383
384 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 70);
385 if (rc != EOK) {
386 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
387 }
388
389 /* Class, subclass, prog IF, length(incl \0) 35 */
390 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
391 "pci/class=%02x&subclass=%02x&progif=%02x",
392 fun->class_code, fun->subclass_code, fun->prog_if);
393 if (rc < 0) {
394 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
395 str_error(rc));
396 }
397
398 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 60);
399 if (rc != EOK) {
400 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
401 }
402
403 /* Class, subclass, length(incl \0) 25 */
404 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
405 "pci/class=%02x&subclass=%02x",
406 fun->class_code, fun->subclass_code);
407 if (rc < 0) {
408 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
409 str_error(rc));
410 }
411
412 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 50);
413 if (rc != EOK) {
414 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
415 }
416
417 /* Class, length(incl \0) 13 */
418 rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/class=%02x",
419 fun->class_code);
420 if (rc < 0) {
421 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
422 str_error(rc));
423 }
424
425 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 40);
426 if (rc != EOK) {
427 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
428 }
429
430 /* TODO add subsys ids, but those exist only in header type 0 */
431}
432
433void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
434 bool io)
435{
436 hw_resource_list_t *hw_res_list = &fun->hw_resources;
437 hw_resource_t *hw_resources = hw_res_list->resources;
438 size_t count = hw_res_list->count;
439
440 assert(hw_resources != NULL);
441 assert(count < PCI_MAX_HW_RES);
442
443 if (io) {
444 hw_resources[count].type = IO_RANGE;
445 hw_resources[count].res.io_range.address = range_addr;
446 hw_resources[count].res.io_range.size = range_size;
447 hw_resources[count].res.io_range.relative = true;
448 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
449 } else {
450 hw_resources[count].type = MEM_RANGE;
451 hw_resources[count].res.mem_range.address = range_addr;
452 hw_resources[count].res.mem_range.size = range_size;
453 hw_resources[count].res.mem_range.relative = false;
454 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
455 }
456
457 hw_res_list->count++;
458}
459
460/** Read the base address register (BAR) of the device and if it contains valid
461 * address add it to the devices hw resource list.
462 *
463 * @param fun PCI function
464 * @param addr The address of the BAR in the PCI configuration address space of
465 * the device
466 * @return The addr the address of the BAR which should be read next
467 */
468int pci_read_bar(pci_fun_t *fun, int addr)
469{
470 /* Value of the BAR */
471 uint32_t val;
472 uint32_t bar;
473 uint32_t mask;
474
475 /* IO space address */
476 bool io;
477 /* 64-bit wide address */
478 bool addrw64;
479
480 /* Size of the io or memory range specified by the BAR */
481 size_t range_size;
482 /* Beginning of the io or memory range specified by the BAR */
483 uint64_t range_addr;
484
485 /* Get the value of the BAR. */
486 val = pci_conf_read_32(fun, addr);
487
488#define IO_MASK (~0x3)
489#define MEM_MASK (~0xf)
490
491 io = (bool) (val & 1);
492 if (io) {
493 addrw64 = false;
494 mask = IO_MASK;
495 } else {
496 mask = MEM_MASK;
497 switch ((val >> 1) & 3) {
498 case 0:
499 addrw64 = false;
500 break;
501 case 2:
502 addrw64 = true;
503 break;
504 default:
505 /* reserved, go to the next BAR */
506 return addr + 4;
507 }
508 }
509
510 /* Get the address mask. */
511 pci_conf_write_32(fun, addr, 0xffffffff);
512 bar = pci_conf_read_32(fun, addr);
513
514 /*
515 * Unimplemented BARs read back as all 0's.
516 */
517 if (!bar)
518 return addr + (addrw64 ? 8 : 4);
519
520 mask &= bar;
521
522 /* Restore the original value. */
523 pci_conf_write_32(fun, addr, val);
524 val = pci_conf_read_32(fun, addr);
525
526 range_size = pci_bar_mask_to_size(mask);
527
528 if (addrw64) {
529 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
530 (val & 0xfffffff0);
531 } else {
532 range_addr = (val & 0xfffffff0);
533 }
534
535 if (range_addr != 0) {
536 ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
537 ", size = %x", ddf_fun_get_name(fun->fnode), range_addr,
538 (unsigned int) range_size);
539 }
540
541 pci_add_range(fun, range_addr, range_size, io);
542
543 if (addrw64)
544 return addr + 8;
545
546 return addr + 4;
547}
548
549void pci_add_interrupt(pci_fun_t *fun, int irq)
550{
551 hw_resource_list_t *hw_res_list = &fun->hw_resources;
552 hw_resource_t *hw_resources = hw_res_list->resources;
553 size_t count = hw_res_list->count;
554
555 assert(NULL != hw_resources);
556 assert(count < PCI_MAX_HW_RES);
557
558 hw_resources[count].type = INTERRUPT;
559 hw_resources[count].res.interrupt.irq = irq;
560
561 hw_res_list->count++;
562
563 ddf_msg(LVL_NOTE, "Function %s uses irq %x.", ddf_fun_get_name(fun->fnode), irq);
564}
565
566void pci_read_interrupt(pci_fun_t *fun)
567{
568 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
569 uint8_t pin = pci_conf_read_8(fun, PCI_BRIDGE_INT_PIN);
570
571 if (pin != 0 && irq != 0xff)
572 pci_add_interrupt(fun, irq);
573}
574
575/** Enumerate (recursively) and register the devices connected to a pci bus.
576 *
577 * @param bus Host-to-PCI bridge
578 * @param bus_num Bus number
579 */
580void pci_bus_scan(pci_bus_t *bus, int bus_num)
581{
582 pci_fun_t *fun;
583 int rc;
584
585 int child_bus = 0;
586 int dnum, fnum;
587 bool multi;
588 uint8_t header_type;
589
590 for (dnum = 0; dnum < 32; dnum++) {
591 multi = true;
592 for (fnum = 0; multi && fnum < 8; fnum++) {
593 fun = pci_fun_new(bus);
594
595 pci_fun_init(fun, bus_num, dnum, fnum);
596 if (fun->vendor_id == 0xffff) {
597 pci_fun_delete(fun);
598 /*
599 * The device is not present, go on scanning the
600 * bus.
601 */
602 if (fnum == 0)
603 break;
604 else
605 continue;
606 }
607
608 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
609 if (fnum == 0) {
610 /* Is the device multifunction? */
611 multi = header_type >> 7;
612 }
613 /* Clear the multifunction bit. */
614 header_type = header_type & 0x7F;
615
616 char *fun_name = pci_fun_create_name(fun);
617 if (fun_name == NULL) {
618 ddf_msg(LVL_ERROR, "Out of memory.");
619 pci_fun_delete(fun);
620 return;
621 }
622
623 rc = ddf_fun_set_name(fun->fnode, fun_name);
624 free(fun_name);
625 if (rc != EOK) {
626 ddf_msg(LVL_ERROR, "Failed setting function name.");
627 pci_fun_delete(fun);
628 return;
629 }
630
631 pci_alloc_resource_list(fun);
632 pci_read_bars(fun);
633 pci_read_interrupt(fun);
634
635 /* Propagate the PIO window to the function. */
636 fun->pio_window = bus->pio_win;
637
638 ddf_fun_set_ops(fun->fnode, &pci_fun_ops);
639
640 ddf_msg(LVL_DEBUG, "Adding new function %s.",
641 ddf_fun_get_name(fun->fnode));
642
643 pci_fun_create_match_ids(fun);
644
645 if (ddf_fun_bind(fun->fnode) != EOK) {
646 pci_clean_resource_list(fun);
647 pci_fun_delete(fun);
648 continue;
649 }
650
651 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
652 header_type == PCI_HEADER_TYPE_CARDBUS) {
653 child_bus = pci_conf_read_8(fun,
654 PCI_BRIDGE_SEC_BUS_NUM);
655 ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
656 "bridge, secondary bus number = %d.",
657 bus_num);
658 if (child_bus > bus_num)
659 pci_bus_scan(bus, child_bus);
660 }
661 }
662 }
663}
664
665static int pci_dev_add(ddf_dev_t *dnode)
666{
667 hw_resource_list_t hw_resources;
668 pci_bus_t *bus = NULL;
669 ddf_fun_t *ctl = NULL;
670 bool got_res = false;
671 async_sess_t *sess;
672 int rc;
673
674 ddf_msg(LVL_DEBUG, "pci_dev_add");
675
676 bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
677 if (bus == NULL) {
678 ddf_msg(LVL_ERROR, "pci_dev_add allocation failed.");
679 rc = ENOMEM;
680 goto fail;
681 }
682 fibril_mutex_initialize(&bus->conf_mutex);
683
684 bus->dnode = dnode;
685
686 sess = ddf_dev_parent_sess_get(dnode);
687 if (sess == NULL) {
688 ddf_msg(LVL_ERROR, "pci_dev_add failed to connect to the "
689 "parent driver.");
690 rc = ENOENT;
691 goto fail;
692 }
693
694 rc = pio_window_get(sess, &bus->pio_win);
695 if (rc != EOK) {
696 ddf_msg(LVL_ERROR, "pci_dev_add failed to get PIO window "
697 "for the device.");
698 goto fail;
699 }
700
701 rc = hw_res_get_resource_list(sess, &hw_resources);
702 if (rc != EOK) {
703 ddf_msg(LVL_ERROR, "pci_dev_add failed to get hw resources "
704 "for the device.");
705 goto fail;
706 }
707 got_res = true;
708
709
710 assert(hw_resources.count >= 1);
711
712 if (hw_resources.count == 1) {
713 assert(hw_resources.resources[0].type == MEM_RANGE);
714
715 ddf_msg(LVL_DEBUG, "conf_addr_space = %" PRIx64 ".",
716 hw_resources.resources[0].res.mem_range.address);
717
718 if (pio_enable_resource(&bus->pio_win,
719 &hw_resources.resources[0],
720 (void **) &bus->conf_space)) {
721 ddf_msg(LVL_ERROR,
722 "Failed to map configuration space.");
723 rc = EADDRNOTAVAIL;
724 goto fail;
725 }
726
727 } else {
728 assert(hw_resources.resources[0].type == IO_RANGE);
729 assert(hw_resources.resources[0].res.io_range.size >= 4);
730
731 assert(hw_resources.resources[1].type == IO_RANGE);
732 assert(hw_resources.resources[1].res.io_range.size >= 4);
733
734 ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
735 hw_resources.resources[0].res.io_range.address);
736 ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
737 hw_resources.resources[1].res.io_range.address);
738
739 if (pio_enable_resource(&bus->pio_win,
740 &hw_resources.resources[0],
741 (void **) &bus->conf_addr_reg)) {
742 ddf_msg(LVL_ERROR,
743 "Failed to enable configuration ports.");
744 rc = EADDRNOTAVAIL;
745 goto fail;
746 }
747 if (pio_enable_resource(&bus->pio_win,
748 &hw_resources.resources[1],
749 (void **) &bus->conf_data_reg)) {
750 ddf_msg(LVL_ERROR,
751 "Failed to enable configuration ports.");
752 rc = EADDRNOTAVAIL;
753 goto fail;
754 }
755 }
756
757 /* Make the bus device more visible. It has no use yet. */
758 ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
759
760 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
761 if (ctl == NULL) {
762 ddf_msg(LVL_ERROR, "Failed creating control function.");
763 rc = ENOMEM;
764 goto fail;
765 }
766
767 rc = ddf_fun_bind(ctl);
768 if (rc != EOK) {
769 ddf_msg(LVL_ERROR, "Failed binding control function.");
770 goto fail;
771 }
772
773 /* Enumerate functions. */
774 ddf_msg(LVL_DEBUG, "Scanning the bus");
775 pci_bus_scan(bus, 0);
776
777 hw_res_clean_resource_list(&hw_resources);
778
779 return EOK;
780
781fail:
782 if (got_res)
783 hw_res_clean_resource_list(&hw_resources);
784
785 if (ctl != NULL)
786 ddf_fun_destroy(ctl);
787
788 return rc;
789}
790
791static int pci_fun_online(ddf_fun_t *fun)
792{
793 ddf_msg(LVL_DEBUG, "pci_fun_online()");
794 return ddf_fun_online(fun);
795}
796
797static int pci_fun_offline(ddf_fun_t *fun)
798{
799 ddf_msg(LVL_DEBUG, "pci_fun_offline()");
800 return ddf_fun_offline(fun);
801}
802
803static void pciintel_init(void)
804{
805 ddf_log_init(NAME);
806}
807
808pci_fun_t *pci_fun_new(pci_bus_t *bus)
809{
810 pci_fun_t *fun;
811 ddf_fun_t *fnode;
812
813 fnode = ddf_fun_create(bus->dnode, fun_inner, NULL);
814 if (fnode == NULL)
815 return NULL;
816
817 fun = ddf_fun_data_alloc(fnode, sizeof(pci_fun_t));
818 if (fun == NULL)
819 return NULL;
820
821 fun->busptr = bus;
822 fun->fnode = fnode;
823 return fun;
824}
825
826void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
827{
828 fun->bus = bus;
829 fun->dev = dev;
830 fun->fn = fn;
831 fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
832 fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
833
834 /* Explicitly enable PCI bus mastering */
835 fun->command = pci_conf_read_16(fun, PCI_COMMAND) |
836 PCI_COMMAND_MASTER;
837 pci_conf_write_16(fun, PCI_COMMAND, fun->command);
838
839 fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
840 fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
841 fun->prog_if = pci_conf_read_8(fun, PCI_PROG_IF);
842 fun->revision = pci_conf_read_8(fun, PCI_REVISION_ID);
843}
844
845void pci_fun_delete(pci_fun_t *fun)
846{
847 hw_res_clean_resource_list(&fun->hw_resources);
848 if (fun->fnode != NULL)
849 ddf_fun_destroy(fun->fnode);
850}
851
852char *pci_fun_create_name(pci_fun_t *fun)
853{
854 char *name = NULL;
855
856 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
857 fun->fn);
858 return name;
859}
860
861bool pci_alloc_resource_list(pci_fun_t *fun)
862{
863 fun->hw_resources.resources = fun->resources;
864 return true;
865}
866
867void pci_clean_resource_list(pci_fun_t *fun)
868{
869 fun->hw_resources.resources = NULL;
870}
871
872/** Read the base address registers (BARs) of the function and add the addresses
873 * to its HW resource list.
874 *
875 * @param fun PCI function
876 */
877void pci_read_bars(pci_fun_t *fun)
878{
879 /*
880 * Position of the BAR in the PCI configuration address space of the
881 * device.
882 */
883 int addr = PCI_BASE_ADDR_0;
884
885 while (addr <= PCI_BASE_ADDR_5)
886 addr = pci_read_bar(fun, addr);
887}
888
889size_t pci_bar_mask_to_size(uint32_t mask)
890{
891 size_t size = mask & ~(mask - 1);
892 return size;
893}
894
895int main(int argc, char *argv[])
896{
897 printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
898 pciintel_init();
899 return ddf_driver_main(&pci_driver);
900}
901
902/**
903 * @}
904 */
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