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source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ cb94e69b

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Last change on this file since cb94e69b was cb94e69b, checked in by Jan Vesely <jano.vesely@…>, 14 years ago
pci: Fix memory leak in error path.
Property mode set to `100644`
File size: 19.5 KB

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1	/*
2	* Copyright (c) 2010 Lenka Trochtova
3	* Copyright (c) 2011 Jiri Svoboda
4	* All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	*
10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/
29
30	/**
31	* @defgroup pciintel pci bus driver for intel method 1.
32	* @brief HelenOS root pci bus driver for intel method 1.
33	* @{
34	*/
35
36	/** @file
37	*/
38
39	#include <assert.h>
40	#include <stdio.h>
41	#include <errno.h>
42	#include <bool.h>
43	#include <fibril_synch.h>
44	#include <str.h>
45	#include <ctype.h>
46	#include <macros.h>
47	#include <str_error.h>
48
49	#include <ddf/driver.h>
50	#include <ddf/log.h>
51	#include <devman.h>
52	#include <ipc/devman.h>
53	#include <ipc/dev_iface.h>
54	#include <ipc/irc.h>
55	#include <ns.h>
56	#include <ipc/services.h>
57	#include <sysinfo.h>
58	#include <ops/hw_res.h>
59	#include <device/hw_res.h>
60	#include <ddi.h>
61	#include <libarch/ddi.h>
62	#include <pci_dev_iface.h>
63
64	#include "pci.h"
65
66	#define NAME "pciintel"
67
68	#define CONF_ADDR(bus, dev, fn, reg) \
69	((1 << 31) \| (bus << 16) \| (dev << 11) \| (fn << 8) \| (reg & ~3))
70
71	/** Obtain PCI function soft-state from DDF function node */
72	#define PCI_FUN(fnode) ((pci_fun_t *) (fnode)->driver_data)
73
74	/** Obtain PCI bus soft-state from DDF device node */
75	#define PCI_BUS(dnode) ((pci_bus_t *) (dnode)->driver_data)
76
77	/** Obtain PCI bus soft-state from function soft-state */
78	#define PCI_BUS_FROM_FUN(fun) ((fun)->busptr)
79
80	static hw_resource_list_t pciintel_get_resources(ddf_fun_t fnode)
81	{
82	pci_fun_t *fun = PCI_FUN(fnode);
83
84	if (fun == NULL)
85	return NULL;
86	return &fun->hw_resources;
87	}
88
89	static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
90	{
91	/* This is an old ugly way, copied from ne2000 driver */
92	assert(fnode);
93	pci_fun_t dev_data = (pci_fun_t ) fnode->driver_data;
94
95	sysarg_t apic;
96	sysarg_t i8259;
97
98	async_sess_t *irc_sess = NULL;
99
100	if (((sysinfo_get_value("apic", &apic) == EOK) && (apic))
101	\|\| ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259))) {
102	irc_sess = service_connect_blocking(EXCHANGE_SERIALIZE,
103	SERVICE_IRC, 0, 0);
104	}
105
106	if (!irc_sess)
107	return false;
108
109	size_t i = 0;
110	hw_resource_list_t *res = &dev_data->hw_resources;
111	for (; i < res->count; i++) {
112	if (res->resources[i].type == INTERRUPT) {
113	const int irq = res->resources[i].res.interrupt.irq;
114
115	async_exch_t *exch = async_exchange_begin(irc_sess);
116	const int rc =
117	async_req_1_0(exch, IRC_ENABLE_INTERRUPT, irq);
118	async_exchange_end(exch);
119
120	if (rc != EOK) {
121	async_hangup(irc_sess);
122	return false;
123	}
124	}
125	}
126
127	async_hangup(irc_sess);
128	return true;
129	}
130
131	static int pci_config_space_write_32(ddf_fun_t *fun, uint32_t address,
132	uint32_t data)
133	{
134	if (address > 252)
135	return EINVAL;
136	pci_conf_write_32(PCI_FUN(fun), address, data);
137	return EOK;
138	}
139
140	static int pci_config_space_write_16(
141	ddf_fun_t *fun, uint32_t address, uint16_t data)
142	{
143	if (address > 254)
144	return EINVAL;
145	pci_conf_write_16(PCI_FUN(fun), address, data);
146	return EOK;
147	}
148
149	static int pci_config_space_write_8(
150	ddf_fun_t *fun, uint32_t address, uint8_t data)
151	{
152	if (address > 255)
153	return EINVAL;
154	pci_conf_write_8(PCI_FUN(fun), address, data);
155	return EOK;
156	}
157
158	static int pci_config_space_read_32(
159	ddf_fun_t fun, uint32_t address, uint32_t data)
160	{
161	if (address > 252)
162	return EINVAL;
163	*data = pci_conf_read_32(PCI_FUN(fun), address);
164	return EOK;
165	}
166
167	static int pci_config_space_read_16(
168	ddf_fun_t fun, uint32_t address, uint16_t data)
169	{
170	if (address > 254)
171	return EINVAL;
172	*data = pci_conf_read_16(PCI_FUN(fun), address);
173	return EOK;
174	}
175
176	static int pci_config_space_read_8(
177	ddf_fun_t fun, uint32_t address, uint8_t data)
178	{
179	if (address > 255)
180	return EINVAL;
181	*data = pci_conf_read_8(PCI_FUN(fun), address);
182	return EOK;
183	}
184
185	static hw_res_ops_t pciintel_hw_res_ops = {
186	&pciintel_get_resources,
187	&pciintel_enable_interrupt
188	};
189
190	static pci_dev_iface_t pci_dev_ops = {
191	.config_space_read_8 = &pci_config_space_read_8,
192	.config_space_read_16 = &pci_config_space_read_16,
193	.config_space_read_32 = &pci_config_space_read_32,
194	.config_space_write_8 = &pci_config_space_write_8,
195	.config_space_write_16 = &pci_config_space_write_16,
196	.config_space_write_32 = &pci_config_space_write_32
197	};
198
199	static ddf_dev_ops_t pci_fun_ops = {
200	.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
201	.interfaces[PCI_DEV_IFACE] = &pci_dev_ops
202	};
203
204	static int pci_add_device(ddf_dev_t *);
205	static int pci_fun_online(ddf_fun_t *);
206	static int pci_fun_offline(ddf_fun_t *);
207
208	/** PCI bus driver standard operations */
209	static driver_ops_t pci_ops = {
210	.add_device = &pci_add_device,
211	.fun_online = &pci_fun_online,
212	.fun_offline = &pci_fun_offline,
213	};
214
215	/** PCI bus driver structure */
216	static driver_t pci_driver = {
217	.name = NAME,
218	.driver_ops = &pci_ops
219	};
220
221	static void pci_conf_read(pci_fun_t fun, int reg, uint8_t buf, size_t len)
222	{
223	pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
224
225	fibril_mutex_lock(&bus->conf_mutex);
226
227	const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
228	void *addr = bus->conf_data_port + (reg & 3);
229
230	pio_write_32(bus->conf_addr_port, conf_addr);
231
232	switch (len) {
233	case 1:
234	buf[0] = pio_read_8(addr);
235	break;
236	case 2:
237	((uint16_t *) buf)[0] = pio_read_16(addr);
238	break;
239	case 4:
240	((uint32_t *) buf)[0] = pio_read_32(addr);
241	break;
242	}
243
244	fibril_mutex_unlock(&bus->conf_mutex);
245	}
246
247	static void pci_conf_write(pci_fun_t fun, int reg, uint8_t buf, size_t len)
248	{
249	pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
250
251	fibril_mutex_lock(&bus->conf_mutex);
252
253	uint32_t conf_addr;
254	conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
255	void *addr = bus->conf_data_port + (reg & 3);
256
257	pio_write_32(bus->conf_addr_port, conf_addr);
258
259	switch (len) {
260	case 1:
261	pio_write_8(addr, buf[0]);
262	break;
263	case 2:
264	pio_write_16(addr, ((uint16_t *) buf)[0]);
265	break;
266	case 4:
267	pio_write_32(addr, ((uint32_t *) buf)[0]);
268	break;
269	}
270
271	fibril_mutex_unlock(&bus->conf_mutex);
272	}
273
274	uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
275	{
276	uint8_t res;
277	pci_conf_read(fun, reg, &res, 1);
278	return res;
279	}
280
281	uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
282	{
283	uint16_t res;
284	pci_conf_read(fun, reg, (uint8_t *) &res, 2);
285	return res;
286	}
287
288	uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
289	{
290	uint32_t res;
291	pci_conf_read(fun, reg, (uint8_t *) &res, 4);
292	return res;
293	}
294
295	void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
296	{
297	pci_conf_write(fun, reg, (uint8_t *) &val, 1);
298	}
299
300	void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
301	{
302	pci_conf_write(fun, reg, (uint8_t *) &val, 2);
303	}
304
305	void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
306	{
307	pci_conf_write(fun, reg, (uint8_t *) &val, 4);
308	}
309
310	void pci_fun_create_match_ids(pci_fun_t *fun)
311	{
312	#define ID_MAX_STR_LEN 50 /* Max is 47, align to something nice. */
313
314	int rc;
315	char match_id_str[ID_MAX_STR_LEN];
316
317	/* Vendor ID & Device ID, length(incl \0) 22 */
318	rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04x&dev=%04x",
319	fun->vendor_id, fun->device_id);
320	if (rc < 0) {
321	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
322	str_error(rc));
323	}
324
325	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
326	if (rc != EOK) {
327	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
328	}
329
330	/* Class, subclass, prog IF, revision, length(incl \0) 47 */
331	rc = snprintf(match_id_str, ID_MAX_STR_LEN,
332	"pci/class=%02x&subclass=%02x&progif=%02x&revision=%02x",
333	fun->class_code, fun->subclass_code, fun->prog_if, fun->revision);
334	if (rc < 0) {
335	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
336	str_error(rc));
337	}
338
339	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 70);
340	if (rc != EOK) {
341	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
342	}
343
344	/* Class, subclass, prog IF, length(incl \0) 35 */
345	rc = snprintf(match_id_str, ID_MAX_STR_LEN,
346	"pci/class=%02x&subclass=%02x&progif=%02x",
347	fun->class_code, fun->subclass_code, fun->prog_if);
348	if (rc < 0) {
349	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
350	str_error(rc));
351	}
352
353	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 60);
354	if (rc != EOK) {
355	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
356	}
357
358	/* Class, subclass, length(incl \0) 25 */
359	rc = snprintf(match_id_str, ID_MAX_STR_LEN,
360	"pci/class=%02x&subclass=%02x",
361	fun->class_code, fun->subclass_code);
362	if (rc < 0) {
363	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
364	str_error(rc));
365	}
366
367	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 50);
368	if (rc != EOK) {
369	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
370	}
371
372	/* Class, length(incl \0) 13 */
373	rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/class=%02x",
374	fun->class_code);
375	if (rc < 0) {
376	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
377	str_error(rc));
378	}
379
380	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 40);
381	if (rc != EOK) {
382	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
383	}
384
385	/* TODO add subsys ids, but those exist only in header type 0 */
386	}
387
388	void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
389	bool io)
390	{
391	hw_resource_list_t *hw_res_list = &fun->hw_resources;
392	hw_resource_t *hw_resources = hw_res_list->resources;
393	size_t count = hw_res_list->count;
394
395	assert(hw_resources != NULL);
396	assert(count < PCI_MAX_HW_RES);
397
398	if (io) {
399	hw_resources[count].type = IO_RANGE;
400	hw_resources[count].res.io_range.address = range_addr;
401	hw_resources[count].res.io_range.size = range_size;
402	hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
403	} else {
404	hw_resources[count].type = MEM_RANGE;
405	hw_resources[count].res.mem_range.address = range_addr;
406	hw_resources[count].res.mem_range.size = range_size;
407	hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
408	}
409
410	hw_res_list->count++;
411	}
412
413	/** Read the base address register (BAR) of the device and if it contains valid
414	* address add it to the devices hw resource list.
415	*
416	* @param fun PCI function
417	* @param addr The address of the BAR in the PCI configuration address space of
418	* the device
419	* @return The addr the address of the BAR which should be read next
420	*/
421	int pci_read_bar(pci_fun_t *fun, int addr)
422	{
423	/* Value of the BAR */
424	uint32_t val, mask;
425	/* IO space address */
426	bool io;
427	/* 64-bit wide address */
428	bool addrw64;
429
430	/* Size of the io or memory range specified by the BAR */
431	size_t range_size;
432	/* Beginning of the io or memory range specified by the BAR */
433	uint64_t range_addr;
434
435	/* Get the value of the BAR. */
436	val = pci_conf_read_32(fun, addr);
437
438	#define IO_MASK (~0x3)
439	#define MEM_MASK (~0xf)
440
441	io = (bool) (val & 1);
442	if (io) {
443	addrw64 = false;
444	mask = IO_MASK;
445	} else {
446	mask = MEM_MASK;
447	switch ((val >> 1) & 3) {
448	case 0:
449	addrw64 = false;
450	break;
451	case 2:
452	addrw64 = true;
453	break;
454	default:
455	/* reserved, go to the next BAR */
456	return addr + 4;
457	}
458	}
459
460	/* Get the address mask. */
461	pci_conf_write_32(fun, addr, 0xffffffff);
462	mask &= pci_conf_read_32(fun, addr);
463
464	/* Restore the original value. */
465	pci_conf_write_32(fun, addr, val);
466	val = pci_conf_read_32(fun, addr);
467
468	range_size = pci_bar_mask_to_size(mask);
469
470	if (addrw64) {
471	range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) \|
472	(val & 0xfffffff0);
473	} else {
474	range_addr = (val & 0xfffffff0);
475	}
476
477	if (range_addr != 0) {
478	ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
479	", size = %x", fun->fnode->name, range_addr,
480	(unsigned int) range_size);
481	}
482
483	pci_add_range(fun, range_addr, range_size, io);
484
485	if (addrw64)
486	return addr + 8;
487
488	return addr + 4;
489	}
490
491	void pci_add_interrupt(pci_fun_t *fun, int irq)
492	{
493	hw_resource_list_t *hw_res_list = &fun->hw_resources;
494	hw_resource_t *hw_resources = hw_res_list->resources;
495	size_t count = hw_res_list->count;
496
497	assert(NULL != hw_resources);
498	assert(count < PCI_MAX_HW_RES);
499
500	hw_resources[count].type = INTERRUPT;
501	hw_resources[count].res.interrupt.irq = irq;
502
503	hw_res_list->count++;
504
505	ddf_msg(LVL_NOTE, "Function %s uses irq %x.", fun->fnode->name, irq);
506	}
507
508	void pci_read_interrupt(pci_fun_t *fun)
509	{
510	uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
511	if (irq != 0xff)
512	pci_add_interrupt(fun, irq);
513	}
514
515	/** Enumerate (recursively) and register the devices connected to a pci bus.
516	*
517	* @param bus Host-to-PCI bridge
518	* @param bus_num Bus number
519	*/
520	void pci_bus_scan(pci_bus_t *bus, int bus_num)
521	{
522	ddf_fun_t *fnode;
523	pci_fun_t *fun;
524
525	int child_bus = 0;
526	int dnum, fnum;
527	bool multi;
528	uint8_t header_type;
529
530	fun = pci_fun_new(bus);
531
532	for (dnum = 0; dnum < 32; dnum++) {
533	multi = true;
534	for (fnum = 0; multi && fnum < 8; fnum++) {
535	pci_fun_init(fun, bus_num, dnum, fnum);
536	if (fun->vendor_id == 0xffff) {
537	/*
538	* The device is not present, go on scanning the
539	* bus.
540	*/
541	if (fnum == 0)
542	break;
543	else
544	continue;
545	}
546
547	header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
548	if (fnum == 0) {
549	/* Is the device multifunction? */
550	multi = header_type >> 7;
551	}
552	/* Clear the multifunction bit. */
553	header_type = header_type & 0x7F;
554
555	char *fun_name = pci_fun_create_name(fun);
556	if (fun_name == NULL) {
557	ddf_msg(LVL_ERROR, "Out of memory.");
558	return;
559	}
560
561	fnode = ddf_fun_create(bus->dnode, fun_inner, fun_name);
562	free(fun_name);
563	if (fnode == NULL) {
564	ddf_msg(LVL_ERROR, "Failed creating function.");
565	return;
566	}
567
568	fun->fnode = fnode;
569
570	pci_alloc_resource_list(fun);
571	pci_read_bars(fun);
572	pci_read_interrupt(fun);
573
574	fnode->ops = &pci_fun_ops;
575	fnode->driver_data = fun;
576
577	ddf_msg(LVL_DEBUG, "Adding new function %s.",
578	fnode->name);
579
580	pci_fun_create_match_ids(fun);
581
582	if (ddf_fun_bind(fnode) != EOK) {
583	pci_clean_resource_list(fun);
584	clean_match_ids(&fnode->match_ids);
585	free((char *) fnode->name);
586	fnode->name = NULL;
587	continue;
588	}
589
590	if (header_type == PCI_HEADER_TYPE_BRIDGE \|\|
591	header_type == PCI_HEADER_TYPE_CARDBUS) {
592	child_bus = pci_conf_read_8(fun,
593	PCI_BRIDGE_SEC_BUS_NUM);
594	ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
595	"bridge, secondary bus number = %d.",
596	bus_num);
597	if (child_bus > bus_num)
598	pci_bus_scan(bus, child_bus);
599	}
600
601	fun = pci_fun_new(bus);
602	}
603	}
604
605	if (fun->vendor_id == 0xffff) {
606	/* Free the auxiliary function structure. */
607	pci_fun_delete(fun);
608	}
609	}
610
611	static int pci_add_device(ddf_dev_t *dnode)
612	{
613	pci_bus_t *bus = NULL;
614	ddf_fun_t *ctl = NULL;
615	bool got_res = false;
616	int rc;
617
618	ddf_msg(LVL_DEBUG, "pci_add_device");
619	dnode->parent_sess = NULL;
620
621	bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
622	if (bus == NULL) {
623	ddf_msg(LVL_ERROR, "pci_add_device allocation failed.");
624	rc = ENOMEM;
625	goto fail;
626	}
627	fibril_mutex_initialize(&bus->conf_mutex);
628
629	bus->dnode = dnode;
630	dnode->driver_data = bus;
631
632	dnode->parent_sess = devman_parent_device_connect(EXCHANGE_SERIALIZE,
633	dnode->handle, IPC_FLAG_BLOCKING);
634	if (!dnode->parent_sess) {
635	ddf_msg(LVL_ERROR, "pci_add_device failed to connect to the "
636	"parent driver.");
637	rc = ENOENT;
638	goto fail;
639	}
640
641	hw_resource_list_t hw_resources;
642
643	rc = hw_res_get_resource_list(dnode->parent_sess, &hw_resources);
644	if (rc != EOK) {
645	ddf_msg(LVL_ERROR, "pci_add_device failed to get hw resources "
646	"for the device.");
647	goto fail;
648	}
649	got_res = true;
650
651	ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
652	hw_resources.resources[0].res.io_range.address);
653
654	assert(hw_resources.count > 0);
655	assert(hw_resources.resources[0].type == IO_RANGE);
656	assert(hw_resources.resources[0].res.io_range.size == 8);
657
658	bus->conf_io_addr =
659	(uint32_t) hw_resources.resources[0].res.io_range.address;
660
661	if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8,
662	&bus->conf_addr_port)) {
663	ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
664	rc = EADDRNOTAVAIL;
665	goto fail;
666	}
667	bus->conf_data_port = (char *) bus->conf_addr_port + 4;
668
669	/* Make the bus device more visible. It has no use yet. */
670	ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
671
672	ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
673	if (ctl == NULL) {
674	ddf_msg(LVL_ERROR, "Failed creating control function.");
675	rc = ENOMEM;
676	goto fail;
677	}
678
679	rc = ddf_fun_bind(ctl);
680	if (rc != EOK) {
681	ddf_msg(LVL_ERROR, "Failed binding control function.");
682	goto fail;
683	}
684
685	/* Enumerate functions. */
686	ddf_msg(LVL_DEBUG, "Scanning the bus");
687	pci_bus_scan(bus, 0);
688
689	hw_res_clean_resource_list(&hw_resources);
690
691	return EOK;
692
693	fail:
694	if (dnode->parent_sess)
695	async_hangup(dnode->parent_sess);
696
697	if (got_res)
698	hw_res_clean_resource_list(&hw_resources);
699
700	if (ctl != NULL)
701	ddf_fun_destroy(ctl);
702
703	return rc;
704	}
705
706	static int pci_fun_online(ddf_fun_t *fun)
707	{
708	ddf_msg(LVL_DEBUG, "pci_fun_online()");
709	return ddf_fun_online(fun);
710	}
711
712	static int pci_fun_offline(ddf_fun_t *fun)
713	{
714	ddf_msg(LVL_DEBUG, "pci_fun_offline()");
715	return ddf_fun_offline(fun);
716	}
717
718	static void pciintel_init(void)
719	{
720	ddf_log_init(NAME, LVL_ERROR);
721	pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
722	pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
723	}
724
725	pci_fun_t pci_fun_new(pci_bus_t bus)
726	{
727	pci_fun_t *fun;
728
729	fun = (pci_fun_t *) calloc(1, sizeof(pci_fun_t));
730	if (fun == NULL)
731	return NULL;
732
733	fun->busptr = bus;
734	return fun;
735	}
736
737	void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
738	{
739	fun->bus = bus;
740	fun->dev = dev;
741	fun->fn = fn;
742	fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
743	fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
744	fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
745	fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
746	fun->prog_if = pci_conf_read_8(fun, PCI_PROG_IF);
747	fun->revision = pci_conf_read_8(fun, PCI_REVISION_ID);
748	}
749
750	void pci_fun_delete(pci_fun_t *fun)
751	{
752	assert(fun != NULL);
753	hw_res_clean_resource_list(&fun->hw_resources);
754	free(fun);
755	}
756
757	char pci_fun_create_name(pci_fun_t fun)
758	{
759	char *name = NULL;
760
761	asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
762	fun->fn);
763	return name;
764	}
765
766	bool pci_alloc_resource_list(pci_fun_t *fun)
767	{
768	fun->hw_resources.resources = fun->resources;
769	return true;
770	}
771
772	void pci_clean_resource_list(pci_fun_t *fun)
773	{
774	fun->hw_resources.resources = NULL;
775	}
776
777	/** Read the base address registers (BARs) of the function and add the addresses
778	* to its HW resource list.
779	*
780	* @param fun PCI function
781	*/
782	void pci_read_bars(pci_fun_t *fun)
783	{
784	/*
785	* Position of the BAR in the PCI configuration address space of the
786	* device.
787	*/
788	int addr = PCI_BASE_ADDR_0;
789
790	while (addr <= PCI_BASE_ADDR_5)
791	addr = pci_read_bar(fun, addr);
792	}
793
794	size_t pci_bar_mask_to_size(uint32_t mask)
795	{
796	size_t size = mask & ~(mask - 1);
797	return size;
798	}
799
800	int main(int argc, char *argv[])
801	{
802	printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
803	pciintel_init();
804	return ddf_driver_main(&pci_driver);
805	}
806
807	/**
808	* @}
809	*/

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