source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ a1b7e80

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since a1b7e80 was 5f6e25e, checked in by Jiri Svoboda <jiri@…>, 14 years ago

Leave it up to DDF to free driver-specific data. This makes it possible
to ensure soft state is not freed during calls to driver entry points.

This requires some driver changes:

  • minimum change is not to free() driver-data structures (ddf_fun_t.driver_data and ddf_dev_t.driver_data)
  • ideally allocate using ddf_dev_data_alloc(), ddf_fun_data_alloc()

I tried fixing existing drivers accordingly (mostly the minimalistic
change variant), but could have missed something.
  • Property mode set to 100644
File size: 17.3 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <stdio.h>
41#include <errno.h>
42#include <bool.h>
43#include <fibril_synch.h>
44#include <str.h>
45#include <ctype.h>
46#include <macros.h>
47#include <str_error.h>
48
49#include <ddf/driver.h>
50#include <ddf/log.h>
51#include <devman.h>
52#include <ipc/devman.h>
53#include <ipc/dev_iface.h>
54#include <ipc/irc.h>
55#include <ns.h>
56#include <ipc/services.h>
57#include <sysinfo.h>
58#include <ops/hw_res.h>
59#include <device/hw_res.h>
60#include <ddi.h>
61#include <libarch/ddi.h>
62#include <pci_dev_iface.h>
63
64#include "pci.h"
65
66#define NAME "pciintel"
67
68#define CONF_ADDR(bus, dev, fn, reg) \
69 ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
70
71/** Obtain PCI function soft-state from DDF function node */
72#define PCI_FUN(fnode) ((pci_fun_t *) (fnode)->driver_data)
73
74/** Obtain PCI bus soft-state from DDF device node */
75#define PCI_BUS(dnode) ((pci_bus_t *) (dnode)->driver_data)
76
77/** Obtain PCI bus soft-state from function soft-state */
78#define PCI_BUS_FROM_FUN(fun) ((fun)->busptr)
79
80static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
81{
82 pci_fun_t *fun = PCI_FUN(fnode);
83
84 if (fun == NULL)
85 return NULL;
86 return &fun->hw_resources;
87}
88
89static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
90{
91 /* This is an old ugly way, copied from ne2000 driver */
92 assert(fnode);
93 pci_fun_t *dev_data = (pci_fun_t *) fnode->driver_data;
94
95 sysarg_t apic;
96 sysarg_t i8259;
97
98 async_sess_t *irc_sess = NULL;
99
100 if (((sysinfo_get_value("apic", &apic) == EOK) && (apic))
101 || ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259))) {
102 irc_sess = service_connect_blocking(EXCHANGE_SERIALIZE,
103 SERVICE_IRC, 0, 0);
104 }
105
106 if (!irc_sess)
107 return false;
108
109 size_t i = 0;
110 hw_resource_list_t *res = &dev_data->hw_resources;
111 for (; i < res->count; i++) {
112 if (res->resources[i].type == INTERRUPT) {
113 const int irq = res->resources[i].res.interrupt.irq;
114
115 async_exch_t *exch = async_exchange_begin(irc_sess);
116 const int rc =
117 async_req_1_0(exch, IRC_ENABLE_INTERRUPT, irq);
118 async_exchange_end(exch);
119
120 if (rc != EOK) {
121 async_hangup(irc_sess);
122 return false;
123 }
124 }
125 }
126
127 async_hangup(irc_sess);
128 return true;
129}
130
131static int pci_config_space_write_32(ddf_fun_t *fun, uint32_t address,
132 uint32_t data)
133{
134 if (address > 252)
135 return EINVAL;
136 pci_conf_write_32(PCI_FUN(fun), address, data);
137 return EOK;
138}
139
140static int pci_config_space_write_16(
141 ddf_fun_t *fun, uint32_t address, uint16_t data)
142{
143 if (address > 254)
144 return EINVAL;
145 pci_conf_write_16(PCI_FUN(fun), address, data);
146 return EOK;
147}
148
149static int pci_config_space_write_8(
150 ddf_fun_t *fun, uint32_t address, uint8_t data)
151{
152 if (address > 255)
153 return EINVAL;
154 pci_conf_write_8(PCI_FUN(fun), address, data);
155 return EOK;
156}
157
158static int pci_config_space_read_32(
159 ddf_fun_t *fun, uint32_t address, uint32_t *data)
160{
161 if (address > 252)
162 return EINVAL;
163 *data = pci_conf_read_32(PCI_FUN(fun), address);
164 return EOK;
165}
166
167static int pci_config_space_read_16(
168 ddf_fun_t *fun, uint32_t address, uint16_t *data)
169{
170 if (address > 254)
171 return EINVAL;
172 *data = pci_conf_read_16(PCI_FUN(fun), address);
173 return EOK;
174}
175
176static int pci_config_space_read_8(
177 ddf_fun_t *fun, uint32_t address, uint8_t *data)
178{
179 if (address > 255)
180 return EINVAL;
181 *data = pci_conf_read_8(PCI_FUN(fun), address);
182 return EOK;
183}
184
185static hw_res_ops_t pciintel_hw_res_ops = {
186 &pciintel_get_resources,
187 &pciintel_enable_interrupt
188};
189
190static pci_dev_iface_t pci_dev_ops = {
191 .config_space_read_8 = &pci_config_space_read_8,
192 .config_space_read_16 = &pci_config_space_read_16,
193 .config_space_read_32 = &pci_config_space_read_32,
194 .config_space_write_8 = &pci_config_space_write_8,
195 .config_space_write_16 = &pci_config_space_write_16,
196 .config_space_write_32 = &pci_config_space_write_32
197};
198
199static ddf_dev_ops_t pci_fun_ops = {
200 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
201 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
202};
203
204static int pci_add_device(ddf_dev_t *);
205
206/** PCI bus driver standard operations */
207static driver_ops_t pci_ops = {
208 .add_device = &pci_add_device
209};
210
211/** PCI bus driver structure */
212static driver_t pci_driver = {
213 .name = NAME,
214 .driver_ops = &pci_ops
215};
216
217static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
218{
219 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
220
221 fibril_mutex_lock(&bus->conf_mutex);
222
223 uint32_t conf_addr;
224 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
225 void *addr = bus->conf_data_port + (reg & 3);
226
227 pio_write_32(bus->conf_addr_port, conf_addr);
228
229 switch (len) {
230 case 1:
231 buf[0] = pio_read_8(addr);
232 break;
233 case 2:
234 ((uint16_t *) buf)[0] = pio_read_16(addr);
235 break;
236 case 4:
237 ((uint32_t *) buf)[0] = pio_read_32(addr);
238 break;
239 }
240
241 fibril_mutex_unlock(&bus->conf_mutex);
242}
243
244static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
245{
246 pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
247
248 fibril_mutex_lock(&bus->conf_mutex);
249
250 uint32_t conf_addr;
251 conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
252 void *addr = bus->conf_data_port + (reg & 3);
253
254 pio_write_32(bus->conf_addr_port, conf_addr);
255
256 switch (len) {
257 case 1:
258 pio_write_8(addr, buf[0]);
259 break;
260 case 2:
261 pio_write_16(addr, ((uint16_t *) buf)[0]);
262 break;
263 case 4:
264 pio_write_32(addr, ((uint32_t *) buf)[0]);
265 break;
266 }
267
268 fibril_mutex_unlock(&bus->conf_mutex);
269}
270
271uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
272{
273 uint8_t res;
274 pci_conf_read(fun, reg, &res, 1);
275 return res;
276}
277
278uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
279{
280 uint16_t res;
281 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
282 return res;
283}
284
285uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
286{
287 uint32_t res;
288 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
289 return res;
290}
291
292void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
293{
294 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
295}
296
297void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
298{
299 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
300}
301
302void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
303{
304 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
305}
306
307void pci_fun_create_match_ids(pci_fun_t *fun)
308{
309 char *match_id_str;
310 int rc;
311
312 asprintf(&match_id_str, "pci/ven=%04x&dev=%04x",
313 fun->vendor_id, fun->device_id);
314
315 if (match_id_str == NULL) {
316 ddf_msg(LVL_ERROR, "Out of memory creating match ID.");
317 return;
318 }
319
320 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
321 if (rc != EOK) {
322 ddf_msg(LVL_ERROR, "Failed adding match ID: %s",
323 str_error(rc));
324 }
325
326 free(match_id_str);
327
328 /* TODO add more ids (with subsys ids, using class id etc.) */
329}
330
331void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
332 bool io)
333{
334 hw_resource_list_t *hw_res_list = &fun->hw_resources;
335 hw_resource_t *hw_resources = hw_res_list->resources;
336 size_t count = hw_res_list->count;
337
338 assert(hw_resources != NULL);
339 assert(count < PCI_MAX_HW_RES);
340
341 if (io) {
342 hw_resources[count].type = IO_RANGE;
343 hw_resources[count].res.io_range.address = range_addr;
344 hw_resources[count].res.io_range.size = range_size;
345 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
346 } else {
347 hw_resources[count].type = MEM_RANGE;
348 hw_resources[count].res.mem_range.address = range_addr;
349 hw_resources[count].res.mem_range.size = range_size;
350 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
351 }
352
353 hw_res_list->count++;
354}
355
356/** Read the base address register (BAR) of the device and if it contains valid
357 * address add it to the devices hw resource list.
358 *
359 * @param fun PCI function
360 * @param addr The address of the BAR in the PCI configuration address space of
361 * the device
362 * @return The addr the address of the BAR which should be read next
363 */
364int pci_read_bar(pci_fun_t *fun, int addr)
365{
366 /* Value of the BAR */
367 uint32_t val, mask;
368 /* IO space address */
369 bool io;
370 /* 64-bit wide address */
371 bool addrw64;
372
373 /* Size of the io or memory range specified by the BAR */
374 size_t range_size;
375 /* Beginning of the io or memory range specified by the BAR */
376 uint64_t range_addr;
377
378 /* Get the value of the BAR. */
379 val = pci_conf_read_32(fun, addr);
380
381#define IO_MASK (~0x3)
382#define MEM_MASK (~0xf)
383
384 io = (bool) (val & 1);
385 if (io) {
386 addrw64 = false;
387 mask = IO_MASK;
388 } else {
389 mask = MEM_MASK;
390 switch ((val >> 1) & 3) {
391 case 0:
392 addrw64 = false;
393 break;
394 case 2:
395 addrw64 = true;
396 break;
397 default:
398 /* reserved, go to the next BAR */
399 return addr + 4;
400 }
401 }
402
403 /* Get the address mask. */
404 pci_conf_write_32(fun, addr, 0xffffffff);
405 mask &= pci_conf_read_32(fun, addr);
406
407 /* Restore the original value. */
408 pci_conf_write_32(fun, addr, val);
409 val = pci_conf_read_32(fun, addr);
410
411 range_size = pci_bar_mask_to_size(mask);
412
413 if (addrw64) {
414 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
415 (val & 0xfffffff0);
416 } else {
417 range_addr = (val & 0xfffffff0);
418 }
419
420 if (range_addr != 0) {
421 ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
422 ", size = %x", fun->fnode->name, range_addr,
423 (unsigned int) range_size);
424 }
425
426 pci_add_range(fun, range_addr, range_size, io);
427
428 if (addrw64)
429 return addr + 8;
430
431 return addr + 4;
432}
433
434void pci_add_interrupt(pci_fun_t *fun, int irq)
435{
436 hw_resource_list_t *hw_res_list = &fun->hw_resources;
437 hw_resource_t *hw_resources = hw_res_list->resources;
438 size_t count = hw_res_list->count;
439
440 assert(NULL != hw_resources);
441 assert(count < PCI_MAX_HW_RES);
442
443 hw_resources[count].type = INTERRUPT;
444 hw_resources[count].res.interrupt.irq = irq;
445
446 hw_res_list->count++;
447
448 ddf_msg(LVL_NOTE, "Function %s uses irq %x.", fun->fnode->name, irq);
449}
450
451void pci_read_interrupt(pci_fun_t *fun)
452{
453 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
454 if (irq != 0xff)
455 pci_add_interrupt(fun, irq);
456}
457
458/** Enumerate (recursively) and register the devices connected to a pci bus.
459 *
460 * @param bus Host-to-PCI bridge
461 * @param bus_num Bus number
462 */
463void pci_bus_scan(pci_bus_t *bus, int bus_num)
464{
465 ddf_fun_t *fnode;
466 pci_fun_t *fun;
467
468 int child_bus = 0;
469 int dnum, fnum;
470 bool multi;
471 uint8_t header_type;
472
473 fun = pci_fun_new(bus);
474
475 for (dnum = 0; dnum < 32; dnum++) {
476 multi = true;
477 for (fnum = 0; multi && fnum < 8; fnum++) {
478 pci_fun_init(fun, bus_num, dnum, fnum);
479 fun->vendor_id = pci_conf_read_16(fun,
480 PCI_VENDOR_ID);
481 fun->device_id = pci_conf_read_16(fun,
482 PCI_DEVICE_ID);
483 if (fun->vendor_id == 0xffff) {
484 /*
485 * The device is not present, go on scanning the
486 * bus.
487 */
488 if (fnum == 0)
489 break;
490 else
491 continue;
492 }
493
494 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
495 if (fnum == 0) {
496 /* Is the device multifunction? */
497 multi = header_type >> 7;
498 }
499 /* Clear the multifunction bit. */
500 header_type = header_type & 0x7F;
501
502 char *fun_name = pci_fun_create_name(fun);
503 if (fun_name == NULL) {
504 ddf_msg(LVL_ERROR, "Out of memory.");
505 return;
506 }
507
508 fnode = ddf_fun_create(bus->dnode, fun_inner, fun_name);
509 if (fnode == NULL) {
510 ddf_msg(LVL_ERROR, "Failed creating function.");
511 return;
512 }
513
514 free(fun_name);
515 fun->fnode = fnode;
516
517 pci_alloc_resource_list(fun);
518 pci_read_bars(fun);
519 pci_read_interrupt(fun);
520
521 fnode->ops = &pci_fun_ops;
522 fnode->driver_data = fun;
523
524 ddf_msg(LVL_DEBUG, "Adding new function %s.",
525 fnode->name);
526
527 pci_fun_create_match_ids(fun);
528
529 if (ddf_fun_bind(fnode) != EOK) {
530 pci_clean_resource_list(fun);
531 clean_match_ids(&fnode->match_ids);
532 free((char *) fnode->name);
533 fnode->name = NULL;
534 continue;
535 }
536
537 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
538 header_type == PCI_HEADER_TYPE_CARDBUS) {
539 child_bus = pci_conf_read_8(fun,
540 PCI_BRIDGE_SEC_BUS_NUM);
541 ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
542 "bridge, secondary bus number = %d.",
543 bus_num);
544 if (child_bus > bus_num)
545 pci_bus_scan(bus, child_bus);
546 }
547
548 fun = pci_fun_new(bus);
549 }
550 }
551
552 if (fun->vendor_id == 0xffff) {
553 /* Free the auxiliary function structure. */
554 pci_fun_delete(fun);
555 }
556}
557
558static int pci_add_device(ddf_dev_t *dnode)
559{
560 pci_bus_t *bus = NULL;
561 ddf_fun_t *ctl = NULL;
562 bool got_res = false;
563 int rc;
564
565 ddf_msg(LVL_DEBUG, "pci_add_device");
566 dnode->parent_sess = NULL;
567
568 bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
569 if (bus == NULL) {
570 ddf_msg(LVL_ERROR, "pci_add_device allocation failed.");
571 rc = ENOMEM;
572 goto fail;
573 }
574 fibril_mutex_initialize(&bus->conf_mutex);
575
576 bus->dnode = dnode;
577 dnode->driver_data = bus;
578
579 dnode->parent_sess = devman_parent_device_connect(EXCHANGE_SERIALIZE,
580 dnode->handle, IPC_FLAG_BLOCKING);
581 if (!dnode->parent_sess) {
582 ddf_msg(LVL_ERROR, "pci_add_device failed to connect to the "
583 "parent driver.");
584 rc = ENOENT;
585 goto fail;
586 }
587
588 hw_resource_list_t hw_resources;
589
590 rc = hw_res_get_resource_list(dnode->parent_sess, &hw_resources);
591 if (rc != EOK) {
592 ddf_msg(LVL_ERROR, "pci_add_device failed to get hw resources "
593 "for the device.");
594 goto fail;
595 }
596 got_res = true;
597
598 ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
599 hw_resources.resources[0].res.io_range.address);
600
601 assert(hw_resources.count > 0);
602 assert(hw_resources.resources[0].type == IO_RANGE);
603 assert(hw_resources.resources[0].res.io_range.size == 8);
604
605 bus->conf_io_addr =
606 (uint32_t) hw_resources.resources[0].res.io_range.address;
607
608 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8,
609 &bus->conf_addr_port)) {
610 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
611 rc = EADDRNOTAVAIL;
612 goto fail;
613 }
614 bus->conf_data_port = (char *) bus->conf_addr_port + 4;
615
616 /* Make the bus device more visible. It has no use yet. */
617 ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
618
619 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
620 if (ctl == NULL) {
621 ddf_msg(LVL_ERROR, "Failed creating control function.");
622 rc = ENOMEM;
623 goto fail;
624 }
625
626 rc = ddf_fun_bind(ctl);
627 if (rc != EOK) {
628 ddf_msg(LVL_ERROR, "Failed binding control function.");
629 goto fail;
630 }
631
632 /* Enumerate functions. */
633 ddf_msg(LVL_DEBUG, "Scanning the bus");
634 pci_bus_scan(bus, 0);
635
636 hw_res_clean_resource_list(&hw_resources);
637
638 return EOK;
639
640fail:
641 if (dnode->parent_sess)
642 async_hangup(dnode->parent_sess);
643
644 if (got_res)
645 hw_res_clean_resource_list(&hw_resources);
646
647 if (ctl != NULL)
648 ddf_fun_destroy(ctl);
649
650 return rc;
651}
652
653static void pciintel_init(void)
654{
655 ddf_log_init(NAME, LVL_ERROR);
656 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
657 pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
658}
659
660pci_fun_t *pci_fun_new(pci_bus_t *bus)
661{
662 pci_fun_t *fun;
663
664 fun = (pci_fun_t *) calloc(1, sizeof(pci_fun_t));
665 if (fun == NULL)
666 return NULL;
667
668 fun->busptr = bus;
669 return fun;
670}
671
672void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
673{
674 fun->bus = bus;
675 fun->dev = dev;
676 fun->fn = fn;
677}
678
679void pci_fun_delete(pci_fun_t *fun)
680{
681 assert(fun != NULL);
682 hw_res_clean_resource_list(&fun->hw_resources);
683 free(fun);
684}
685
686char *pci_fun_create_name(pci_fun_t *fun)
687{
688 char *name = NULL;
689
690 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
691 fun->fn);
692 return name;
693}
694
695bool pci_alloc_resource_list(pci_fun_t *fun)
696{
697 fun->hw_resources.resources =
698 (hw_resource_t *) malloc(PCI_MAX_HW_RES * sizeof(hw_resource_t));
699 return fun->hw_resources.resources != NULL;
700}
701
702void pci_clean_resource_list(pci_fun_t *fun)
703{
704 if (fun->hw_resources.resources != NULL) {
705 free(fun->hw_resources.resources);
706 fun->hw_resources.resources = NULL;
707 }
708}
709
710/** Read the base address registers (BARs) of the function and add the addresses
711 * to its HW resource list.
712 *
713 * @param fun PCI function
714 */
715void pci_read_bars(pci_fun_t *fun)
716{
717 /*
718 * Position of the BAR in the PCI configuration address space of the
719 * device.
720 */
721 int addr = PCI_BASE_ADDR_0;
722
723 while (addr <= PCI_BASE_ADDR_5)
724 addr = pci_read_bar(fun, addr);
725}
726
727size_t pci_bar_mask_to_size(uint32_t mask)
728{
729 size_t size = mask & ~(mask - 1);
730 return size;
731}
732
733int main(int argc, char *argv[])
734{
735 printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
736 pciintel_init();
737 return ddf_driver_main(&pci_driver);
738}
739
740/**
741 * @}
742 */
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