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source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ 90478727

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Last change on this file since 90478727 was 690d2e7, checked in by Jan Vesely <jano.vesely@…>, 14 years ago
pci: intel pci is always little endian.
Property mode set to `100644`
File size: 20.1 KB

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1	/*
2	* Copyright (c) 2010 Lenka Trochtova
3	* Copyright (c) 2011 Jiri Svoboda
4	* All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	*
10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/
29
30	/**
31	* @defgroup pciintel pci bus driver for intel method 1.
32	* @brief HelenOS root pci bus driver for intel method 1.
33	* @{
34	*/
35
36	/** @file
37	*/
38
39	#include <assert.h>
40	#include <byteorder.h>
41	#include <stdio.h>
42	#include <errno.h>
43	#include <bool.h>
44	#include <fibril_synch.h>
45	#include <str.h>
46	#include <ctype.h>
47	#include <macros.h>
48	#include <str_error.h>
49
50	#include <ddf/driver.h>
51	#include <ddf/log.h>
52	#include <devman.h>
53	#include <ipc/devman.h>
54	#include <ipc/dev_iface.h>
55	#include <ipc/irc.h>
56	#include <ns.h>
57	#include <ipc/services.h>
58	#include <sysinfo.h>
59	#include <ops/hw_res.h>
60	#include <device/hw_res.h>
61	#include <ddi.h>
62	#include <libarch/ddi.h>
63	#include <pci_dev_iface.h>
64
65	#include "pci.h"
66
67	#define NAME "pciintel"
68
69	#define CONF_ADDR(bus, dev, fn, reg) \
70	((1 << 31) \| (bus << 16) \| (dev << 11) \| (fn << 8) \| (reg & ~3))
71
72	/** Obtain PCI function soft-state from DDF function node */
73	#define PCI_FUN(fnode) ((pci_fun_t *) (fnode)->driver_data)
74
75	/** Obtain PCI bus soft-state from DDF device node */
76	#define PCI_BUS(dnode) ((pci_bus_t *) (dnode)->driver_data)
77
78	/** Obtain PCI bus soft-state from function soft-state */
79	#define PCI_BUS_FROM_FUN(fun) ((fun)->busptr)
80
81	/** Max is 47, align to something nice. */
82	#define ID_MAX_STR_LEN 50
83
84	static hw_resource_list_t pciintel_get_resources(ddf_fun_t fnode)
85	{
86	pci_fun_t *fun = PCI_FUN(fnode);
87
88	if (fun == NULL)
89	return NULL;
90	return &fun->hw_resources;
91	}
92
93	static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
94	{
95	/* This is an old ugly way */
96	assert(fnode);
97	pci_fun_t dev_data = (pci_fun_t ) fnode->driver_data;
98
99	sysarg_t apic;
100	sysarg_t i8259;
101
102	async_sess_t *irc_sess = NULL;
103
104	if (((sysinfo_get_value("apic", &apic) == EOK) && (apic))
105	\|\| ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259))) {
106	irc_sess = service_connect_blocking(EXCHANGE_SERIALIZE,
107	SERVICE_IRC, 0, 0);
108	}
109
110	if (!irc_sess)
111	return false;
112
113	size_t i = 0;
114	hw_resource_list_t *res = &dev_data->hw_resources;
115	for (; i < res->count; i++) {
116	if (res->resources[i].type == INTERRUPT) {
117	const int irq = res->resources[i].res.interrupt.irq;
118
119	async_exch_t *exch = async_exchange_begin(irc_sess);
120	const int rc =
121	async_req_1_0(exch, IRC_ENABLE_INTERRUPT, irq);
122	async_exchange_end(exch);
123
124	if (rc != EOK) {
125	async_hangup(irc_sess);
126	return false;
127	}
128	}
129	}
130
131	async_hangup(irc_sess);
132	return true;
133	}
134
135	static int pci_config_space_write_32(ddf_fun_t *fun, uint32_t address,
136	uint32_t data)
137	{
138	if (address > 252)
139	return EINVAL;
140	pci_conf_write_32(PCI_FUN(fun), address, data);
141	return EOK;
142	}
143
144	static int pci_config_space_write_16(
145	ddf_fun_t *fun, uint32_t address, uint16_t data)
146	{
147	if (address > 254)
148	return EINVAL;
149	pci_conf_write_16(PCI_FUN(fun), address, data);
150	return EOK;
151	}
152
153	static int pci_config_space_write_8(
154	ddf_fun_t *fun, uint32_t address, uint8_t data)
155	{
156	if (address > 255)
157	return EINVAL;
158	pci_conf_write_8(PCI_FUN(fun), address, data);
159	return EOK;
160	}
161
162	static int pci_config_space_read_32(
163	ddf_fun_t fun, uint32_t address, uint32_t data)
164	{
165	if (address > 252)
166	return EINVAL;
167	*data = pci_conf_read_32(PCI_FUN(fun), address);
168	return EOK;
169	}
170
171	static int pci_config_space_read_16(
172	ddf_fun_t fun, uint32_t address, uint16_t data)
173	{
174	if (address > 254)
175	return EINVAL;
176	*data = pci_conf_read_16(PCI_FUN(fun), address);
177	return EOK;
178	}
179
180	static int pci_config_space_read_8(
181	ddf_fun_t fun, uint32_t address, uint8_t data)
182	{
183	if (address > 255)
184	return EINVAL;
185	*data = pci_conf_read_8(PCI_FUN(fun), address);
186	return EOK;
187	}
188
189	static hw_res_ops_t pciintel_hw_res_ops = {
190	.get_resource_list = &pciintel_get_resources,
191	.enable_interrupt = &pciintel_enable_interrupt,
192	};
193
194	static pci_dev_iface_t pci_dev_ops = {
195	.config_space_read_8 = &pci_config_space_read_8,
196	.config_space_read_16 = &pci_config_space_read_16,
197	.config_space_read_32 = &pci_config_space_read_32,
198	.config_space_write_8 = &pci_config_space_write_8,
199	.config_space_write_16 = &pci_config_space_write_16,
200	.config_space_write_32 = &pci_config_space_write_32
201	};
202
203	static ddf_dev_ops_t pci_fun_ops = {
204	.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
205	.interfaces[PCI_DEV_IFACE] = &pci_dev_ops
206	};
207
208	static int pci_dev_add(ddf_dev_t *);
209	static int pci_fun_online(ddf_fun_t *);
210	static int pci_fun_offline(ddf_fun_t *);
211
212	/** PCI bus driver standard operations */
213	static driver_ops_t pci_ops = {
214	.dev_add = &pci_dev_add,
215	.fun_online = &pci_fun_online,
216	.fun_offline = &pci_fun_offline,
217	};
218
219	/** PCI bus driver structure */
220	static driver_t pci_driver = {
221	.name = NAME,
222	.driver_ops = &pci_ops
223	};
224
225	static void pci_conf_read(pci_fun_t fun, int reg, uint8_t buf, size_t len)
226	{
227	pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
228
229	fibril_mutex_lock(&bus->conf_mutex);
230
231	const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
232	void *addr = bus->conf_data_port + (reg & 3);
233
234	pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
235
236	switch (len) {
237	case 1:
238	/* No endianness change for 1 byte */
239	buf[0] = pio_read_8(addr);
240	break;
241	case 2:
242	((uint16_t *) buf)[0] = uint16_t_le2host(pio_read_16(addr));
243	break;
244	case 4:
245	((uint32_t *) buf)[0] = uint32_t_le2host(pio_read_32(addr));
246	break;
247	}
248
249	fibril_mutex_unlock(&bus->conf_mutex);
250	}
251
252	static void pci_conf_write(pci_fun_t fun, int reg, uint8_t buf, size_t len)
253	{
254	pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
255
256	fibril_mutex_lock(&bus->conf_mutex);
257
258	const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
259	void *addr = bus->conf_data_port + (reg & 3);
260
261	pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
262
263	switch (len) {
264	case 1:
265	/* No endianness change for 1 byte */
266	pio_write_8(addr, buf[0]);
267	break;
268	case 2:
269	pio_write_16(addr, host2uint16_t_le(((uint16_t *) buf)[0]));
270	break;
271	case 4:
272	pio_write_32(addr, host2uint32_t_le(((uint32_t *) buf)[0]));
273	break;
274	}
275
276	fibril_mutex_unlock(&bus->conf_mutex);
277	}
278
279	uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
280	{
281	uint8_t res;
282	pci_conf_read(fun, reg, &res, 1);
283	return res;
284	}
285
286	uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
287	{
288	uint16_t res;
289	pci_conf_read(fun, reg, (uint8_t *) &res, 2);
290	return res;
291	}
292
293	uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
294	{
295	uint32_t res;
296	pci_conf_read(fun, reg, (uint8_t *) &res, 4);
297	return res;
298	}
299
300	void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
301	{
302	pci_conf_write(fun, reg, (uint8_t *) &val, 1);
303	}
304
305	void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
306	{
307	pci_conf_write(fun, reg, (uint8_t *) &val, 2);
308	}
309
310	void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
311	{
312	pci_conf_write(fun, reg, (uint8_t *) &val, 4);
313	}
314
315	void pci_fun_create_match_ids(pci_fun_t *fun)
316	{
317	int rc;
318	char match_id_str[ID_MAX_STR_LEN];
319
320	/* Vendor ID & Device ID, length(incl \0) 22 */
321	rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04x&dev=%04x",
322	fun->vendor_id, fun->device_id);
323	if (rc < 0) {
324	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
325	str_error(rc));
326	}
327
328	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
329	if (rc != EOK) {
330	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
331	}
332
333	/* Class, subclass, prog IF, revision, length(incl \0) 47 */
334	rc = snprintf(match_id_str, ID_MAX_STR_LEN,
335	"pci/class=%02x&subclass=%02x&progif=%02x&revision=%02x",
336	fun->class_code, fun->subclass_code, fun->prog_if, fun->revision);
337	if (rc < 0) {
338	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
339	str_error(rc));
340	}
341
342	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 70);
343	if (rc != EOK) {
344	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
345	}
346
347	/* Class, subclass, prog IF, length(incl \0) 35 */
348	rc = snprintf(match_id_str, ID_MAX_STR_LEN,
349	"pci/class=%02x&subclass=%02x&progif=%02x",
350	fun->class_code, fun->subclass_code, fun->prog_if);
351	if (rc < 0) {
352	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
353	str_error(rc));
354	}
355
356	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 60);
357	if (rc != EOK) {
358	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
359	}
360
361	/* Class, subclass, length(incl \0) 25 */
362	rc = snprintf(match_id_str, ID_MAX_STR_LEN,
363	"pci/class=%02x&subclass=%02x",
364	fun->class_code, fun->subclass_code);
365	if (rc < 0) {
366	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
367	str_error(rc));
368	}
369
370	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 50);
371	if (rc != EOK) {
372	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
373	}
374
375	/* Class, length(incl \0) 13 */
376	rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/class=%02x",
377	fun->class_code);
378	if (rc < 0) {
379	ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
380	str_error(rc));
381	}
382
383	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 40);
384	if (rc != EOK) {
385	ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
386	}
387
388	/* TODO add subsys ids, but those exist only in header type 0 */
389	}
390
391	void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
392	bool io)
393	{
394	hw_resource_list_t *hw_res_list = &fun->hw_resources;
395	hw_resource_t *hw_resources = hw_res_list->resources;
396	size_t count = hw_res_list->count;
397
398	assert(hw_resources != NULL);
399	assert(count < PCI_MAX_HW_RES);
400
401	if (io) {
402	hw_resources[count].type = IO_RANGE;
403	hw_resources[count].res.io_range.address = range_addr;
404	hw_resources[count].res.io_range.size = range_size;
405	hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
406	} else {
407	hw_resources[count].type = MEM_RANGE;
408	hw_resources[count].res.mem_range.address = range_addr;
409	hw_resources[count].res.mem_range.size = range_size;
410	hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
411	}
412
413	hw_res_list->count++;
414	}
415
416	/** Read the base address register (BAR) of the device and if it contains valid
417	* address add it to the devices hw resource list.
418	*
419	* @param fun PCI function
420	* @param addr The address of the BAR in the PCI configuration address space of
421	* the device
422	* @return The addr the address of the BAR which should be read next
423	*/
424	int pci_read_bar(pci_fun_t *fun, int addr)
425	{
426	/* Value of the BAR */
427	uint32_t val, mask;
428	/* IO space address */
429	bool io;
430	/* 64-bit wide address */
431	bool addrw64;
432
433	/* Size of the io or memory range specified by the BAR */
434	size_t range_size;
435	/* Beginning of the io or memory range specified by the BAR */
436	uint64_t range_addr;
437
438	/* Get the value of the BAR. */
439	val = pci_conf_read_32(fun, addr);
440
441	#define IO_MASK (~0x3)
442	#define MEM_MASK (~0xf)
443
444	io = (bool) (val & 1);
445	if (io) {
446	addrw64 = false;
447	mask = IO_MASK;
448	} else {
449	mask = MEM_MASK;
450	switch ((val >> 1) & 3) {
451	case 0:
452	addrw64 = false;
453	break;
454	case 2:
455	addrw64 = true;
456	break;
457	default:
458	/* reserved, go to the next BAR */
459	return addr + 4;
460	}
461	}
462
463	/* Get the address mask. */
464	pci_conf_write_32(fun, addr, 0xffffffff);
465	mask &= pci_conf_read_32(fun, addr);
466
467	/* Restore the original value. */
468	pci_conf_write_32(fun, addr, val);
469	val = pci_conf_read_32(fun, addr);
470
471	range_size = pci_bar_mask_to_size(mask);
472
473	if (addrw64) {
474	range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) \|
475	(val & 0xfffffff0);
476	} else {
477	range_addr = (val & 0xfffffff0);
478	}
479
480	if (range_addr != 0) {
481	ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
482	", size = %x", fun->fnode->name, range_addr,
483	(unsigned int) range_size);
484	}
485
486	pci_add_range(fun, range_addr, range_size, io);
487
488	if (addrw64)
489	return addr + 8;
490
491	return addr + 4;
492	}
493
494	void pci_add_interrupt(pci_fun_t *fun, int irq)
495	{
496	hw_resource_list_t *hw_res_list = &fun->hw_resources;
497	hw_resource_t *hw_resources = hw_res_list->resources;
498	size_t count = hw_res_list->count;
499
500	assert(NULL != hw_resources);
501	assert(count < PCI_MAX_HW_RES);
502
503	hw_resources[count].type = INTERRUPT;
504	hw_resources[count].res.interrupt.irq = irq;
505
506	hw_res_list->count++;
507
508	ddf_msg(LVL_NOTE, "Function %s uses irq %x.", fun->fnode->name, irq);
509	}
510
511	void pci_read_interrupt(pci_fun_t *fun)
512	{
513	uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
514	if (irq != 0xff)
515	pci_add_interrupt(fun, irq);
516	}
517
518	/** Enumerate (recursively) and register the devices connected to a pci bus.
519	*
520	* @param bus Host-to-PCI bridge
521	* @param bus_num Bus number
522	*/
523	void pci_bus_scan(pci_bus_t *bus, int bus_num)
524	{
525	ddf_fun_t *fnode;
526	pci_fun_t *fun;
527
528	int child_bus = 0;
529	int dnum, fnum;
530	bool multi;
531	uint8_t header_type;
532
533	fun = pci_fun_new(bus);
534
535	for (dnum = 0; dnum < 32; dnum++) {
536	multi = true;
537	for (fnum = 0; multi && fnum < 8; fnum++) {
538	pci_fun_init(fun, bus_num, dnum, fnum);
539	if (fun->vendor_id == 0xffff) {
540	/*
541	* The device is not present, go on scanning the
542	* bus.
543	*/
544	if (fnum == 0)
545	break;
546	else
547	continue;
548	}
549
550	header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
551	if (fnum == 0) {
552	/* Is the device multifunction? */
553	multi = header_type >> 7;
554	}
555	/* Clear the multifunction bit. */
556	header_type = header_type & 0x7F;
557
558	char *fun_name = pci_fun_create_name(fun);
559	if (fun_name == NULL) {
560	ddf_msg(LVL_ERROR, "Out of memory.");
561	return;
562	}
563
564	fnode = ddf_fun_create(bus->dnode, fun_inner, fun_name);
565	free(fun_name);
566	if (fnode == NULL) {
567	ddf_msg(LVL_ERROR, "Failed creating function.");
568	return;
569	}
570
571	fun->fnode = fnode;
572
573	pci_alloc_resource_list(fun);
574	pci_read_bars(fun);
575	pci_read_interrupt(fun);
576
577	fnode->ops = &pci_fun_ops;
578	fnode->driver_data = fun;
579
580	ddf_msg(LVL_DEBUG, "Adding new function %s.",
581	fnode->name);
582
583	pci_fun_create_match_ids(fun);
584
585	if (ddf_fun_bind(fnode) != EOK) {
586	pci_clean_resource_list(fun);
587	clean_match_ids(&fnode->match_ids);
588	free((char *) fnode->name);
589	fnode->name = NULL;
590	continue;
591	}
592
593	if (header_type == PCI_HEADER_TYPE_BRIDGE \|\|
594	header_type == PCI_HEADER_TYPE_CARDBUS) {
595	child_bus = pci_conf_read_8(fun,
596	PCI_BRIDGE_SEC_BUS_NUM);
597	ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
598	"bridge, secondary bus number = %d.",
599	bus_num);
600	if (child_bus > bus_num)
601	pci_bus_scan(bus, child_bus);
602	}
603
604	fun = pci_fun_new(bus);
605	}
606	}
607
608	if (fun->vendor_id == 0xffff) {
609	/* Free the auxiliary function structure. */
610	pci_fun_delete(fun);
611	}
612	}
613
614	static int pci_dev_add(ddf_dev_t *dnode)
615	{
616	pci_bus_t *bus = NULL;
617	ddf_fun_t *ctl = NULL;
618	bool got_res = false;
619	int rc;
620
621	ddf_msg(LVL_DEBUG, "pci_dev_add");
622	dnode->parent_sess = NULL;
623
624	bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
625	if (bus == NULL) {
626	ddf_msg(LVL_ERROR, "pci_dev_add allocation failed.");
627	rc = ENOMEM;
628	goto fail;
629	}
630	fibril_mutex_initialize(&bus->conf_mutex);
631
632	bus->dnode = dnode;
633	dnode->driver_data = bus;
634
635	dnode->parent_sess = devman_parent_device_connect(EXCHANGE_SERIALIZE,
636	dnode->handle, IPC_FLAG_BLOCKING);
637	if (!dnode->parent_sess) {
638	ddf_msg(LVL_ERROR, "pci_dev_add failed to connect to the "
639	"parent driver.");
640	rc = ENOENT;
641	goto fail;
642	}
643
644	hw_resource_list_t hw_resources;
645
646	rc = hw_res_get_resource_list(dnode->parent_sess, &hw_resources);
647	if (rc != EOK) {
648	ddf_msg(LVL_ERROR, "pci_dev_add failed to get hw resources "
649	"for the device.");
650	goto fail;
651	}
652	got_res = true;
653
654
655	assert(hw_resources.count > 1);
656	assert(hw_resources.resources[0].type == IO_RANGE);
657	assert(hw_resources.resources[0].res.io_range.size >= 4);
658
659	assert(hw_resources.resources[1].type == IO_RANGE);
660	assert(hw_resources.resources[1].res.io_range.size >= 4);
661
662	ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
663	hw_resources.resources[0].res.io_range.address);
664	ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
665	hw_resources.resources[1].res.io_range.address);
666
667	bus->conf_io_addr =
668	(uint32_t) hw_resources.resources[0].res.io_range.address;
669	bus->conf_io_data =
670	(uint32_t) hw_resources.resources[1].res.io_range.address;
671
672	if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 4,
673	&bus->conf_addr_port)) {
674	ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
675	rc = EADDRNOTAVAIL;
676	goto fail;
677	}
678	if (pio_enable((void *)(uintptr_t)bus->conf_io_data, 4,
679	&bus->conf_data_port)) {
680	ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
681	rc = EADDRNOTAVAIL;
682	goto fail;
683	}
684
685	/* Make the bus device more visible. It has no use yet. */
686	ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
687
688	ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
689	if (ctl == NULL) {
690	ddf_msg(LVL_ERROR, "Failed creating control function.");
691	rc = ENOMEM;
692	goto fail;
693	}
694
695	rc = ddf_fun_bind(ctl);
696	if (rc != EOK) {
697	ddf_msg(LVL_ERROR, "Failed binding control function.");
698	goto fail;
699	}
700
701	/* Enumerate functions. */
702	ddf_msg(LVL_DEBUG, "Scanning the bus");
703	pci_bus_scan(bus, 0);
704
705	hw_res_clean_resource_list(&hw_resources);
706
707	return EOK;
708
709	fail:
710	if (dnode->parent_sess)
711	async_hangup(dnode->parent_sess);
712
713	if (got_res)
714	hw_res_clean_resource_list(&hw_resources);
715
716	if (ctl != NULL)
717	ddf_fun_destroy(ctl);
718
719	return rc;
720	}
721
722	static int pci_fun_online(ddf_fun_t *fun)
723	{
724	ddf_msg(LVL_DEBUG, "pci_fun_online()");
725	return ddf_fun_online(fun);
726	}
727
728	static int pci_fun_offline(ddf_fun_t *fun)
729	{
730	ddf_msg(LVL_DEBUG, "pci_fun_offline()");
731	return ddf_fun_offline(fun);
732	}
733
734	static void pciintel_init(void)
735	{
736	ddf_log_init(NAME, LVL_ERROR);
737	pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
738	pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
739	}
740
741	pci_fun_t pci_fun_new(pci_bus_t bus)
742	{
743	pci_fun_t *fun;
744
745	fun = (pci_fun_t *) calloc(1, sizeof(pci_fun_t));
746	if (fun == NULL)
747	return NULL;
748
749	fun->busptr = bus;
750	return fun;
751	}
752
753	void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
754	{
755	fun->bus = bus;
756	fun->dev = dev;
757	fun->fn = fn;
758	fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
759	fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
760	fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
761	fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
762	fun->prog_if = pci_conf_read_8(fun, PCI_PROG_IF);
763	fun->revision = pci_conf_read_8(fun, PCI_REVISION_ID);
764	}
765
766	void pci_fun_delete(pci_fun_t *fun)
767	{
768	assert(fun != NULL);
769	hw_res_clean_resource_list(&fun->hw_resources);
770	free(fun);
771	}
772
773	char pci_fun_create_name(pci_fun_t fun)
774	{
775	char *name = NULL;
776
777	asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
778	fun->fn);
779	return name;
780	}
781
782	bool pci_alloc_resource_list(pci_fun_t *fun)
783	{
784	fun->hw_resources.resources = fun->resources;
785	return true;
786	}
787
788	void pci_clean_resource_list(pci_fun_t *fun)
789	{
790	fun->hw_resources.resources = NULL;
791	}
792
793	/** Read the base address registers (BARs) of the function and add the addresses
794	* to its HW resource list.
795	*
796	* @param fun PCI function
797	*/
798	void pci_read_bars(pci_fun_t *fun)
799	{
800	/*
801	* Position of the BAR in the PCI configuration address space of the
802	* device.
803	*/
804	int addr = PCI_BASE_ADDR_0;
805
806	while (addr <= PCI_BASE_ADDR_5)
807	addr = pci_read_bar(fun, addr);
808	}
809
810	size_t pci_bar_mask_to_size(uint32_t mask)
811	{
812	size_t size = mask & ~(mask - 1);
813	return size;
814	}
815
816	int main(int argc, char *argv[])
817	{
818	printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
819	pciintel_init();
820	return ddf_driver_main(&pci_driver);
821	}
822
823	/**
824	* @}
825	*/

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