source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ 82721f5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 82721f5 was 82721f5, checked in by Jakub Jermar <jakub@…>, 12 years ago

Use only aligned 32-bit accesses to read/write the PCI configuration data register.

  • Some platforms (e.g. Malta) cannot do smaller accesses to offset addresses.
  • Property mode set to 100644
File size: 20.8 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <byteorder.h>
41#include <stdio.h>
42#include <errno.h>
43#include <stdbool.h>
44#include <fibril_synch.h>
45#include <str.h>
46#include <ctype.h>
47#include <macros.h>
48#include <str_error.h>
49
50#include <ddf/driver.h>
51#include <ddf/log.h>
52#include <ipc/dev_iface.h>
53#include <ipc/irc.h>
54#include <ns.h>
55#include <ipc/services.h>
56#include <sysinfo.h>
57#include <ops/hw_res.h>
58#include <device/hw_res.h>
59#include <ddi.h>
60#include <pci_dev_iface.h>
61
62#include "pci.h"
63
64#define NAME "pciintel"
65
66#define CONF_ADDR(bus, dev, fn, reg) \
67 ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
68
69/** Obtain PCI function soft-state from DDF function node */
70static pci_fun_t *pci_fun(ddf_fun_t *fnode)
71{
72 return ddf_fun_data_get(fnode);
73}
74
75/** Obtain PCI bus soft-state from DDF device node */
76#if 0
77static pci_bus_t *pci_bus(ddf_dev_t *dnode)
78{
79 return ddf_dev_data_get(dnode);
80}
81#endif
82
83/** Obtain PCI bus soft-state from function soft-state */
84static pci_bus_t *pci_bus_from_fun(pci_fun_t *fun)
85{
86 return fun->busptr;
87}
88
89/** Max is 47, align to something nice. */
90#define ID_MAX_STR_LEN 50
91
92static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
93{
94 pci_fun_t *fun = pci_fun(fnode);
95
96 if (fun == NULL)
97 return NULL;
98 return &fun->hw_resources;
99}
100
101static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
102{
103 /* This is an old ugly way */
104 assert(fnode);
105 pci_fun_t *dev_data = pci_fun(fnode);
106
107 sysarg_t apic;
108 sysarg_t i8259;
109
110 async_sess_t *irc_sess = NULL;
111
112 if (((sysinfo_get_value("apic", &apic) == EOK) && (apic))
113 || ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259))) {
114 irc_sess = service_connect_blocking(EXCHANGE_SERIALIZE,
115 SERVICE_IRC, 0, 0);
116 }
117
118 if (!irc_sess)
119 return false;
120
121 size_t i = 0;
122 hw_resource_list_t *res = &dev_data->hw_resources;
123 for (; i < res->count; i++) {
124 if (res->resources[i].type == INTERRUPT) {
125 const int irq = res->resources[i].res.interrupt.irq;
126
127 async_exch_t *exch = async_exchange_begin(irc_sess);
128 const int rc =
129 async_req_1_0(exch, IRC_ENABLE_INTERRUPT, irq);
130 async_exchange_end(exch);
131
132 if (rc != EOK) {
133 async_hangup(irc_sess);
134 return false;
135 }
136 }
137 }
138
139 async_hangup(irc_sess);
140 return true;
141}
142
143static int pci_config_space_write_32(ddf_fun_t *fun, uint32_t address,
144 uint32_t data)
145{
146 if (address > 252)
147 return EINVAL;
148 pci_conf_write_32(pci_fun(fun), address, data);
149 return EOK;
150}
151
152static int pci_config_space_write_16(
153 ddf_fun_t *fun, uint32_t address, uint16_t data)
154{
155 if (address > 254)
156 return EINVAL;
157 pci_conf_write_16(pci_fun(fun), address, data);
158 return EOK;
159}
160
161static int pci_config_space_write_8(
162 ddf_fun_t *fun, uint32_t address, uint8_t data)
163{
164 if (address > 255)
165 return EINVAL;
166 pci_conf_write_8(pci_fun(fun), address, data);
167 return EOK;
168}
169
170static int pci_config_space_read_32(
171 ddf_fun_t *fun, uint32_t address, uint32_t *data)
172{
173 if (address > 252)
174 return EINVAL;
175 *data = pci_conf_read_32(pci_fun(fun), address);
176 return EOK;
177}
178
179static int pci_config_space_read_16(
180 ddf_fun_t *fun, uint32_t address, uint16_t *data)
181{
182 if (address > 254)
183 return EINVAL;
184 *data = pci_conf_read_16(pci_fun(fun), address);
185 return EOK;
186}
187
188static int pci_config_space_read_8(
189 ddf_fun_t *fun, uint32_t address, uint8_t *data)
190{
191 if (address > 255)
192 return EINVAL;
193 *data = pci_conf_read_8(pci_fun(fun), address);
194 return EOK;
195}
196
197static hw_res_ops_t pciintel_hw_res_ops = {
198 .get_resource_list = &pciintel_get_resources,
199 .enable_interrupt = &pciintel_enable_interrupt,
200};
201
202static pci_dev_iface_t pci_dev_ops = {
203 .config_space_read_8 = &pci_config_space_read_8,
204 .config_space_read_16 = &pci_config_space_read_16,
205 .config_space_read_32 = &pci_config_space_read_32,
206 .config_space_write_8 = &pci_config_space_write_8,
207 .config_space_write_16 = &pci_config_space_write_16,
208 .config_space_write_32 = &pci_config_space_write_32
209};
210
211static ddf_dev_ops_t pci_fun_ops = {
212 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
213 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
214};
215
216static int pci_dev_add(ddf_dev_t *);
217static int pci_fun_online(ddf_fun_t *);
218static int pci_fun_offline(ddf_fun_t *);
219
220/** PCI bus driver standard operations */
221static driver_ops_t pci_ops = {
222 .dev_add = &pci_dev_add,
223 .fun_online = &pci_fun_online,
224 .fun_offline = &pci_fun_offline,
225};
226
227/** PCI bus driver structure */
228static driver_t pci_driver = {
229 .name = NAME,
230 .driver_ops = &pci_ops
231};
232
233static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
234{
235 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
236 pci_bus_t *bus = pci_bus_from_fun(fun);
237 uint32_t val;
238
239 fibril_mutex_lock(&bus->conf_mutex);
240
241 pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
242
243 /*
244 * Always read full 32-bits from the PCI conf_data_port register and
245 * get the desired portion of it afterwards. Some architectures do not
246 * support shorter PIO reads offset from this register.
247 */
248 val = uint32_t_le2host(pio_read_32(bus->conf_data_port));
249
250 switch (len) {
251 case 1:
252 *buf = (uint8_t) (val >> ((reg & 3) * 8));
253 break;
254 case 2:
255 *((uint16_t *) buf) = (uint16_t) (val >> ((reg & 3)) * 8);
256 break;
257 case 4:
258 *((uint32_t *) buf) = (uint32_t) val;
259 break;
260 }
261
262 fibril_mutex_unlock(&bus->conf_mutex);
263}
264
265static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
266{
267 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
268 pci_bus_t *bus = pci_bus_from_fun(fun);
269 uint32_t val;
270
271 fibril_mutex_lock(&bus->conf_mutex);
272
273 /*
274 * Prepare to write full 32-bits to the PCI conf_data_port register.
275 * Some architectures do not support shorter PIO writes offset from this
276 * register.
277 */
278
279 if (len < 4) {
280 /*
281 * We have fewer than full 32-bits, so we need to read the
282 * missing bits first.
283 */
284 pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
285 val = uint32_t_le2host(pio_read_32(bus->conf_data_port));
286 }
287
288 switch (len) {
289 case 1:
290 val &= ~(0xffU << ((reg & 3) * 8));
291 val |= *buf << ((reg & 3) * 8);
292 break;
293 case 2:
294 val &= ~(0xffffU << ((reg & 3) * 8));
295 val |= *((uint16_t *) buf) << ((reg & 3) * 8);
296 break;
297 case 4:
298 val = *((uint32_t *) buf);
299 break;
300 }
301
302 pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
303 pio_write_32(bus->conf_data_port, host2uint32_t_le(val));
304
305 fibril_mutex_unlock(&bus->conf_mutex);
306}
307
308uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
309{
310 uint8_t res;
311 pci_conf_read(fun, reg, &res, 1);
312 return res;
313}
314
315uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
316{
317 uint16_t res;
318 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
319 return res;
320}
321
322uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
323{
324 uint32_t res;
325 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
326 return res;
327}
328
329void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
330{
331 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
332}
333
334void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
335{
336 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
337}
338
339void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
340{
341 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
342}
343
344void pci_fun_create_match_ids(pci_fun_t *fun)
345{
346 int rc;
347 char match_id_str[ID_MAX_STR_LEN];
348
349 /* Vendor ID & Device ID, length(incl \0) 22 */
350 rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04"
351 PRIx16 "&dev=%04" PRIx16, fun->vendor_id, fun->device_id);
352 if (rc < 0) {
353 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
354 str_error(rc));
355 }
356
357 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
358 if (rc != EOK) {
359 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
360 }
361
362 /* Class, subclass, prog IF, revision, length(incl \0) 47 */
363 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
364 "pci/class=%02x&subclass=%02x&progif=%02x&revision=%02x",
365 fun->class_code, fun->subclass_code, fun->prog_if, fun->revision);
366 if (rc < 0) {
367 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
368 str_error(rc));
369 }
370
371 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 70);
372 if (rc != EOK) {
373 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
374 }
375
376 /* Class, subclass, prog IF, length(incl \0) 35 */
377 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
378 "pci/class=%02x&subclass=%02x&progif=%02x",
379 fun->class_code, fun->subclass_code, fun->prog_if);
380 if (rc < 0) {
381 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
382 str_error(rc));
383 }
384
385 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 60);
386 if (rc != EOK) {
387 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
388 }
389
390 /* Class, subclass, length(incl \0) 25 */
391 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
392 "pci/class=%02x&subclass=%02x",
393 fun->class_code, fun->subclass_code);
394 if (rc < 0) {
395 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
396 str_error(rc));
397 }
398
399 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 50);
400 if (rc != EOK) {
401 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
402 }
403
404 /* Class, length(incl \0) 13 */
405 rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/class=%02x",
406 fun->class_code);
407 if (rc < 0) {
408 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
409 str_error(rc));
410 }
411
412 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 40);
413 if (rc != EOK) {
414 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
415 }
416
417 /* TODO add subsys ids, but those exist only in header type 0 */
418}
419
420void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
421 bool io)
422{
423 hw_resource_list_t *hw_res_list = &fun->hw_resources;
424 hw_resource_t *hw_resources = hw_res_list->resources;
425 size_t count = hw_res_list->count;
426
427 assert(hw_resources != NULL);
428 assert(count < PCI_MAX_HW_RES);
429
430 if (io) {
431 hw_resources[count].type = IO_RANGE;
432 hw_resources[count].res.io_range.address = range_addr;
433 hw_resources[count].res.io_range.size = range_size;
434 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
435 } else {
436 hw_resources[count].type = MEM_RANGE;
437 hw_resources[count].res.mem_range.address = range_addr;
438 hw_resources[count].res.mem_range.size = range_size;
439 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
440 }
441
442 hw_res_list->count++;
443}
444
445/** Read the base address register (BAR) of the device and if it contains valid
446 * address add it to the devices hw resource list.
447 *
448 * @param fun PCI function
449 * @param addr The address of the BAR in the PCI configuration address space of
450 * the device
451 * @return The addr the address of the BAR which should be read next
452 */
453int pci_read_bar(pci_fun_t *fun, int addr)
454{
455 /* Value of the BAR */
456 uint32_t val, mask;
457 /* IO space address */
458 bool io;
459 /* 64-bit wide address */
460 bool addrw64;
461
462 /* Size of the io or memory range specified by the BAR */
463 size_t range_size;
464 /* Beginning of the io or memory range specified by the BAR */
465 uint64_t range_addr;
466
467 /* Get the value of the BAR. */
468 val = pci_conf_read_32(fun, addr);
469
470#define IO_MASK (~0x3)
471#define MEM_MASK (~0xf)
472
473 io = (bool) (val & 1);
474 if (io) {
475 addrw64 = false;
476 mask = IO_MASK;
477 } else {
478 mask = MEM_MASK;
479 switch ((val >> 1) & 3) {
480 case 0:
481 addrw64 = false;
482 break;
483 case 2:
484 addrw64 = true;
485 break;
486 default:
487 /* reserved, go to the next BAR */
488 return addr + 4;
489 }
490 }
491
492 /* Get the address mask. */
493 pci_conf_write_32(fun, addr, 0xffffffff);
494 mask &= pci_conf_read_32(fun, addr);
495
496 /* Restore the original value. */
497 pci_conf_write_32(fun, addr, val);
498 val = pci_conf_read_32(fun, addr);
499
500 range_size = pci_bar_mask_to_size(mask);
501
502 if (addrw64) {
503 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
504 (val & 0xfffffff0);
505 } else {
506 range_addr = (val & 0xfffffff0);
507 }
508
509 if (range_addr != 0) {
510 ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
511 ", size = %x", ddf_fun_get_name(fun->fnode), range_addr,
512 (unsigned int) range_size);
513 }
514
515 pci_add_range(fun, range_addr, range_size, io);
516
517 if (addrw64)
518 return addr + 8;
519
520 return addr + 4;
521}
522
523void pci_add_interrupt(pci_fun_t *fun, int irq)
524{
525 hw_resource_list_t *hw_res_list = &fun->hw_resources;
526 hw_resource_t *hw_resources = hw_res_list->resources;
527 size_t count = hw_res_list->count;
528
529 assert(NULL != hw_resources);
530 assert(count < PCI_MAX_HW_RES);
531
532 hw_resources[count].type = INTERRUPT;
533 hw_resources[count].res.interrupt.irq = irq;
534
535 hw_res_list->count++;
536
537 ddf_msg(LVL_NOTE, "Function %s uses irq %x.", ddf_fun_get_name(fun->fnode), irq);
538}
539
540void pci_read_interrupt(pci_fun_t *fun)
541{
542 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
543 if (irq != 0xff)
544 pci_add_interrupt(fun, irq);
545}
546
547/** Enumerate (recursively) and register the devices connected to a pci bus.
548 *
549 * @param bus Host-to-PCI bridge
550 * @param bus_num Bus number
551 */
552void pci_bus_scan(pci_bus_t *bus, int bus_num)
553{
554 pci_fun_t *fun;
555 int rc;
556
557 int child_bus = 0;
558 int dnum, fnum;
559 bool multi;
560 uint8_t header_type;
561
562 for (dnum = 0; dnum < 32; dnum++) {
563 multi = true;
564 for (fnum = 0; multi && fnum < 8; fnum++) {
565 fun = pci_fun_new(bus);
566
567 pci_fun_init(fun, bus_num, dnum, fnum);
568 if (fun->vendor_id == 0xffff) {
569 pci_fun_delete(fun);
570 /*
571 * The device is not present, go on scanning the
572 * bus.
573 */
574 if (fnum == 0)
575 break;
576 else
577 continue;
578 }
579
580 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
581 if (fnum == 0) {
582 /* Is the device multifunction? */
583 multi = header_type >> 7;
584 }
585 /* Clear the multifunction bit. */
586 header_type = header_type & 0x7F;
587
588 char *fun_name = pci_fun_create_name(fun);
589 if (fun_name == NULL) {
590 ddf_msg(LVL_ERROR, "Out of memory.");
591 pci_fun_delete(fun);
592 return;
593 }
594
595 rc = ddf_fun_set_name(fun->fnode, fun_name);
596 free(fun_name);
597 if (rc != EOK) {
598 ddf_msg(LVL_ERROR, "Failed setting function name.");
599 pci_fun_delete(fun);
600 return;
601 }
602
603 pci_alloc_resource_list(fun);
604 pci_read_bars(fun);
605 pci_read_interrupt(fun);
606
607 ddf_fun_set_ops(fun->fnode, &pci_fun_ops);
608
609 ddf_msg(LVL_DEBUG, "Adding new function %s.",
610 ddf_fun_get_name(fun->fnode));
611
612 pci_fun_create_match_ids(fun);
613
614 if (ddf_fun_bind(fun->fnode) != EOK) {
615 pci_clean_resource_list(fun);
616 pci_fun_delete(fun);
617 continue;
618 }
619
620 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
621 header_type == PCI_HEADER_TYPE_CARDBUS) {
622 child_bus = pci_conf_read_8(fun,
623 PCI_BRIDGE_SEC_BUS_NUM);
624 ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
625 "bridge, secondary bus number = %d.",
626 bus_num);
627 if (child_bus > bus_num)
628 pci_bus_scan(bus, child_bus);
629 }
630 }
631 }
632}
633
634static int pci_dev_add(ddf_dev_t *dnode)
635{
636 pci_bus_t *bus = NULL;
637 ddf_fun_t *ctl = NULL;
638 bool got_res = false;
639 async_sess_t *sess;
640 int rc;
641
642 ddf_msg(LVL_DEBUG, "pci_dev_add");
643
644 bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
645 if (bus == NULL) {
646 ddf_msg(LVL_ERROR, "pci_dev_add allocation failed.");
647 rc = ENOMEM;
648 goto fail;
649 }
650 fibril_mutex_initialize(&bus->conf_mutex);
651
652 bus->dnode = dnode;
653
654 sess = ddf_dev_parent_sess_create(dnode, EXCHANGE_SERIALIZE);
655 if (sess == NULL) {
656 ddf_msg(LVL_ERROR, "pci_dev_add failed to connect to the "
657 "parent driver.");
658 rc = ENOENT;
659 goto fail;
660 }
661
662 hw_resource_list_t hw_resources;
663
664 rc = hw_res_get_resource_list(sess, &hw_resources);
665 if (rc != EOK) {
666 ddf_msg(LVL_ERROR, "pci_dev_add failed to get hw resources "
667 "for the device.");
668 goto fail;
669 }
670 got_res = true;
671
672
673 assert(hw_resources.count > 1);
674 assert(hw_resources.resources[0].type == IO_RANGE);
675 assert(hw_resources.resources[0].res.io_range.size >= 4);
676
677 assert(hw_resources.resources[1].type == IO_RANGE);
678 assert(hw_resources.resources[1].res.io_range.size >= 4);
679
680 ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
681 hw_resources.resources[0].res.io_range.address);
682 ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
683 hw_resources.resources[1].res.io_range.address);
684
685 bus->conf_io_addr =
686 (uint32_t) hw_resources.resources[0].res.io_range.address;
687 bus->conf_io_data =
688 (uint32_t) hw_resources.resources[1].res.io_range.address;
689
690 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 4,
691 &bus->conf_addr_port)) {
692 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
693 rc = EADDRNOTAVAIL;
694 goto fail;
695 }
696 if (pio_enable((void *)(uintptr_t)bus->conf_io_data, 4,
697 &bus->conf_data_port)) {
698 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
699 rc = EADDRNOTAVAIL;
700 goto fail;
701 }
702
703 /* Make the bus device more visible. It has no use yet. */
704 ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
705
706 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
707 if (ctl == NULL) {
708 ddf_msg(LVL_ERROR, "Failed creating control function.");
709 rc = ENOMEM;
710 goto fail;
711 }
712
713 rc = ddf_fun_bind(ctl);
714 if (rc != EOK) {
715 ddf_msg(LVL_ERROR, "Failed binding control function.");
716 goto fail;
717 }
718
719 /* Enumerate functions. */
720 ddf_msg(LVL_DEBUG, "Scanning the bus");
721 pci_bus_scan(bus, 0);
722
723 hw_res_clean_resource_list(&hw_resources);
724
725 return EOK;
726
727fail:
728 if (got_res)
729 hw_res_clean_resource_list(&hw_resources);
730
731 if (ctl != NULL)
732 ddf_fun_destroy(ctl);
733
734 return rc;
735}
736
737static int pci_fun_online(ddf_fun_t *fun)
738{
739 ddf_msg(LVL_DEBUG, "pci_fun_online()");
740 return ddf_fun_online(fun);
741}
742
743static int pci_fun_offline(ddf_fun_t *fun)
744{
745 ddf_msg(LVL_DEBUG, "pci_fun_offline()");
746 return ddf_fun_offline(fun);
747}
748
749static void pciintel_init(void)
750{
751 ddf_log_init(NAME);
752 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
753 pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
754}
755
756pci_fun_t *pci_fun_new(pci_bus_t *bus)
757{
758 pci_fun_t *fun;
759 ddf_fun_t *fnode;
760
761 fnode = ddf_fun_create(bus->dnode, fun_inner, NULL);
762 if (fnode == NULL)
763 return NULL;
764
765 fun = ddf_fun_data_alloc(fnode, sizeof(pci_fun_t));
766 if (fun == NULL)
767 return NULL;
768
769 fun->busptr = bus;
770 fun->fnode = fnode;
771 return fun;
772}
773
774void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
775{
776 fun->bus = bus;
777 fun->dev = dev;
778 fun->fn = fn;
779 fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
780 fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
781
782 /* Explicitly enable PCI bus mastering */
783 fun->command = pci_conf_read_16(fun, PCI_COMMAND) |
784 PCI_COMMAND_MASTER;
785 pci_conf_write_16(fun, PCI_COMMAND, fun->command);
786
787 fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
788 fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
789 fun->prog_if = pci_conf_read_8(fun, PCI_PROG_IF);
790 fun->revision = pci_conf_read_8(fun, PCI_REVISION_ID);
791}
792
793void pci_fun_delete(pci_fun_t *fun)
794{
795 hw_res_clean_resource_list(&fun->hw_resources);
796 if (fun->fnode != NULL)
797 ddf_fun_destroy(fun->fnode);
798}
799
800char *pci_fun_create_name(pci_fun_t *fun)
801{
802 char *name = NULL;
803
804 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
805 fun->fn);
806 return name;
807}
808
809bool pci_alloc_resource_list(pci_fun_t *fun)
810{
811 fun->hw_resources.resources = fun->resources;
812 return true;
813}
814
815void pci_clean_resource_list(pci_fun_t *fun)
816{
817 fun->hw_resources.resources = NULL;
818}
819
820/** Read the base address registers (BARs) of the function and add the addresses
821 * to its HW resource list.
822 *
823 * @param fun PCI function
824 */
825void pci_read_bars(pci_fun_t *fun)
826{
827 /*
828 * Position of the BAR in the PCI configuration address space of the
829 * device.
830 */
831 int addr = PCI_BASE_ADDR_0;
832
833 while (addr <= PCI_BASE_ADDR_5)
834 addr = pci_read_bar(fun, addr);
835}
836
837size_t pci_bar_mask_to_size(uint32_t mask)
838{
839 size_t size = mask & ~(mask - 1);
840 return size;
841}
842
843int main(int argc, char *argv[])
844{
845 printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
846 pciintel_init();
847 return ddf_driver_main(&pci_driver);
848}
849
850/**
851 * @}
852 */
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