source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ 5572ad1

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 5572ad1 was 56fd7cf, checked in by Jiri Svoboda <jiri@…>, 13 years ago

Make ddf_dev_t and ddf_fun_t opaque. This further tighthens the DDF interface.
  • Property mode set to 100644
File size: 20.0 KB
Line 
1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @defgroup pciintel pci bus driver for intel method 1.
32 * @brief HelenOS root pci bus driver for intel method 1.
33 * @{
34 */
35
36/** @file
37 */
38
39#include <assert.h>
40#include <byteorder.h>
41#include <stdio.h>
42#include <errno.h>
43#include <bool.h>
44#include <fibril_synch.h>
45#include <str.h>
46#include <ctype.h>
47#include <macros.h>
48#include <str_error.h>
49
50#include <ddf/driver.h>
51#include <ddf/log.h>
52#include <ipc/dev_iface.h>
53#include <ipc/irc.h>
54#include <ns.h>
55#include <ipc/services.h>
56#include <sysinfo.h>
57#include <ops/hw_res.h>
58#include <device/hw_res.h>
59#include <ddi.h>
60#include <libarch/ddi.h>
61#include <pci_dev_iface.h>
62
63#include "pci.h"
64
65#define NAME "pciintel"
66
67#define CONF_ADDR(bus, dev, fn, reg) \
68 ((1 << 31) | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
69
70/** Obtain PCI function soft-state from DDF function node */
71static pci_fun_t *pci_fun(ddf_fun_t *fnode)
72{
73 return ddf_fun_data_get(fnode);
74}
75
76/** Obtain PCI bus soft-state from DDF device node */
77#if 0
78static pci_bus_t *pci_bus(ddf_dev_t *dnode)
79{
80 return ddf_dev_data_get(dnode);
81}
82#endif
83
84/** Obtain PCI bus soft-state from function soft-state */
85static pci_bus_t *pci_bus_from_fun(pci_fun_t *fun)
86{
87 return fun->busptr;
88}
89
90/** Max is 47, align to something nice. */
91#define ID_MAX_STR_LEN 50
92
93static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
94{
95 pci_fun_t *fun = pci_fun(fnode);
96
97 if (fun == NULL)
98 return NULL;
99 return &fun->hw_resources;
100}
101
102static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
103{
104 /* This is an old ugly way */
105 assert(fnode);
106 pci_fun_t *dev_data = pci_fun(fnode);
107
108 sysarg_t apic;
109 sysarg_t i8259;
110
111 async_sess_t *irc_sess = NULL;
112
113 if (((sysinfo_get_value("apic", &apic) == EOK) && (apic))
114 || ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259))) {
115 irc_sess = service_connect_blocking(EXCHANGE_SERIALIZE,
116 SERVICE_IRC, 0, 0);
117 }
118
119 if (!irc_sess)
120 return false;
121
122 size_t i = 0;
123 hw_resource_list_t *res = &dev_data->hw_resources;
124 for (; i < res->count; i++) {
125 if (res->resources[i].type == INTERRUPT) {
126 const int irq = res->resources[i].res.interrupt.irq;
127
128 async_exch_t *exch = async_exchange_begin(irc_sess);
129 const int rc =
130 async_req_1_0(exch, IRC_ENABLE_INTERRUPT, irq);
131 async_exchange_end(exch);
132
133 if (rc != EOK) {
134 async_hangup(irc_sess);
135 return false;
136 }
137 }
138 }
139
140 async_hangup(irc_sess);
141 return true;
142}
143
144static int pci_config_space_write_32(ddf_fun_t *fun, uint32_t address,
145 uint32_t data)
146{
147 if (address > 252)
148 return EINVAL;
149 pci_conf_write_32(pci_fun(fun), address, data);
150 return EOK;
151}
152
153static int pci_config_space_write_16(
154 ddf_fun_t *fun, uint32_t address, uint16_t data)
155{
156 if (address > 254)
157 return EINVAL;
158 pci_conf_write_16(pci_fun(fun), address, data);
159 return EOK;
160}
161
162static int pci_config_space_write_8(
163 ddf_fun_t *fun, uint32_t address, uint8_t data)
164{
165 if (address > 255)
166 return EINVAL;
167 pci_conf_write_8(pci_fun(fun), address, data);
168 return EOK;
169}
170
171static int pci_config_space_read_32(
172 ddf_fun_t *fun, uint32_t address, uint32_t *data)
173{
174 if (address > 252)
175 return EINVAL;
176 *data = pci_conf_read_32(pci_fun(fun), address);
177 return EOK;
178}
179
180static int pci_config_space_read_16(
181 ddf_fun_t *fun, uint32_t address, uint16_t *data)
182{
183 if (address > 254)
184 return EINVAL;
185 *data = pci_conf_read_16(pci_fun(fun), address);
186 return EOK;
187}
188
189static int pci_config_space_read_8(
190 ddf_fun_t *fun, uint32_t address, uint8_t *data)
191{
192 if (address > 255)
193 return EINVAL;
194 *data = pci_conf_read_8(pci_fun(fun), address);
195 return EOK;
196}
197
198static hw_res_ops_t pciintel_hw_res_ops = {
199 .get_resource_list = &pciintel_get_resources,
200 .enable_interrupt = &pciintel_enable_interrupt,
201};
202
203static pci_dev_iface_t pci_dev_ops = {
204 .config_space_read_8 = &pci_config_space_read_8,
205 .config_space_read_16 = &pci_config_space_read_16,
206 .config_space_read_32 = &pci_config_space_read_32,
207 .config_space_write_8 = &pci_config_space_write_8,
208 .config_space_write_16 = &pci_config_space_write_16,
209 .config_space_write_32 = &pci_config_space_write_32
210};
211
212static ddf_dev_ops_t pci_fun_ops = {
213 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
214 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
215};
216
217static int pci_dev_add(ddf_dev_t *);
218static int pci_fun_online(ddf_fun_t *);
219static int pci_fun_offline(ddf_fun_t *);
220
221/** PCI bus driver standard operations */
222static driver_ops_t pci_ops = {
223 .dev_add = &pci_dev_add,
224 .fun_online = &pci_fun_online,
225 .fun_offline = &pci_fun_offline,
226};
227
228/** PCI bus driver structure */
229static driver_t pci_driver = {
230 .name = NAME,
231 .driver_ops = &pci_ops
232};
233
234static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
235{
236 pci_bus_t *bus = pci_bus_from_fun(fun);
237
238 fibril_mutex_lock(&bus->conf_mutex);
239
240 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
241 void *addr = bus->conf_data_port + (reg & 3);
242
243 pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
244
245 switch (len) {
246 case 1:
247 /* No endianness change for 1 byte */
248 buf[0] = pio_read_8(addr);
249 break;
250 case 2:
251 ((uint16_t *) buf)[0] = uint16_t_le2host(pio_read_16(addr));
252 break;
253 case 4:
254 ((uint32_t *) buf)[0] = uint32_t_le2host(pio_read_32(addr));
255 break;
256 }
257
258 fibril_mutex_unlock(&bus->conf_mutex);
259}
260
261static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
262{
263 pci_bus_t *bus = pci_bus_from_fun(fun);
264
265 fibril_mutex_lock(&bus->conf_mutex);
266
267 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
268 void *addr = bus->conf_data_port + (reg & 3);
269
270 pio_write_32(bus->conf_addr_port, host2uint32_t_le(conf_addr));
271
272 switch (len) {
273 case 1:
274 /* No endianness change for 1 byte */
275 pio_write_8(addr, buf[0]);
276 break;
277 case 2:
278 pio_write_16(addr, host2uint16_t_le(((uint16_t *) buf)[0]));
279 break;
280 case 4:
281 pio_write_32(addr, host2uint32_t_le(((uint32_t *) buf)[0]));
282 break;
283 }
284
285 fibril_mutex_unlock(&bus->conf_mutex);
286}
287
288uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
289{
290 uint8_t res;
291 pci_conf_read(fun, reg, &res, 1);
292 return res;
293}
294
295uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
296{
297 uint16_t res;
298 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
299 return res;
300}
301
302uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
303{
304 uint32_t res;
305 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
306 return res;
307}
308
309void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
310{
311 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
312}
313
314void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
315{
316 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
317}
318
319void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
320{
321 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
322}
323
324void pci_fun_create_match_ids(pci_fun_t *fun)
325{
326 int rc;
327 char match_id_str[ID_MAX_STR_LEN];
328
329 /* Vendor ID & Device ID, length(incl \0) 22 */
330 rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04x&dev=%04x",
331 fun->vendor_id, fun->device_id);
332 if (rc < 0) {
333 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
334 str_error(rc));
335 }
336
337 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
338 if (rc != EOK) {
339 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
340 }
341
342 /* Class, subclass, prog IF, revision, length(incl \0) 47 */
343 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
344 "pci/class=%02x&subclass=%02x&progif=%02x&revision=%02x",
345 fun->class_code, fun->subclass_code, fun->prog_if, fun->revision);
346 if (rc < 0) {
347 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
348 str_error(rc));
349 }
350
351 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 70);
352 if (rc != EOK) {
353 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
354 }
355
356 /* Class, subclass, prog IF, length(incl \0) 35 */
357 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
358 "pci/class=%02x&subclass=%02x&progif=%02x",
359 fun->class_code, fun->subclass_code, fun->prog_if);
360 if (rc < 0) {
361 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
362 str_error(rc));
363 }
364
365 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 60);
366 if (rc != EOK) {
367 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
368 }
369
370 /* Class, subclass, length(incl \0) 25 */
371 rc = snprintf(match_id_str, ID_MAX_STR_LEN,
372 "pci/class=%02x&subclass=%02x",
373 fun->class_code, fun->subclass_code);
374 if (rc < 0) {
375 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
376 str_error(rc));
377 }
378
379 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 50);
380 if (rc != EOK) {
381 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
382 }
383
384 /* Class, length(incl \0) 13 */
385 rc = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/class=%02x",
386 fun->class_code);
387 if (rc < 0) {
388 ddf_msg(LVL_ERROR, "Failed creating match ID str: %s",
389 str_error(rc));
390 }
391
392 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 40);
393 if (rc != EOK) {
394 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
395 }
396
397 /* TODO add subsys ids, but those exist only in header type 0 */
398}
399
400void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
401 bool io)
402{
403 hw_resource_list_t *hw_res_list = &fun->hw_resources;
404 hw_resource_t *hw_resources = hw_res_list->resources;
405 size_t count = hw_res_list->count;
406
407 assert(hw_resources != NULL);
408 assert(count < PCI_MAX_HW_RES);
409
410 if (io) {
411 hw_resources[count].type = IO_RANGE;
412 hw_resources[count].res.io_range.address = range_addr;
413 hw_resources[count].res.io_range.size = range_size;
414 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
415 } else {
416 hw_resources[count].type = MEM_RANGE;
417 hw_resources[count].res.mem_range.address = range_addr;
418 hw_resources[count].res.mem_range.size = range_size;
419 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
420 }
421
422 hw_res_list->count++;
423}
424
425/** Read the base address register (BAR) of the device and if it contains valid
426 * address add it to the devices hw resource list.
427 *
428 * @param fun PCI function
429 * @param addr The address of the BAR in the PCI configuration address space of
430 * the device
431 * @return The addr the address of the BAR which should be read next
432 */
433int pci_read_bar(pci_fun_t *fun, int addr)
434{
435 /* Value of the BAR */
436 uint32_t val, mask;
437 /* IO space address */
438 bool io;
439 /* 64-bit wide address */
440 bool addrw64;
441
442 /* Size of the io or memory range specified by the BAR */
443 size_t range_size;
444 /* Beginning of the io or memory range specified by the BAR */
445 uint64_t range_addr;
446
447 /* Get the value of the BAR. */
448 val = pci_conf_read_32(fun, addr);
449
450#define IO_MASK (~0x3)
451#define MEM_MASK (~0xf)
452
453 io = (bool) (val & 1);
454 if (io) {
455 addrw64 = false;
456 mask = IO_MASK;
457 } else {
458 mask = MEM_MASK;
459 switch ((val >> 1) & 3) {
460 case 0:
461 addrw64 = false;
462 break;
463 case 2:
464 addrw64 = true;
465 break;
466 default:
467 /* reserved, go to the next BAR */
468 return addr + 4;
469 }
470 }
471
472 /* Get the address mask. */
473 pci_conf_write_32(fun, addr, 0xffffffff);
474 mask &= pci_conf_read_32(fun, addr);
475
476 /* Restore the original value. */
477 pci_conf_write_32(fun, addr, val);
478 val = pci_conf_read_32(fun, addr);
479
480 range_size = pci_bar_mask_to_size(mask);
481
482 if (addrw64) {
483 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
484 (val & 0xfffffff0);
485 } else {
486 range_addr = (val & 0xfffffff0);
487 }
488
489 if (range_addr != 0) {
490 ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
491 ", size = %x", ddf_fun_get_name(fun->fnode), range_addr,
492 (unsigned int) range_size);
493 }
494
495 pci_add_range(fun, range_addr, range_size, io);
496
497 if (addrw64)
498 return addr + 8;
499
500 return addr + 4;
501}
502
503void pci_add_interrupt(pci_fun_t *fun, int irq)
504{
505 hw_resource_list_t *hw_res_list = &fun->hw_resources;
506 hw_resource_t *hw_resources = hw_res_list->resources;
507 size_t count = hw_res_list->count;
508
509 assert(NULL != hw_resources);
510 assert(count < PCI_MAX_HW_RES);
511
512 hw_resources[count].type = INTERRUPT;
513 hw_resources[count].res.interrupt.irq = irq;
514
515 hw_res_list->count++;
516
517 ddf_msg(LVL_NOTE, "Function %s uses irq %x.", ddf_fun_get_name(fun->fnode), irq);
518}
519
520void pci_read_interrupt(pci_fun_t *fun)
521{
522 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
523 if (irq != 0xff)
524 pci_add_interrupt(fun, irq);
525}
526
527/** Enumerate (recursively) and register the devices connected to a pci bus.
528 *
529 * @param bus Host-to-PCI bridge
530 * @param bus_num Bus number
531 */
532void pci_bus_scan(pci_bus_t *bus, int bus_num)
533{
534 pci_fun_t *fun;
535 int rc;
536
537 int child_bus = 0;
538 int dnum, fnum;
539 bool multi;
540 uint8_t header_type;
541
542 for (dnum = 0; dnum < 32; dnum++) {
543 multi = true;
544 for (fnum = 0; multi && fnum < 8; fnum++) {
545 fun = pci_fun_new(bus);
546
547 pci_fun_init(fun, bus_num, dnum, fnum);
548 if (fun->vendor_id == 0xffff) {
549 pci_fun_delete(fun);
550 /*
551 * The device is not present, go on scanning the
552 * bus.
553 */
554 if (fnum == 0)
555 break;
556 else
557 continue;
558 }
559
560 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
561 if (fnum == 0) {
562 /* Is the device multifunction? */
563 multi = header_type >> 7;
564 }
565 /* Clear the multifunction bit. */
566 header_type = header_type & 0x7F;
567
568 char *fun_name = pci_fun_create_name(fun);
569 if (fun_name == NULL) {
570 ddf_msg(LVL_ERROR, "Out of memory.");
571 pci_fun_delete(fun);
572 return;
573 }
574
575 rc = ddf_fun_set_name(fun->fnode, fun_name);
576 free(fun_name);
577 if (rc != EOK) {
578 ddf_msg(LVL_ERROR, "Failed setting function name.");
579 pci_fun_delete(fun);
580 return;
581 }
582
583 pci_alloc_resource_list(fun);
584 pci_read_bars(fun);
585 pci_read_interrupt(fun);
586
587 ddf_fun_set_ops(fun->fnode, &pci_fun_ops);
588
589 ddf_msg(LVL_DEBUG, "Adding new function %s.",
590 ddf_fun_get_name(fun->fnode));
591
592 pci_fun_create_match_ids(fun);
593
594 if (ddf_fun_bind(fun->fnode) != EOK) {
595 pci_clean_resource_list(fun);
596 pci_fun_delete(fun);
597 continue;
598 }
599
600 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
601 header_type == PCI_HEADER_TYPE_CARDBUS) {
602 child_bus = pci_conf_read_8(fun,
603 PCI_BRIDGE_SEC_BUS_NUM);
604 ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
605 "bridge, secondary bus number = %d.",
606 bus_num);
607 if (child_bus > bus_num)
608 pci_bus_scan(bus, child_bus);
609 }
610 }
611 }
612}
613
614static int pci_dev_add(ddf_dev_t *dnode)
615{
616 pci_bus_t *bus = NULL;
617 ddf_fun_t *ctl = NULL;
618 bool got_res = false;
619 async_sess_t *sess;
620 int rc;
621
622 ddf_msg(LVL_DEBUG, "pci_dev_add");
623
624 bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
625 if (bus == NULL) {
626 ddf_msg(LVL_ERROR, "pci_dev_add allocation failed.");
627 rc = ENOMEM;
628 goto fail;
629 }
630 fibril_mutex_initialize(&bus->conf_mutex);
631
632 bus->dnode = dnode;
633
634 sess = ddf_dev_parent_sess_create(dnode, EXCHANGE_SERIALIZE);
635 if (sess == NULL) {
636 ddf_msg(LVL_ERROR, "pci_dev_add failed to connect to the "
637 "parent driver.");
638 rc = ENOENT;
639 goto fail;
640 }
641
642 hw_resource_list_t hw_resources;
643
644 rc = hw_res_get_resource_list(sess, &hw_resources);
645 if (rc != EOK) {
646 ddf_msg(LVL_ERROR, "pci_dev_add failed to get hw resources "
647 "for the device.");
648 goto fail;
649 }
650 got_res = true;
651
652
653 assert(hw_resources.count > 1);
654 assert(hw_resources.resources[0].type == IO_RANGE);
655 assert(hw_resources.resources[0].res.io_range.size >= 4);
656
657 assert(hw_resources.resources[1].type == IO_RANGE);
658 assert(hw_resources.resources[1].res.io_range.size >= 4);
659
660 ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
661 hw_resources.resources[0].res.io_range.address);
662 ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
663 hw_resources.resources[1].res.io_range.address);
664
665 bus->conf_io_addr =
666 (uint32_t) hw_resources.resources[0].res.io_range.address;
667 bus->conf_io_data =
668 (uint32_t) hw_resources.resources[1].res.io_range.address;
669
670 if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 4,
671 &bus->conf_addr_port)) {
672 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
673 rc = EADDRNOTAVAIL;
674 goto fail;
675 }
676 if (pio_enable((void *)(uintptr_t)bus->conf_io_data, 4,
677 &bus->conf_data_port)) {
678 ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
679 rc = EADDRNOTAVAIL;
680 goto fail;
681 }
682
683 /* Make the bus device more visible. It has no use yet. */
684 ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
685
686 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
687 if (ctl == NULL) {
688 ddf_msg(LVL_ERROR, "Failed creating control function.");
689 rc = ENOMEM;
690 goto fail;
691 }
692
693 rc = ddf_fun_bind(ctl);
694 if (rc != EOK) {
695 ddf_msg(LVL_ERROR, "Failed binding control function.");
696 goto fail;
697 }
698
699 /* Enumerate functions. */
700 ddf_msg(LVL_DEBUG, "Scanning the bus");
701 pci_bus_scan(bus, 0);
702
703 hw_res_clean_resource_list(&hw_resources);
704
705 return EOK;
706
707fail:
708 if (got_res)
709 hw_res_clean_resource_list(&hw_resources);
710
711 if (ctl != NULL)
712 ddf_fun_destroy(ctl);
713
714 return rc;
715}
716
717static int pci_fun_online(ddf_fun_t *fun)
718{
719 ddf_msg(LVL_DEBUG, "pci_fun_online()");
720 return ddf_fun_online(fun);
721}
722
723static int pci_fun_offline(ddf_fun_t *fun)
724{
725 ddf_msg(LVL_DEBUG, "pci_fun_offline()");
726 return ddf_fun_offline(fun);
727}
728
729static void pciintel_init(void)
730{
731 ddf_log_init(NAME, LVL_ERROR);
732 pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
733 pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
734}
735
736pci_fun_t *pci_fun_new(pci_bus_t *bus)
737{
738 pci_fun_t *fun;
739 ddf_fun_t *fnode;
740
741 fnode = ddf_fun_create(bus->dnode, fun_inner, NULL);
742 if (fnode == NULL)
743 return NULL;
744
745 fun = ddf_fun_data_alloc(fnode, sizeof(pci_fun_t));
746 if (fun == NULL)
747 return NULL;
748
749 fun->busptr = bus;
750 fun->fnode = fnode;
751 return fun;
752}
753
754void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
755{
756 fun->bus = bus;
757 fun->dev = dev;
758 fun->fn = fn;
759 fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
760 fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
761 fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
762 fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
763 fun->prog_if = pci_conf_read_8(fun, PCI_PROG_IF);
764 fun->revision = pci_conf_read_8(fun, PCI_REVISION_ID);
765}
766
767void pci_fun_delete(pci_fun_t *fun)
768{
769 hw_res_clean_resource_list(&fun->hw_resources);
770 if (fun->fnode != NULL)
771 ddf_fun_destroy(fun->fnode);
772}
773
774char *pci_fun_create_name(pci_fun_t *fun)
775{
776 char *name = NULL;
777
778 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
779 fun->fn);
780 return name;
781}
782
783bool pci_alloc_resource_list(pci_fun_t *fun)
784{
785 fun->hw_resources.resources = fun->resources;
786 return true;
787}
788
789void pci_clean_resource_list(pci_fun_t *fun)
790{
791 fun->hw_resources.resources = NULL;
792}
793
794/** Read the base address registers (BARs) of the function and add the addresses
795 * to its HW resource list.
796 *
797 * @param fun PCI function
798 */
799void pci_read_bars(pci_fun_t *fun)
800{
801 /*
802 * Position of the BAR in the PCI configuration address space of the
803 * device.
804 */
805 int addr = PCI_BASE_ADDR_0;
806
807 while (addr <= PCI_BASE_ADDR_5)
808 addr = pci_read_bar(fun, addr);
809}
810
811size_t pci_bar_mask_to_size(uint32_t mask)
812{
813 size_t size = mask & ~(mask - 1);
814 return size;
815}
816
817int main(int argc, char *argv[])
818{
819 printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
820 pciintel_init();
821 return ddf_driver_main(&pci_driver);
822}
823
824/**
825 * @}
826 */
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