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source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ 4069f5c

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Last change on this file since 4069f5c was ef9460b, checked in by Jiri Svoboda <jiri@…>, 14 years ago
ddf_fun_add_match_id() should copy its string argument.
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1	/*
2	* Copyright (c) 2010 Lenka Trochtova
3	* Copyright (c) 2011 Jiri Svoboda
4	* All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	*
10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.
17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/
29
30	/**
31	* @defgroup pciintel pci bus driver for intel method 1.
32	* @brief HelenOS root pci bus driver for intel method 1.
33	* @{
34	*/
35
36	/** @file
37	*/
38
39	#include <assert.h>
40	#include <stdio.h>
41	#include <errno.h>
42	#include <bool.h>
43	#include <fibril_synch.h>
44	#include <str.h>
45	#include <ctype.h>
46	#include <macros.h>
47	#include <str_error.h>
48
49	#include <ddf/driver.h>
50	#include <ddf/log.h>
51	#include <devman.h>
52	#include <ipc/devman.h>
53	#include <ipc/dev_iface.h>
54	#include <ipc/irc.h>
55	#include <ns.h>
56	#include <ipc/services.h>
57	#include <sysinfo.h>
58	#include <ops/hw_res.h>
59	#include <device/hw_res.h>
60	#include <ddi.h>
61	#include <libarch/ddi.h>
62	#include <pci_dev_iface.h>
63
64	#include "pci.h"
65
66	#define NAME "pciintel"
67
68	#define CONF_ADDR(bus, dev, fn, reg) \
69	((1 << 31) \| (bus << 16) \| (dev << 11) \| (fn << 8) \| (reg & ~3))
70
71	/** Obtain PCI function soft-state from DDF function node */
72	#define PCI_FUN(fnode) ((pci_fun_t *) (fnode)->driver_data)
73
74	/** Obtain PCI bus soft-state from DDF device node */
75	#define PCI_BUS(dnode) ((pci_bus_t *) (dnode)->driver_data)
76
77	/** Obtain PCI bus soft-state from function soft-state */
78	#define PCI_BUS_FROM_FUN(fun) ((fun)->busptr)
79
80	static hw_resource_list_t pciintel_get_resources(ddf_fun_t fnode)
81	{
82	pci_fun_t *fun = PCI_FUN(fnode);
83
84	if (fun == NULL)
85	return NULL;
86	return &fun->hw_resources;
87	}
88
89	static bool pciintel_enable_interrupt(ddf_fun_t *fnode)
90	{
91	/* This is an old ugly way, copied from ne2000 driver */
92	assert(fnode);
93	pci_fun_t dev_data = (pci_fun_t ) fnode->driver_data;
94
95	sysarg_t apic;
96	sysarg_t i8259;
97
98	async_sess_t *irc_sess = NULL;
99
100	if (((sysinfo_get_value("apic", &apic) == EOK) && (apic))
101	\|\| ((sysinfo_get_value("i8259", &i8259) == EOK) && (i8259))) {
102	irc_sess = service_connect_blocking(EXCHANGE_SERIALIZE,
103	SERVICE_IRC, 0, 0);
104	}
105
106	if (!irc_sess)
107	return false;
108
109	size_t i = 0;
110	hw_resource_list_t *res = &dev_data->hw_resources;
111	for (; i < res->count; i++) {
112	if (res->resources[i].type == INTERRUPT) {
113	const int irq = res->resources[i].res.interrupt.irq;
114
115	async_exch_t *exch = async_exchange_begin(irc_sess);
116	const int rc =
117	async_req_1_0(exch, IRC_ENABLE_INTERRUPT, irq);
118	async_exchange_end(exch);
119
120	if (rc != EOK) {
121	async_hangup(irc_sess);
122	return false;
123	}
124	}
125	}
126
127	async_hangup(irc_sess);
128	return true;
129	}
130
131	static int pci_config_space_write_32(ddf_fun_t *fun, uint32_t address,
132	uint32_t data)
133	{
134	if (address > 252)
135	return EINVAL;
136	pci_conf_write_32(PCI_FUN(fun), address, data);
137	return EOK;
138	}
139
140	static int pci_config_space_write_16(
141	ddf_fun_t *fun, uint32_t address, uint16_t data)
142	{
143	if (address > 254)
144	return EINVAL;
145	pci_conf_write_16(PCI_FUN(fun), address, data);
146	return EOK;
147	}
148
149	static int pci_config_space_write_8(
150	ddf_fun_t *fun, uint32_t address, uint8_t data)
151	{
152	if (address > 255)
153	return EINVAL;
154	pci_conf_write_8(PCI_FUN(fun), address, data);
155	return EOK;
156	}
157
158	static int pci_config_space_read_32(
159	ddf_fun_t fun, uint32_t address, uint32_t data)
160	{
161	if (address > 252)
162	return EINVAL;
163	*data = pci_conf_read_32(PCI_FUN(fun), address);
164	return EOK;
165	}
166
167	static int pci_config_space_read_16(
168	ddf_fun_t fun, uint32_t address, uint16_t data)
169	{
170	if (address > 254)
171	return EINVAL;
172	*data = pci_conf_read_16(PCI_FUN(fun), address);
173	return EOK;
174	}
175
176	static int pci_config_space_read_8(
177	ddf_fun_t fun, uint32_t address, uint8_t data)
178	{
179	if (address > 255)
180	return EINVAL;
181	*data = pci_conf_read_8(PCI_FUN(fun), address);
182	return EOK;
183	}
184
185	static hw_res_ops_t pciintel_hw_res_ops = {
186	&pciintel_get_resources,
187	&pciintel_enable_interrupt
188	};
189
190	static pci_dev_iface_t pci_dev_ops = {
191	.config_space_read_8 = &pci_config_space_read_8,
192	.config_space_read_16 = &pci_config_space_read_16,
193	.config_space_read_32 = &pci_config_space_read_32,
194	.config_space_write_8 = &pci_config_space_write_8,
195	.config_space_write_16 = &pci_config_space_write_16,
196	.config_space_write_32 = &pci_config_space_write_32
197	};
198
199	static ddf_dev_ops_t pci_fun_ops = {
200	.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
201	.interfaces[PCI_DEV_IFACE] = &pci_dev_ops
202	};
203
204	static int pci_add_device(ddf_dev_t *);
205
206	/** PCI bus driver standard operations */
207	static driver_ops_t pci_ops = {
208	.add_device = &pci_add_device
209	};
210
211	/** PCI bus driver structure */
212	static driver_t pci_driver = {
213	.name = NAME,
214	.driver_ops = &pci_ops
215	};
216
217	static pci_bus_t *pci_bus_new(void)
218	{
219	pci_bus_t *bus;
220
221	bus = (pci_bus_t *) calloc(1, sizeof(pci_bus_t));
222	if (bus == NULL)
223	return NULL;
224
225	fibril_mutex_initialize(&bus->conf_mutex);
226	return bus;
227	}
228
229	static void pci_bus_delete(pci_bus_t *bus)
230	{
231	assert(bus != NULL);
232	free(bus);
233	}
234
235	static void pci_conf_read(pci_fun_t fun, int reg, uint8_t buf, size_t len)
236	{
237	pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
238
239	fibril_mutex_lock(&bus->conf_mutex);
240
241	uint32_t conf_addr;
242	conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
243	void *addr = bus->conf_data_port + (reg & 3);
244
245	pio_write_32(bus->conf_addr_port, conf_addr);
246
247	switch (len) {
248	case 1:
249	buf[0] = pio_read_8(addr);
250	break;
251	case 2:
252	((uint16_t *) buf)[0] = pio_read_16(addr);
253	break;
254	case 4:
255	((uint32_t *) buf)[0] = pio_read_32(addr);
256	break;
257	}
258
259	fibril_mutex_unlock(&bus->conf_mutex);
260	}
261
262	static void pci_conf_write(pci_fun_t fun, int reg, uint8_t buf, size_t len)
263	{
264	pci_bus_t *bus = PCI_BUS_FROM_FUN(fun);
265
266	fibril_mutex_lock(&bus->conf_mutex);
267
268	uint32_t conf_addr;
269	conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
270	void *addr = bus->conf_data_port + (reg & 3);
271
272	pio_write_32(bus->conf_addr_port, conf_addr);
273
274	switch (len) {
275	case 1:
276	pio_write_8(addr, buf[0]);
277	break;
278	case 2:
279	pio_write_16(addr, ((uint16_t *) buf)[0]);
280	break;
281	case 4:
282	pio_write_32(addr, ((uint32_t *) buf)[0]);
283	break;
284	}
285
286	fibril_mutex_unlock(&bus->conf_mutex);
287	}
288
289	uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
290	{
291	uint8_t res;
292	pci_conf_read(fun, reg, &res, 1);
293	return res;
294	}
295
296	uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
297	{
298	uint16_t res;
299	pci_conf_read(fun, reg, (uint8_t *) &res, 2);
300	return res;
301	}
302
303	uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
304	{
305	uint32_t res;
306	pci_conf_read(fun, reg, (uint8_t *) &res, 4);
307	return res;
308	}
309
310	void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
311	{
312	pci_conf_write(fun, reg, (uint8_t *) &val, 1);
313	}
314
315	void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
316	{
317	pci_conf_write(fun, reg, (uint8_t *) &val, 2);
318	}
319
320	void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
321	{
322	pci_conf_write(fun, reg, (uint8_t *) &val, 4);
323	}
324
325	void pci_fun_create_match_ids(pci_fun_t *fun)
326	{
327	char *match_id_str;
328	int rc;
329
330	asprintf(&match_id_str, "pci/ven=%04x&dev=%04x",
331	fun->vendor_id, fun->device_id);
332
333	if (match_id_str == NULL) {
334	ddf_msg(LVL_ERROR, "Out of memory creating match ID.");
335	return;
336	}
337
338	rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
339	if (rc != EOK) {
340	ddf_msg(LVL_ERROR, "Failed adding match ID: %s",
341	str_error(rc));
342	}
343
344	free(match_id_str);
345
346	/* TODO add more ids (with subsys ids, using class id etc.) */
347	}
348
349	void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
350	bool io)
351	{
352	hw_resource_list_t *hw_res_list = &fun->hw_resources;
353	hw_resource_t *hw_resources = hw_res_list->resources;
354	size_t count = hw_res_list->count;
355
356	assert(hw_resources != NULL);
357	assert(count < PCI_MAX_HW_RES);
358
359	if (io) {
360	hw_resources[count].type = IO_RANGE;
361	hw_resources[count].res.io_range.address = range_addr;
362	hw_resources[count].res.io_range.size = range_size;
363	hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
364	} else {
365	hw_resources[count].type = MEM_RANGE;
366	hw_resources[count].res.mem_range.address = range_addr;
367	hw_resources[count].res.mem_range.size = range_size;
368	hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
369	}
370
371	hw_res_list->count++;
372	}
373
374	/** Read the base address register (BAR) of the device and if it contains valid
375	* address add it to the devices hw resource list.
376	*
377	* @param fun PCI function
378	* @param addr The address of the BAR in the PCI configuration address space of
379	* the device
380	* @return The addr the address of the BAR which should be read next
381	*/
382	int pci_read_bar(pci_fun_t *fun, int addr)
383	{
384	/* Value of the BAR */
385	uint32_t val, mask;
386	/* IO space address */
387	bool io;
388	/* 64-bit wide address */
389	bool addrw64;
390
391	/* Size of the io or memory range specified by the BAR */
392	size_t range_size;
393	/* Beginning of the io or memory range specified by the BAR */
394	uint64_t range_addr;
395
396	/* Get the value of the BAR. */
397	val = pci_conf_read_32(fun, addr);
398
399	#define IO_MASK (~0x3)
400	#define MEM_MASK (~0xf)
401
402	io = (bool) (val & 1);
403	if (io) {
404	addrw64 = false;
405	mask = IO_MASK;
406	} else {
407	mask = MEM_MASK;
408	switch ((val >> 1) & 3) {
409	case 0:
410	addrw64 = false;
411	break;
412	case 2:
413	addrw64 = true;
414	break;
415	default:
416	/* reserved, go to the next BAR */
417	return addr + 4;
418	}
419	}
420
421	/* Get the address mask. */
422	pci_conf_write_32(fun, addr, 0xffffffff);
423	mask &= pci_conf_read_32(fun, addr);
424
425	/* Restore the original value. */
426	pci_conf_write_32(fun, addr, val);
427	val = pci_conf_read_32(fun, addr);
428
429	range_size = pci_bar_mask_to_size(mask);
430
431	if (addrw64) {
432	range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) \|
433	(val & 0xfffffff0);
434	} else {
435	range_addr = (val & 0xfffffff0);
436	}
437
438	if (range_addr != 0) {
439	ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
440	", size = %x", fun->fnode->name, range_addr,
441	(unsigned int) range_size);
442	}
443
444	pci_add_range(fun, range_addr, range_size, io);
445
446	if (addrw64)
447	return addr + 8;
448
449	return addr + 4;
450	}
451
452	void pci_add_interrupt(pci_fun_t *fun, int irq)
453	{
454	hw_resource_list_t *hw_res_list = &fun->hw_resources;
455	hw_resource_t *hw_resources = hw_res_list->resources;
456	size_t count = hw_res_list->count;
457
458	assert(NULL != hw_resources);
459	assert(count < PCI_MAX_HW_RES);
460
461	hw_resources[count].type = INTERRUPT;
462	hw_resources[count].res.interrupt.irq = irq;
463
464	hw_res_list->count++;
465
466	ddf_msg(LVL_NOTE, "Function %s uses irq %x.", fun->fnode->name, irq);
467	}
468
469	void pci_read_interrupt(pci_fun_t *fun)
470	{
471	uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
472	if (irq != 0xff)
473	pci_add_interrupt(fun, irq);
474	}
475
476	/** Enumerate (recursively) and register the devices connected to a pci bus.
477	*
478	* @param bus Host-to-PCI bridge
479	* @param bus_num Bus number
480	*/
481	void pci_bus_scan(pci_bus_t *bus, int bus_num)
482	{
483	ddf_fun_t *fnode;
484	pci_fun_t *fun;
485
486	int child_bus = 0;
487	int dnum, fnum;
488	bool multi;
489	uint8_t header_type;
490
491	fun = pci_fun_new(bus);
492
493	for (dnum = 0; dnum < 32; dnum++) {
494	multi = true;
495	for (fnum = 0; multi && fnum < 8; fnum++) {
496	pci_fun_init(fun, bus_num, dnum, fnum);
497	fun->vendor_id = pci_conf_read_16(fun,
498	PCI_VENDOR_ID);
499	fun->device_id = pci_conf_read_16(fun,
500	PCI_DEVICE_ID);
501	if (fun->vendor_id == 0xffff) {
502	/*
503	* The device is not present, go on scanning the
504	* bus.
505	*/
506	if (fnum == 0)
507	break;
508	else
509	continue;
510	}
511
512	header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
513	if (fnum == 0) {
514	/* Is the device multifunction? */
515	multi = header_type >> 7;
516	}
517	/* Clear the multifunction bit. */
518	header_type = header_type & 0x7F;
519
520	char *fun_name = pci_fun_create_name(fun);
521	if (fun_name == NULL) {
522	ddf_msg(LVL_ERROR, "Out of memory.");
523	return;
524	}
525
526	fnode = ddf_fun_create(bus->dnode, fun_inner, fun_name);
527	if (fnode == NULL) {
528	ddf_msg(LVL_ERROR, "Failed creating function.");
529	return;
530	}
531
532	free(fun_name);
533	fun->fnode = fnode;
534
535	pci_alloc_resource_list(fun);
536	pci_read_bars(fun);
537	pci_read_interrupt(fun);
538
539	fnode->ops = &pci_fun_ops;
540	fnode->driver_data = fun;
541
542	ddf_msg(LVL_DEBUG, "Adding new function %s.",
543	fnode->name);
544
545	pci_fun_create_match_ids(fun);
546
547	if (ddf_fun_bind(fnode) != EOK) {
548	pci_clean_resource_list(fun);
549	clean_match_ids(&fnode->match_ids);
550	free((char *) fnode->name);
551	fnode->name = NULL;
552	continue;
553	}
554
555	if (header_type == PCI_HEADER_TYPE_BRIDGE \|\|
556	header_type == PCI_HEADER_TYPE_CARDBUS) {
557	child_bus = pci_conf_read_8(fun,
558	PCI_BRIDGE_SEC_BUS_NUM);
559	ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
560	"bridge, secondary bus number = %d.",
561	bus_num);
562	if (child_bus > bus_num)
563	pci_bus_scan(bus, child_bus);
564	}
565
566	fun = pci_fun_new(bus);
567	}
568	}
569
570	if (fun->vendor_id == 0xffff) {
571	/* Free the auxiliary function structure. */
572	pci_fun_delete(fun);
573	}
574	}
575
576	static int pci_add_device(ddf_dev_t *dnode)
577	{
578	pci_bus_t *bus = NULL;
579	ddf_fun_t *ctl = NULL;
580	bool got_res = false;
581	int rc;
582
583	ddf_msg(LVL_DEBUG, "pci_add_device");
584	dnode->parent_sess = NULL;
585
586	bus = pci_bus_new();
587	if (bus == NULL) {
588	ddf_msg(LVL_ERROR, "pci_add_device allocation failed.");
589	rc = ENOMEM;
590	goto fail;
591	}
592	bus->dnode = dnode;
593	dnode->driver_data = bus;
594
595	dnode->parent_sess = devman_parent_device_connect(EXCHANGE_SERIALIZE,
596	dnode->handle, IPC_FLAG_BLOCKING);
597	if (!dnode->parent_sess) {
598	ddf_msg(LVL_ERROR, "pci_add_device failed to connect to the "
599	"parent driver.");
600	rc = ENOENT;
601	goto fail;
602	}
603
604	hw_resource_list_t hw_resources;
605
606	rc = hw_res_get_resource_list(dnode->parent_sess, &hw_resources);
607	if (rc != EOK) {
608	ddf_msg(LVL_ERROR, "pci_add_device failed to get hw resources "
609	"for the device.");
610	goto fail;
611	}
612	got_res = true;
613
614	ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
615	hw_resources.resources[0].res.io_range.address);
616
617	assert(hw_resources.count > 0);
618	assert(hw_resources.resources[0].type == IO_RANGE);
619	assert(hw_resources.resources[0].res.io_range.size == 8);
620
621	bus->conf_io_addr =
622	(uint32_t) hw_resources.resources[0].res.io_range.address;
623
624	if (pio_enable((void *)(uintptr_t)bus->conf_io_addr, 8,
625	&bus->conf_addr_port)) {
626	ddf_msg(LVL_ERROR, "Failed to enable configuration ports.");
627	rc = EADDRNOTAVAIL;
628	goto fail;
629	}
630	bus->conf_data_port = (char *) bus->conf_addr_port + 4;
631
632	/* Make the bus device more visible. It has no use yet. */
633	ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
634
635	ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
636	if (ctl == NULL) {
637	ddf_msg(LVL_ERROR, "Failed creating control function.");
638	rc = ENOMEM;
639	goto fail;
640	}
641
642	rc = ddf_fun_bind(ctl);
643	if (rc != EOK) {
644	ddf_msg(LVL_ERROR, "Failed binding control function.");
645	goto fail;
646	}
647
648	/* Enumerate functions. */
649	ddf_msg(LVL_DEBUG, "Scanning the bus");
650	pci_bus_scan(bus, 0);
651
652	hw_res_clean_resource_list(&hw_resources);
653
654	return EOK;
655
656	fail:
657	if (bus != NULL)
658	pci_bus_delete(bus);
659
660	if (dnode->parent_sess)
661	async_hangup(dnode->parent_sess);
662
663	if (got_res)
664	hw_res_clean_resource_list(&hw_resources);
665
666	if (ctl != NULL)
667	ddf_fun_destroy(ctl);
668
669	return rc;
670	}
671
672	static void pciintel_init(void)
673	{
674	ddf_log_init(NAME, LVL_ERROR);
675	pci_fun_ops.interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops;
676	pci_fun_ops.interfaces[PCI_DEV_IFACE] = &pci_dev_ops;
677	}
678
679	pci_fun_t pci_fun_new(pci_bus_t bus)
680	{
681	pci_fun_t *fun;
682
683	fun = (pci_fun_t *) calloc(1, sizeof(pci_fun_t));
684	if (fun == NULL)
685	return NULL;
686
687	fun->busptr = bus;
688	return fun;
689	}
690
691	void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
692	{
693	fun->bus = bus;
694	fun->dev = dev;
695	fun->fn = fn;
696	}
697
698	void pci_fun_delete(pci_fun_t *fun)
699	{
700	assert(fun != NULL);
701	hw_res_clean_resource_list(&fun->hw_resources);
702	free(fun);
703	}
704
705	char pci_fun_create_name(pci_fun_t fun)
706	{
707	char *name = NULL;
708
709	asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
710	fun->fn);
711	return name;
712	}
713
714	bool pci_alloc_resource_list(pci_fun_t *fun)
715	{
716	fun->hw_resources.resources =
717	(hw_resource_t ) malloc(PCI_MAX_HW_RES sizeof(hw_resource_t));
718	return fun->hw_resources.resources != NULL;
719	}
720
721	void pci_clean_resource_list(pci_fun_t *fun)
722	{
723	if (fun->hw_resources.resources != NULL) {
724	free(fun->hw_resources.resources);
725	fun->hw_resources.resources = NULL;
726	}
727	}
728
729	/** Read the base address registers (BARs) of the function and add the addresses
730	* to its HW resource list.
731	*
732	* @param fun PCI function
733	*/
734	void pci_read_bars(pci_fun_t *fun)
735	{
736	/*
737	* Position of the BAR in the PCI configuration address space of the
738	* device.
739	*/
740	int addr = PCI_BASE_ADDR_0;
741
742	while (addr <= PCI_BASE_ADDR_5)
743	addr = pci_read_bar(fun, addr);
744	}
745
746	size_t pci_bar_mask_to_size(uint32_t mask)
747	{
748	size_t size = mask & ~(mask - 1);
749	return size;
750	}
751
752	int main(int argc, char *argv[])
753	{
754	printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
755	pciintel_init();
756	return ddf_driver_main(&pci_driver);
757	}
758
759	/**
760	* @}
761	*/

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