source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ 0dab4850

Last change on this file since 0dab4850 was 7acd787, checked in by Jiri Svoboda <jiri@…>, 6 years ago

Utility for listing PCI devices

Currently all information presented can also be gathered from devctl -v,
although 'pci' prints it in a nice compact format. Ability to print
more information, including information not available from devctl,
can be added later.
  • Property mode set to 100644
File size: 23.6 KB
Line 
1/*
2 * Copyright (c) 2019 Jiri Svoboda
3 * Copyright (c) 2010 Lenka Trochtova
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @addtogroup pciintel
32 * @{
33 */
34
35/** @file
36 */
37
38#include <assert.h>
39#include <byteorder.h>
40#include <stdio.h>
41#include <errno.h>
42#include <stdbool.h>
43#include <fibril_synch.h>
44#include <str.h>
45#include <ctype.h>
46#include <macros.h>
47#include <str_error.h>
48
49#include <ddf/driver.h>
50#include <ddf/log.h>
51#include <ipc/dev_iface.h>
52#include <irc.h>
53#include <ops/hw_res.h>
54#include <device/hw_res.h>
55#include <ops/pio_window.h>
56#include <device/pio_window.h>
57#include <ddi.h>
58#include <pci_dev_iface.h>
59
60#include "ctl.h"
61#include "pci.h"
62#include "pci_regs.h"
63
64#define NAME "pciintel"
65
66#define CONF_ADDR_ENABLE (((unsigned)1) << 31)
67#define CONF_ADDR(bus, dev, fn, reg) \
68 ((bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
69
70/** Obtain PCI function soft-state from DDF function node */
71static pci_fun_t *pci_fun(ddf_fun_t *fnode)
72{
73 return ddf_fun_data_get(fnode);
74}
75
76/** Obtain PCI bus soft-state from DDF device node */
77pci_bus_t *pci_bus(ddf_dev_t *dnode)
78{
79 return ddf_dev_data_get(dnode);
80}
81
82/** Obtain PCI bus soft-state from function soft-state */
83static pci_bus_t *pci_bus_from_fun(pci_fun_t *fun)
84{
85 return fun->busptr;
86}
87
88/** Max is 47, align to something nice. */
89#define ID_MAX_STR_LEN 50
90
91static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
92{
93 pci_fun_t *fun = pci_fun(fnode);
94
95 if (fun == NULL)
96 return NULL;
97 return &fun->hw_resources;
98}
99
100static bool pciintel_fun_owns_interrupt(pci_fun_t *fun, int irq)
101{
102 size_t i;
103 hw_resource_list_t *res = &fun->hw_resources;
104
105 for (i = 0; i < res->count; i++) {
106 if (res->resources[i].type == INTERRUPT &&
107 res->resources[i].res.interrupt.irq == irq) {
108 return true;
109 }
110 }
111
112 return false;
113}
114
115static errno_t pciintel_enable_interrupt(ddf_fun_t *fnode, int irq)
116{
117 pci_fun_t *fun = pci_fun(fnode);
118
119 if (!pciintel_fun_owns_interrupt(fun, irq))
120 return EINVAL;
121
122 return irc_enable_interrupt(irq);
123}
124
125static errno_t pciintel_disable_interrupt(ddf_fun_t *fnode, int irq)
126{
127 pci_fun_t *fun = pci_fun(fnode);
128
129 if (!pciintel_fun_owns_interrupt(fun, irq))
130 return EINVAL;
131
132 return irc_disable_interrupt(irq);
133}
134
135static errno_t pciintel_clear_interrupt(ddf_fun_t *fnode, int irq)
136{
137 pci_fun_t *fun = pci_fun(fnode);
138
139 if (!pciintel_fun_owns_interrupt(fun, irq))
140 return EINVAL;
141
142 return irc_clear_interrupt(irq);
143}
144
145static pio_window_t *pciintel_get_pio_window(ddf_fun_t *fnode)
146{
147 pci_fun_t *fun = pci_fun(fnode);
148
149 if (fun == NULL)
150 return NULL;
151 return &fun->pio_window;
152}
153
154static errno_t config_space_write_32(ddf_fun_t *fun, uint32_t address,
155 uint32_t data)
156{
157 if (address > 252)
158 return EINVAL;
159 pci_conf_write_32(pci_fun(fun), address, data);
160 return EOK;
161}
162
163static errno_t config_space_write_16(
164 ddf_fun_t *fun, uint32_t address, uint16_t data)
165{
166 if (address > 254)
167 return EINVAL;
168 pci_conf_write_16(pci_fun(fun), address, data);
169 return EOK;
170}
171
172static errno_t config_space_write_8(
173 ddf_fun_t *fun, uint32_t address, uint8_t data)
174{
175 if (address > 255)
176 return EINVAL;
177 pci_conf_write_8(pci_fun(fun), address, data);
178 return EOK;
179}
180
181static errno_t config_space_read_32(
182 ddf_fun_t *fun, uint32_t address, uint32_t *data)
183{
184 if (address > 252)
185 return EINVAL;
186 *data = pci_conf_read_32(pci_fun(fun), address);
187 return EOK;
188}
189
190static errno_t config_space_read_16(
191 ddf_fun_t *fun, uint32_t address, uint16_t *data)
192{
193 if (address > 254)
194 return EINVAL;
195 *data = pci_conf_read_16(pci_fun(fun), address);
196 return EOK;
197}
198
199static errno_t config_space_read_8(
200 ddf_fun_t *fun, uint32_t address, uint8_t *data)
201{
202 if (address > 255)
203 return EINVAL;
204 *data = pci_conf_read_8(pci_fun(fun), address);
205 return EOK;
206}
207
208static hw_res_ops_t pciintel_hw_res_ops = {
209 .get_resource_list = &pciintel_get_resources,
210 .enable_interrupt = &pciintel_enable_interrupt,
211 .disable_interrupt = &pciintel_disable_interrupt,
212 .clear_interrupt = &pciintel_clear_interrupt,
213};
214
215static pio_window_ops_t pciintel_pio_window_ops = {
216 .get_pio_window = &pciintel_get_pio_window
217};
218
219static pci_dev_iface_t pci_dev_ops = {
220 .config_space_read_8 = &config_space_read_8,
221 .config_space_read_16 = &config_space_read_16,
222 .config_space_read_32 = &config_space_read_32,
223 .config_space_write_8 = &config_space_write_8,
224 .config_space_write_16 = &config_space_write_16,
225 .config_space_write_32 = &config_space_write_32
226};
227
228static ddf_dev_ops_t pci_fun_ops = {
229 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
230 .interfaces[PIO_WINDOW_DEV_IFACE] = &pciintel_pio_window_ops,
231 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
232};
233
234static errno_t pci_dev_add(ddf_dev_t *);
235static errno_t pci_fun_online(ddf_fun_t *);
236static errno_t pci_fun_offline(ddf_fun_t *);
237
238/** PCI bus driver standard operations */
239static driver_ops_t pci_ops = {
240 .dev_add = &pci_dev_add,
241 .fun_online = &pci_fun_online,
242 .fun_offline = &pci_fun_offline,
243};
244
245/** PCI bus driver structure */
246static driver_t pci_driver = {
247 .name = NAME,
248 .driver_ops = &pci_ops
249};
250
251static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
252{
253 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
254 pci_bus_t *bus = pci_bus_from_fun(fun);
255 uint32_t val;
256
257 fibril_mutex_lock(&bus->conf_mutex);
258
259 if (bus->conf_addr_reg) {
260 pio_write_32(bus->conf_addr_reg,
261 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
262 /*
263 * Always read full 32-bits from the PCI conf_data_port
264 * register and get the desired portion of it afterwards. Some
265 * architectures do not support shorter PIO reads offset from
266 * this register.
267 */
268 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
269 } else {
270 val = uint32_t_le2host(pio_read_32(
271 &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
272 }
273
274 switch (len) {
275 case 1:
276 *buf = (uint8_t) (val >> ((reg & 3) * 8));
277 break;
278 case 2:
279 *((uint16_t *) buf) = (uint16_t) (val >> ((reg & 3)) * 8);
280 break;
281 case 4:
282 *((uint32_t *) buf) = (uint32_t) val;
283 break;
284 }
285
286 fibril_mutex_unlock(&bus->conf_mutex);
287}
288
289static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
290{
291 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
292 pci_bus_t *bus = pci_bus_from_fun(fun);
293 uint32_t val = 0;
294
295 fibril_mutex_lock(&bus->conf_mutex);
296
297 /*
298 * Prepare to write full 32-bits to the PCI conf_data_port register.
299 * Some architectures do not support shorter PIO writes offset from this
300 * register.
301 */
302
303 if (len < 4) {
304 /*
305 * We have fewer than full 32-bits, so we need to read the
306 * missing bits first.
307 */
308 if (bus->conf_addr_reg) {
309 pio_write_32(bus->conf_addr_reg,
310 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
311 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
312 } else {
313 val = uint32_t_le2host(pio_read_32(
314 &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
315 }
316 }
317
318 switch (len) {
319 case 1:
320 val &= ~(0xffU << ((reg & 3) * 8));
321 val |= *buf << ((reg & 3) * 8);
322 break;
323 case 2:
324 val &= ~(0xffffU << ((reg & 3) * 8));
325 val |= *((uint16_t *) buf) << ((reg & 3) * 8);
326 break;
327 case 4:
328 val = *((uint32_t *) buf);
329 break;
330 }
331
332 if (bus->conf_addr_reg) {
333 pio_write_32(bus->conf_addr_reg,
334 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
335 pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
336 } else {
337 pio_write_32(&bus->conf_space[conf_addr / sizeof(ioport32_t)],
338 host2uint32_t_le(val));
339 }
340
341 fibril_mutex_unlock(&bus->conf_mutex);
342}
343
344uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
345{
346 uint8_t res;
347 pci_conf_read(fun, reg, &res, 1);
348 return res;
349}
350
351uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
352{
353 uint16_t res;
354 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
355 return res;
356}
357
358uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
359{
360 uint32_t res;
361 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
362 return res;
363}
364
365void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
366{
367 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
368}
369
370void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
371{
372 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
373}
374
375void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
376{
377 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
378}
379
380void pci_fun_create_match_ids(pci_fun_t *fun)
381{
382 errno_t rc;
383 int ret;
384 char match_id_str[ID_MAX_STR_LEN];
385
386 /* Vendor ID & Device ID, length(incl \0) 22 */
387 ret = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04"
388 PRIx16 "&dev=%04" PRIx16, fun->vendor_id, fun->device_id);
389 if (ret < 0) {
390 ddf_msg(LVL_ERROR, "Failed creating match ID str");
391 }
392
393 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
394 if (rc != EOK) {
395 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
396 }
397
398 /* Class, subclass, prog IF, revision, length(incl \0) 47 */
399 ret = snprintf(match_id_str, ID_MAX_STR_LEN,
400 "pci/class=%02x&subclass=%02x&progif=%02x&revision=%02x",
401 fun->class_code, fun->subclass_code, fun->prog_if, fun->revision);
402 if (ret < 0) {
403 ddf_msg(LVL_ERROR, "Failed creating match ID str");
404 }
405
406 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 70);
407 if (rc != EOK) {
408 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
409 }
410
411 /* Class, subclass, prog IF, length(incl \0) 35 */
412 ret = snprintf(match_id_str, ID_MAX_STR_LEN,
413 "pci/class=%02x&subclass=%02x&progif=%02x",
414 fun->class_code, fun->subclass_code, fun->prog_if);
415 if (ret < 0) {
416 ddf_msg(LVL_ERROR, "Failed creating match ID str");
417 }
418
419 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 60);
420 if (rc != EOK) {
421 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
422 }
423
424 /* Class, subclass, length(incl \0) 25 */
425 ret = snprintf(match_id_str, ID_MAX_STR_LEN,
426 "pci/class=%02x&subclass=%02x",
427 fun->class_code, fun->subclass_code);
428 if (ret < 0) {
429 ddf_msg(LVL_ERROR, "Failed creating match ID str");
430 }
431
432 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 50);
433 if (rc != EOK) {
434 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
435 }
436
437 /* Class, length(incl \0) 13 */
438 ret = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/class=%02x",
439 fun->class_code);
440 if (ret < 0) {
441 ddf_msg(LVL_ERROR, "Failed creating match ID str");
442 }
443
444 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 40);
445 if (rc != EOK) {
446 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
447 }
448
449 /* TODO add subsys ids, but those exist only in header type 0 */
450}
451
452/** Get first PCI function.
453 *
454 * @param bus PCI bus
455 * @return First PCI function on @a bus or @c NULL if there is none
456 */
457pci_fun_t *pci_fun_first(pci_bus_t *bus)
458{
459 link_t *link;
460
461 link = list_first(&bus->funs);
462 if (link == NULL)
463 return NULL;
464
465 return list_get_instance(link, pci_fun_t, lfuns);
466}
467
468/** Get next PCI function.
469 *
470 * @param cur Current function
471 * @return Next PCI function on the same bus or @c NULL if there is none
472 */
473pci_fun_t *pci_fun_next(pci_fun_t *cur)
474{
475 link_t *link;
476
477 link = list_next(&cur->lfuns, &cur->busptr->funs);
478 if (link == NULL)
479 return NULL;
480
481 return list_get_instance(link, pci_fun_t, lfuns);
482}
483
484void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
485 bool io)
486{
487 hw_resource_list_t *hw_res_list = &fun->hw_resources;
488 hw_resource_t *hw_resources = hw_res_list->resources;
489 size_t count = hw_res_list->count;
490
491 assert(hw_resources != NULL);
492 assert(count < PCI_MAX_HW_RES);
493
494 if (io) {
495 hw_resources[count].type = IO_RANGE;
496 hw_resources[count].res.io_range.address = range_addr;
497 hw_resources[count].res.io_range.size = range_size;
498 hw_resources[count].res.io_range.relative = true;
499 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
500 } else {
501 hw_resources[count].type = MEM_RANGE;
502 hw_resources[count].res.mem_range.address = range_addr;
503 hw_resources[count].res.mem_range.size = range_size;
504 hw_resources[count].res.mem_range.relative = false;
505 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
506 }
507
508 hw_res_list->count++;
509}
510
511/** Read the base address register (BAR) of the device and if it contains valid
512 * address add it to the devices hw resource list.
513 *
514 * @param fun PCI function
515 * @param addr The address of the BAR in the PCI configuration address space of
516 * the device
517 * @return The addr the address of the BAR which should be read next
518 */
519int pci_read_bar(pci_fun_t *fun, int addr)
520{
521 /* Value of the BAR */
522 uint32_t val;
523 uint32_t bar;
524 uint32_t mask;
525
526 /* IO space address */
527 bool io;
528 /* 64-bit wide address */
529 bool addrw64;
530
531 /* Size of the io or memory range specified by the BAR */
532 size_t range_size;
533 /* Beginning of the io or memory range specified by the BAR */
534 uint64_t range_addr;
535
536 /* Get the value of the BAR. */
537 val = pci_conf_read_32(fun, addr);
538
539#define IO_MASK (~0x3)
540#define MEM_MASK (~0xf)
541
542 io = (val & 1) != 0;
543 if (io) {
544 addrw64 = false;
545 mask = IO_MASK;
546 } else {
547 mask = MEM_MASK;
548 switch ((val >> 1) & 3) {
549 case 0:
550 addrw64 = false;
551 break;
552 case 2:
553 addrw64 = true;
554 break;
555 default:
556 /* reserved, go to the next BAR */
557 return addr + 4;
558 }
559 }
560
561 /* Get the address mask. */
562 pci_conf_write_32(fun, addr, 0xffffffff);
563 bar = pci_conf_read_32(fun, addr);
564
565 /*
566 * Unimplemented BARs read back as all 0's.
567 */
568 if (!bar)
569 return addr + (addrw64 ? 8 : 4);
570
571 mask &= bar;
572
573 /* Restore the original value. */
574 pci_conf_write_32(fun, addr, val);
575 val = pci_conf_read_32(fun, addr);
576
577 range_size = pci_bar_mask_to_size(mask);
578
579 if (addrw64) {
580 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
581 (val & 0xfffffff0);
582 } else {
583 range_addr = (val & 0xfffffff0);
584 }
585
586 if (range_addr != 0) {
587 ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
588 ", size = %x", ddf_fun_get_name(fun->fnode), range_addr,
589 (unsigned int) range_size);
590 }
591
592 pci_add_range(fun, range_addr, range_size, io);
593
594 if (addrw64)
595 return addr + 8;
596
597 return addr + 4;
598}
599
600void pci_add_interrupt(pci_fun_t *fun, int irq)
601{
602 hw_resource_list_t *hw_res_list = &fun->hw_resources;
603 hw_resource_t *hw_resources = hw_res_list->resources;
604 size_t count = hw_res_list->count;
605
606 assert(NULL != hw_resources);
607 assert(count < PCI_MAX_HW_RES);
608
609 hw_resources[count].type = INTERRUPT;
610 hw_resources[count].res.interrupt.irq = irq;
611
612 hw_res_list->count++;
613
614 ddf_msg(LVL_NOTE, "Function %s uses irq %x.", ddf_fun_get_name(fun->fnode), irq);
615}
616
617void pci_read_interrupt(pci_fun_t *fun)
618{
619 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
620 uint8_t pin = pci_conf_read_8(fun, PCI_BRIDGE_INT_PIN);
621
622 if (pin != 0 && irq != 0xff)
623 pci_add_interrupt(fun, irq);
624}
625
626/** Enumerate (recursively) and register the devices connected to a pci bus.
627 *
628 * @param bus Host-to-PCI bridge
629 * @param bus_num Bus number
630 *
631 * @return EOK on success, ENOENT if no PCI devices found, ENOMEM if out of
632 * memory, EIO on other I/O error
633 */
634errno_t pci_bus_scan(pci_bus_t *bus, int bus_num)
635{
636 pci_fun_t *fun;
637 errno_t rc;
638
639 int child_bus = 0;
640 int dnum, fnum;
641 bool multi;
642 uint8_t header_type;
643 bool device_found;
644
645 device_found = false;
646
647 for (dnum = 0; dnum < 32; dnum++) {
648 multi = true;
649 for (fnum = 0; multi && fnum < 8; fnum++) {
650 fun = pci_fun_new(bus);
651
652 pci_fun_init(fun, bus_num, dnum, fnum);
653 if (fun->vendor_id == 0xffff) {
654 pci_fun_delete(fun);
655 /*
656 * The device is not present, go on scanning the
657 * bus.
658 */
659 if (fnum == 0)
660 break;
661 else
662 continue;
663 }
664
665 device_found = true;
666
667 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
668 if (fnum == 0) {
669 /* Is the device multifunction? */
670 multi = header_type >> 7;
671 }
672 /* Clear the multifunction bit. */
673 header_type = header_type & 0x7F;
674
675 char *fun_name = pci_fun_create_name(fun);
676 if (fun_name == NULL) {
677 ddf_msg(LVL_ERROR, "Out of memory.");
678 pci_fun_delete(fun);
679 return ENOMEM;
680 }
681
682 rc = ddf_fun_set_name(fun->fnode, fun_name);
683 free(fun_name);
684 if (rc != EOK) {
685 ddf_msg(LVL_ERROR, "Failed setting function name.");
686 pci_fun_delete(fun);
687 return EIO;
688 }
689
690 pci_alloc_resource_list(fun);
691 pci_read_bars(fun);
692 pci_read_interrupt(fun);
693
694 /* Propagate the PIO window to the function. */
695 fun->pio_window = bus->pio_win;
696
697 ddf_fun_set_ops(fun->fnode, &pci_fun_ops);
698
699 ddf_msg(LVL_DEBUG, "Adding new function %s.",
700 ddf_fun_get_name(fun->fnode));
701
702 pci_fun_create_match_ids(fun);
703
704 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
705 header_type == PCI_HEADER_TYPE_CARDBUS) {
706 child_bus = pci_conf_read_8(fun,
707 PCI_BRIDGE_SEC_BUS_NUM);
708 ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
709 "bridge, secondary bus number = %d.",
710 bus_num);
711 if (child_bus > bus_num) {
712 rc = pci_bus_scan(bus, child_bus);
713 if (rc != EOK && rc != ENOENT) {
714 pci_fun_delete(fun);
715 return rc;
716 }
717 }
718 }
719
720 if (ddf_fun_bind(fun->fnode) != EOK) {
721 pci_clean_resource_list(fun);
722 pci_fun_delete(fun);
723 continue;
724 }
725
726 list_append(&fun->lfuns, &bus->funs);
727 }
728 }
729
730 /* Fail bus scan if no devices are found. */
731 if (!device_found)
732 return ENOENT;
733
734 return EOK;
735}
736
737static errno_t pci_dev_add(ddf_dev_t *dnode)
738{
739 hw_resource_list_t hw_resources;
740 pci_bus_t *bus = NULL;
741 ddf_fun_t *ctl = NULL;
742 bool got_res = false;
743 async_sess_t *sess;
744 errno_t rc;
745
746 ddf_msg(LVL_DEBUG, "pci_dev_add");
747
748 bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
749 if (bus == NULL) {
750 ddf_msg(LVL_ERROR, "pci_dev_add allocation failed.");
751 rc = ENOMEM;
752 goto fail;
753 }
754
755 list_initialize(&bus->funs);
756 fibril_mutex_initialize(&bus->conf_mutex);
757
758 bus->dnode = dnode;
759
760 sess = ddf_dev_parent_sess_get(dnode);
761 if (sess == NULL) {
762 ddf_msg(LVL_ERROR, "pci_dev_add failed to connect to the "
763 "parent driver.");
764 rc = ENOENT;
765 goto fail;
766 }
767
768 rc = pio_window_get(sess, &bus->pio_win);
769 if (rc != EOK) {
770 ddf_msg(LVL_ERROR, "pci_dev_add failed to get PIO window "
771 "for the device.");
772 goto fail;
773 }
774
775 rc = hw_res_get_resource_list(sess, &hw_resources);
776 if (rc != EOK) {
777 ddf_msg(LVL_ERROR, "pci_dev_add failed to get hw resources "
778 "for the device.");
779 goto fail;
780 }
781 got_res = true;
782
783 assert(hw_resources.count >= 1);
784
785 if (hw_resources.count == 1) {
786 assert(hw_resources.resources[0].type == MEM_RANGE);
787
788 ddf_msg(LVL_DEBUG, "conf_addr_space = %" PRIx64 ".",
789 hw_resources.resources[0].res.mem_range.address);
790
791 if (pio_enable_resource(&bus->pio_win,
792 &hw_resources.resources[0], (void **) &bus->conf_space,
793 NULL, NULL)) {
794 ddf_msg(LVL_ERROR,
795 "Failed to map configuration space.");
796 rc = EADDRNOTAVAIL;
797 goto fail;
798 }
799
800 } else {
801 assert(hw_resources.resources[0].type == IO_RANGE);
802 assert(hw_resources.resources[0].res.io_range.size >= 4);
803
804 assert(hw_resources.resources[1].type == IO_RANGE);
805 assert(hw_resources.resources[1].res.io_range.size >= 4);
806
807 ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
808 hw_resources.resources[0].res.io_range.address);
809 ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
810 hw_resources.resources[1].res.io_range.address);
811
812 if (pio_enable_resource(&bus->pio_win,
813 &hw_resources.resources[0], (void **) &bus->conf_addr_reg,
814 NULL, NULL)) {
815 ddf_msg(LVL_ERROR,
816 "Failed to enable configuration ports.");
817 rc = EADDRNOTAVAIL;
818 goto fail;
819 }
820 if (pio_enable_resource(&bus->pio_win,
821 &hw_resources.resources[1], (void **) &bus->conf_data_reg,
822 NULL, NULL)) {
823 ddf_msg(LVL_ERROR,
824 "Failed to enable configuration ports.");
825 rc = EADDRNOTAVAIL;
826 goto fail;
827 }
828 }
829
830 /* Make the bus device more visible. It has no use yet. */
831 ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
832
833 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
834 if (ctl == NULL) {
835 ddf_msg(LVL_ERROR, "Failed creating control function.");
836 rc = ENOMEM;
837 goto fail;
838 }
839
840 ddf_fun_set_conn_handler(ctl, pci_ctl_connection);
841
842 /* Enumerate functions. */
843 ddf_msg(LVL_DEBUG, "Enumerating the bus");
844 rc = pci_bus_scan(bus, 0);
845 if (rc != EOK) {
846 ddf_msg(LVL_ERROR, "Bus enumeration failed.");
847 goto fail;
848 }
849
850 rc = ddf_fun_bind(ctl);
851 if (rc != EOK) {
852 ddf_msg(LVL_ERROR, "Failed binding control function.");
853 goto fail;
854 }
855
856 rc = ddf_fun_add_to_category(ctl, "pci");
857 if (rc != EOK) {
858 ddf_msg(LVL_ERROR, "Failed adding control function to category "
859 "'pci'.");
860 goto fail;
861 }
862
863 hw_res_clean_resource_list(&hw_resources);
864
865 return EOK;
866
867fail:
868 if (got_res)
869 hw_res_clean_resource_list(&hw_resources);
870
871 if (ctl != NULL)
872 ddf_fun_destroy(ctl);
873
874 return rc;
875}
876
877static errno_t pci_fun_online(ddf_fun_t *fun)
878{
879 ddf_msg(LVL_DEBUG, "pci_fun_online()");
880 return ddf_fun_online(fun);
881}
882
883static errno_t pci_fun_offline(ddf_fun_t *fun)
884{
885 ddf_msg(LVL_DEBUG, "pci_fun_offline()");
886 return ddf_fun_offline(fun);
887}
888
889static void pciintel_init(void)
890{
891 ddf_log_init(NAME);
892}
893
894pci_fun_t *pci_fun_new(pci_bus_t *bus)
895{
896 pci_fun_t *fun;
897 ddf_fun_t *fnode;
898
899 fnode = ddf_fun_create(bus->dnode, fun_inner, NULL);
900 if (fnode == NULL)
901 return NULL;
902
903 fun = ddf_fun_data_alloc(fnode, sizeof(pci_fun_t));
904 if (fun == NULL)
905 return NULL;
906
907 fun->busptr = bus;
908 fun->fnode = fnode;
909 return fun;
910}
911
912void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
913{
914 fun->bus = bus;
915 fun->dev = dev;
916 fun->fn = fn;
917 fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
918 fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
919
920 /* Explicitly enable PCI bus mastering */
921 fun->command = pci_conf_read_16(fun, PCI_COMMAND) |
922 PCI_COMMAND_MASTER;
923 pci_conf_write_16(fun, PCI_COMMAND, fun->command);
924
925 fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
926 fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
927 fun->prog_if = pci_conf_read_8(fun, PCI_PROG_IF);
928 fun->revision = pci_conf_read_8(fun, PCI_REVISION_ID);
929}
930
931void pci_fun_delete(pci_fun_t *fun)
932{
933 hw_res_clean_resource_list(&fun->hw_resources);
934 if (fun->fnode != NULL)
935 ddf_fun_destroy(fun->fnode);
936}
937
938char *pci_fun_create_name(pci_fun_t *fun)
939{
940 char *name = NULL;
941
942 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
943 fun->fn);
944 return name;
945}
946
947bool pci_alloc_resource_list(pci_fun_t *fun)
948{
949 fun->hw_resources.resources = fun->resources;
950 return true;
951}
952
953void pci_clean_resource_list(pci_fun_t *fun)
954{
955 fun->hw_resources.resources = NULL;
956}
957
958/** Read the base address registers (BARs) of the function and add the addresses
959 * to its HW resource list.
960 *
961 * @param fun PCI function
962 */
963void pci_read_bars(pci_fun_t *fun)
964{
965 /*
966 * Position of the BAR in the PCI configuration address space of the
967 * device.
968 */
969 int addr = PCI_BASE_ADDR_0;
970
971 while (addr <= PCI_BASE_ADDR_5)
972 addr = pci_read_bar(fun, addr);
973}
974
975size_t pci_bar_mask_to_size(uint32_t mask)
976{
977 size_t size = mask & ~(mask - 1);
978 return size;
979}
980
981int main(int argc, char *argv[])
982{
983 printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
984 pciintel_init();
985 return ddf_driver_main(&pci_driver);
986}
987
988/**
989 * @}
990 */
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