source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ 09ab0a9a

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 09ab0a9a was 09ab0a9a, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Fix vertical spacing with new Ccheck revision.
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1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @addtogroup pciintel
32 * @{
33 */
34
35/** @file
36 */
37
38#include <assert.h>
39#include <byteorder.h>
40#include <stdio.h>
41#include <errno.h>
42#include <stdbool.h>
43#include <fibril_synch.h>
44#include <str.h>
45#include <ctype.h>
46#include <macros.h>
47#include <str_error.h>
48
49#include <ddf/driver.h>
50#include <ddf/log.h>
51#include <ipc/dev_iface.h>
52#include <irc.h>
53#include <ops/hw_res.h>
54#include <device/hw_res.h>
55#include <ops/pio_window.h>
56#include <device/pio_window.h>
57#include <ddi.h>
58#include <pci_dev_iface.h>
59
60#include "pci.h"
61
62#define NAME "pciintel"
63
64#define CONF_ADDR_ENABLE (((unsigned)1) << 31)
65#define CONF_ADDR(bus, dev, fn, reg) \
66 ((bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
67
68/** Obtain PCI function soft-state from DDF function node */
69static pci_fun_t *pci_fun(ddf_fun_t *fnode)
70{
71 return ddf_fun_data_get(fnode);
72}
73
74/** Obtain PCI bus soft-state from DDF device node */
75#if 0
76static pci_bus_t *pci_bus(ddf_dev_t *dnode)
77{
78 return ddf_dev_data_get(dnode);
79}
80#endif
81
82/** Obtain PCI bus soft-state from function soft-state */
83static pci_bus_t *pci_bus_from_fun(pci_fun_t *fun)
84{
85 return fun->busptr;
86}
87
88/** Max is 47, align to something nice. */
89#define ID_MAX_STR_LEN 50
90
91static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
92{
93 pci_fun_t *fun = pci_fun(fnode);
94
95 if (fun == NULL)
96 return NULL;
97 return &fun->hw_resources;
98}
99
100static bool pciintel_fun_owns_interrupt(pci_fun_t *fun, int irq)
101{
102 size_t i;
103 hw_resource_list_t *res = &fun->hw_resources;
104
105 for (i = 0; i < res->count; i++) {
106 if (res->resources[i].type == INTERRUPT &&
107 res->resources[i].res.interrupt.irq == irq) {
108 return true;
109 }
110 }
111
112 return false;
113}
114
115static errno_t pciintel_enable_interrupt(ddf_fun_t *fnode, int irq)
116{
117 pci_fun_t *fun = pci_fun(fnode);
118
119 if (!pciintel_fun_owns_interrupt(fun, irq))
120 return EINVAL;
121
122 return irc_enable_interrupt(irq);
123}
124
125static errno_t pciintel_disable_interrupt(ddf_fun_t *fnode, int irq)
126{
127 pci_fun_t *fun = pci_fun(fnode);
128
129 if (!pciintel_fun_owns_interrupt(fun, irq))
130 return EINVAL;
131
132 return irc_disable_interrupt(irq);
133}
134
135static errno_t pciintel_clear_interrupt(ddf_fun_t *fnode, int irq)
136{
137 pci_fun_t *fun = pci_fun(fnode);
138
139 if (!pciintel_fun_owns_interrupt(fun, irq))
140 return EINVAL;
141
142 return irc_clear_interrupt(irq);
143}
144
145static pio_window_t *pciintel_get_pio_window(ddf_fun_t *fnode)
146{
147 pci_fun_t *fun = pci_fun(fnode);
148
149 if (fun == NULL)
150 return NULL;
151 return &fun->pio_window;
152}
153
154static errno_t config_space_write_32(ddf_fun_t *fun, uint32_t address,
155 uint32_t data)
156{
157 if (address > 252)
158 return EINVAL;
159 pci_conf_write_32(pci_fun(fun), address, data);
160 return EOK;
161}
162
163static errno_t config_space_write_16(
164 ddf_fun_t *fun, uint32_t address, uint16_t data)
165{
166 if (address > 254)
167 return EINVAL;
168 pci_conf_write_16(pci_fun(fun), address, data);
169 return EOK;
170}
171
172static errno_t config_space_write_8(
173 ddf_fun_t *fun, uint32_t address, uint8_t data)
174{
175 if (address > 255)
176 return EINVAL;
177 pci_conf_write_8(pci_fun(fun), address, data);
178 return EOK;
179}
180
181static errno_t config_space_read_32(
182 ddf_fun_t *fun, uint32_t address, uint32_t *data)
183{
184 if (address > 252)
185 return EINVAL;
186 *data = pci_conf_read_32(pci_fun(fun), address);
187 return EOK;
188}
189
190static errno_t config_space_read_16(
191 ddf_fun_t *fun, uint32_t address, uint16_t *data)
192{
193 if (address > 254)
194 return EINVAL;
195 *data = pci_conf_read_16(pci_fun(fun), address);
196 return EOK;
197}
198
199static errno_t config_space_read_8(
200 ddf_fun_t *fun, uint32_t address, uint8_t *data)
201{
202 if (address > 255)
203 return EINVAL;
204 *data = pci_conf_read_8(pci_fun(fun), address);
205 return EOK;
206}
207
208static hw_res_ops_t pciintel_hw_res_ops = {
209 .get_resource_list = &pciintel_get_resources,
210 .enable_interrupt = &pciintel_enable_interrupt,
211 .disable_interrupt = &pciintel_disable_interrupt,
212 .clear_interrupt = &pciintel_clear_interrupt,
213};
214
215static pio_window_ops_t pciintel_pio_window_ops = {
216 .get_pio_window = &pciintel_get_pio_window
217};
218
219static pci_dev_iface_t pci_dev_ops = {
220 .config_space_read_8 = &config_space_read_8,
221 .config_space_read_16 = &config_space_read_16,
222 .config_space_read_32 = &config_space_read_32,
223 .config_space_write_8 = &config_space_write_8,
224 .config_space_write_16 = &config_space_write_16,
225 .config_space_write_32 = &config_space_write_32
226};
227
228static ddf_dev_ops_t pci_fun_ops = {
229 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
230 .interfaces[PIO_WINDOW_DEV_IFACE] = &pciintel_pio_window_ops,
231 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
232};
233
234static errno_t pci_dev_add(ddf_dev_t *);
235static errno_t pci_fun_online(ddf_fun_t *);
236static errno_t pci_fun_offline(ddf_fun_t *);
237
238/** PCI bus driver standard operations */
239static driver_ops_t pci_ops = {
240 .dev_add = &pci_dev_add,
241 .fun_online = &pci_fun_online,
242 .fun_offline = &pci_fun_offline,
243};
244
245/** PCI bus driver structure */
246static driver_t pci_driver = {
247 .name = NAME,
248 .driver_ops = &pci_ops
249};
250
251static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
252{
253 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
254 pci_bus_t *bus = pci_bus_from_fun(fun);
255 uint32_t val;
256
257 fibril_mutex_lock(&bus->conf_mutex);
258
259 if (bus->conf_addr_reg) {
260 pio_write_32(bus->conf_addr_reg,
261 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
262 /*
263 * Always read full 32-bits from the PCI conf_data_port
264 * register and get the desired portion of it afterwards. Some
265 * architectures do not support shorter PIO reads offset from
266 * this register.
267 */
268 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
269 } else {
270 val = uint32_t_le2host(pio_read_32(
271 &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
272 }
273
274 switch (len) {
275 case 1:
276 *buf = (uint8_t) (val >> ((reg & 3) * 8));
277 break;
278 case 2:
279 *((uint16_t *) buf) = (uint16_t) (val >> ((reg & 3)) * 8);
280 break;
281 case 4:
282 *((uint32_t *) buf) = (uint32_t) val;
283 break;
284 }
285
286 fibril_mutex_unlock(&bus->conf_mutex);
287}
288
289static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
290{
291 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
292 pci_bus_t *bus = pci_bus_from_fun(fun);
293 uint32_t val = 0;
294
295 fibril_mutex_lock(&bus->conf_mutex);
296
297 /*
298 * Prepare to write full 32-bits to the PCI conf_data_port register.
299 * Some architectures do not support shorter PIO writes offset from this
300 * register.
301 */
302
303 if (len < 4) {
304 /*
305 * We have fewer than full 32-bits, so we need to read the
306 * missing bits first.
307 */
308 if (bus->conf_addr_reg) {
309 pio_write_32(bus->conf_addr_reg,
310 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
311 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
312 } else {
313 val = uint32_t_le2host(pio_read_32(
314 &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
315 }
316 }
317
318 switch (len) {
319 case 1:
320 val &= ~(0xffU << ((reg & 3) * 8));
321 val |= *buf << ((reg & 3) * 8);
322 break;
323 case 2:
324 val &= ~(0xffffU << ((reg & 3) * 8));
325 val |= *((uint16_t *) buf) << ((reg & 3) * 8);
326 break;
327 case 4:
328 val = *((uint32_t *) buf);
329 break;
330 }
331
332 if (bus->conf_addr_reg) {
333 pio_write_32(bus->conf_addr_reg,
334 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
335 pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
336 } else {
337 pio_write_32(&bus->conf_space[conf_addr / sizeof(ioport32_t)],
338 host2uint32_t_le(val));
339 }
340
341 fibril_mutex_unlock(&bus->conf_mutex);
342}
343
344uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
345{
346 uint8_t res;
347 pci_conf_read(fun, reg, &res, 1);
348 return res;
349}
350
351uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
352{
353 uint16_t res;
354 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
355 return res;
356}
357
358uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
359{
360 uint32_t res;
361 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
362 return res;
363}
364
365void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
366{
367 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
368}
369
370void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
371{
372 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
373}
374
375void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
376{
377 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
378}
379
380void pci_fun_create_match_ids(pci_fun_t *fun)
381{
382 errno_t rc;
383 int ret;
384 char match_id_str[ID_MAX_STR_LEN];
385
386 /* Vendor ID & Device ID, length(incl \0) 22 */
387 ret = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04"
388 PRIx16 "&dev=%04" PRIx16, fun->vendor_id, fun->device_id);
389 if (ret < 0) {
390 ddf_msg(LVL_ERROR, "Failed creating match ID str");
391 }
392
393 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
394 if (rc != EOK) {
395 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
396 }
397
398 /* Class, subclass, prog IF, revision, length(incl \0) 47 */
399 ret = snprintf(match_id_str, ID_MAX_STR_LEN,
400 "pci/class=%02x&subclass=%02x&progif=%02x&revision=%02x",
401 fun->class_code, fun->subclass_code, fun->prog_if, fun->revision);
402 if (ret < 0) {
403 ddf_msg(LVL_ERROR, "Failed creating match ID str");
404 }
405
406 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 70);
407 if (rc != EOK) {
408 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
409 }
410
411 /* Class, subclass, prog IF, length(incl \0) 35 */
412 ret = snprintf(match_id_str, ID_MAX_STR_LEN,
413 "pci/class=%02x&subclass=%02x&progif=%02x",
414 fun->class_code, fun->subclass_code, fun->prog_if);
415 if (ret < 0) {
416 ddf_msg(LVL_ERROR, "Failed creating match ID str");
417 }
418
419 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 60);
420 if (rc != EOK) {
421 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
422 }
423
424 /* Class, subclass, length(incl \0) 25 */
425 ret = snprintf(match_id_str, ID_MAX_STR_LEN,
426 "pci/class=%02x&subclass=%02x",
427 fun->class_code, fun->subclass_code);
428 if (ret < 0) {
429 ddf_msg(LVL_ERROR, "Failed creating match ID str");
430 }
431
432 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 50);
433 if (rc != EOK) {
434 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
435 }
436
437 /* Class, length(incl \0) 13 */
438 ret = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/class=%02x",
439 fun->class_code);
440 if (ret < 0) {
441 ddf_msg(LVL_ERROR, "Failed creating match ID str");
442 }
443
444 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 40);
445 if (rc != EOK) {
446 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
447 }
448
449 /* TODO add subsys ids, but those exist only in header type 0 */
450}
451
452void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
453 bool io)
454{
455 hw_resource_list_t *hw_res_list = &fun->hw_resources;
456 hw_resource_t *hw_resources = hw_res_list->resources;
457 size_t count = hw_res_list->count;
458
459 assert(hw_resources != NULL);
460 assert(count < PCI_MAX_HW_RES);
461
462 if (io) {
463 hw_resources[count].type = IO_RANGE;
464 hw_resources[count].res.io_range.address = range_addr;
465 hw_resources[count].res.io_range.size = range_size;
466 hw_resources[count].res.io_range.relative = true;
467 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
468 } else {
469 hw_resources[count].type = MEM_RANGE;
470 hw_resources[count].res.mem_range.address = range_addr;
471 hw_resources[count].res.mem_range.size = range_size;
472 hw_resources[count].res.mem_range.relative = false;
473 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
474 }
475
476 hw_res_list->count++;
477}
478
479/** Read the base address register (BAR) of the device and if it contains valid
480 * address add it to the devices hw resource list.
481 *
482 * @param fun PCI function
483 * @param addr The address of the BAR in the PCI configuration address space of
484 * the device
485 * @return The addr the address of the BAR which should be read next
486 */
487int pci_read_bar(pci_fun_t *fun, int addr)
488{
489 /* Value of the BAR */
490 uint32_t val;
491 uint32_t bar;
492 uint32_t mask;
493
494 /* IO space address */
495 bool io;
496 /* 64-bit wide address */
497 bool addrw64;
498
499 /* Size of the io or memory range specified by the BAR */
500 size_t range_size;
501 /* Beginning of the io or memory range specified by the BAR */
502 uint64_t range_addr;
503
504 /* Get the value of the BAR. */
505 val = pci_conf_read_32(fun, addr);
506
507#define IO_MASK (~0x3)
508#define MEM_MASK (~0xf)
509
510 io = (val & 1) != 0;
511 if (io) {
512 addrw64 = false;
513 mask = IO_MASK;
514 } else {
515 mask = MEM_MASK;
516 switch ((val >> 1) & 3) {
517 case 0:
518 addrw64 = false;
519 break;
520 case 2:
521 addrw64 = true;
522 break;
523 default:
524 /* reserved, go to the next BAR */
525 return addr + 4;
526 }
527 }
528
529 /* Get the address mask. */
530 pci_conf_write_32(fun, addr, 0xffffffff);
531 bar = pci_conf_read_32(fun, addr);
532
533 /*
534 * Unimplemented BARs read back as all 0's.
535 */
536 if (!bar)
537 return addr + (addrw64 ? 8 : 4);
538
539 mask &= bar;
540
541 /* Restore the original value. */
542 pci_conf_write_32(fun, addr, val);
543 val = pci_conf_read_32(fun, addr);
544
545 range_size = pci_bar_mask_to_size(mask);
546
547 if (addrw64) {
548 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
549 (val & 0xfffffff0);
550 } else {
551 range_addr = (val & 0xfffffff0);
552 }
553
554 if (range_addr != 0) {
555 ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
556 ", size = %x", ddf_fun_get_name(fun->fnode), range_addr,
557 (unsigned int) range_size);
558 }
559
560 pci_add_range(fun, range_addr, range_size, io);
561
562 if (addrw64)
563 return addr + 8;
564
565 return addr + 4;
566}
567
568void pci_add_interrupt(pci_fun_t *fun, int irq)
569{
570 hw_resource_list_t *hw_res_list = &fun->hw_resources;
571 hw_resource_t *hw_resources = hw_res_list->resources;
572 size_t count = hw_res_list->count;
573
574 assert(NULL != hw_resources);
575 assert(count < PCI_MAX_HW_RES);
576
577 hw_resources[count].type = INTERRUPT;
578 hw_resources[count].res.interrupt.irq = irq;
579
580 hw_res_list->count++;
581
582 ddf_msg(LVL_NOTE, "Function %s uses irq %x.", ddf_fun_get_name(fun->fnode), irq);
583}
584
585void pci_read_interrupt(pci_fun_t *fun)
586{
587 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
588 uint8_t pin = pci_conf_read_8(fun, PCI_BRIDGE_INT_PIN);
589
590 if (pin != 0 && irq != 0xff)
591 pci_add_interrupt(fun, irq);
592}
593
594/** Enumerate (recursively) and register the devices connected to a pci bus.
595 *
596 * @param bus Host-to-PCI bridge
597 * @param bus_num Bus number
598 */
599void pci_bus_scan(pci_bus_t *bus, int bus_num)
600{
601 pci_fun_t *fun;
602 errno_t rc;
603
604 int child_bus = 0;
605 int dnum, fnum;
606 bool multi;
607 uint8_t header_type;
608
609 for (dnum = 0; dnum < 32; dnum++) {
610 multi = true;
611 for (fnum = 0; multi && fnum < 8; fnum++) {
612 fun = pci_fun_new(bus);
613
614 pci_fun_init(fun, bus_num, dnum, fnum);
615 if (fun->vendor_id == 0xffff) {
616 pci_fun_delete(fun);
617 /*
618 * The device is not present, go on scanning the
619 * bus.
620 */
621 if (fnum == 0)
622 break;
623 else
624 continue;
625 }
626
627 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
628 if (fnum == 0) {
629 /* Is the device multifunction? */
630 multi = header_type >> 7;
631 }
632 /* Clear the multifunction bit. */
633 header_type = header_type & 0x7F;
634
635 char *fun_name = pci_fun_create_name(fun);
636 if (fun_name == NULL) {
637 ddf_msg(LVL_ERROR, "Out of memory.");
638 pci_fun_delete(fun);
639 return;
640 }
641
642 rc = ddf_fun_set_name(fun->fnode, fun_name);
643 free(fun_name);
644 if (rc != EOK) {
645 ddf_msg(LVL_ERROR, "Failed setting function name.");
646 pci_fun_delete(fun);
647 return;
648 }
649
650 pci_alloc_resource_list(fun);
651 pci_read_bars(fun);
652 pci_read_interrupt(fun);
653
654 /* Propagate the PIO window to the function. */
655 fun->pio_window = bus->pio_win;
656
657 ddf_fun_set_ops(fun->fnode, &pci_fun_ops);
658
659 ddf_msg(LVL_DEBUG, "Adding new function %s.",
660 ddf_fun_get_name(fun->fnode));
661
662 pci_fun_create_match_ids(fun);
663
664 if (ddf_fun_bind(fun->fnode) != EOK) {
665 pci_clean_resource_list(fun);
666 pci_fun_delete(fun);
667 continue;
668 }
669
670 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
671 header_type == PCI_HEADER_TYPE_CARDBUS) {
672 child_bus = pci_conf_read_8(fun,
673 PCI_BRIDGE_SEC_BUS_NUM);
674 ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
675 "bridge, secondary bus number = %d.",
676 bus_num);
677 if (child_bus > bus_num)
678 pci_bus_scan(bus, child_bus);
679 }
680 }
681 }
682}
683
684static errno_t pci_dev_add(ddf_dev_t *dnode)
685{
686 hw_resource_list_t hw_resources;
687 pci_bus_t *bus = NULL;
688 ddf_fun_t *ctl = NULL;
689 bool got_res = false;
690 async_sess_t *sess;
691 errno_t rc;
692
693 ddf_msg(LVL_DEBUG, "pci_dev_add");
694
695 bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
696 if (bus == NULL) {
697 ddf_msg(LVL_ERROR, "pci_dev_add allocation failed.");
698 rc = ENOMEM;
699 goto fail;
700 }
701 fibril_mutex_initialize(&bus->conf_mutex);
702
703 bus->dnode = dnode;
704
705 sess = ddf_dev_parent_sess_get(dnode);
706 if (sess == NULL) {
707 ddf_msg(LVL_ERROR, "pci_dev_add failed to connect to the "
708 "parent driver.");
709 rc = ENOENT;
710 goto fail;
711 }
712
713 rc = pio_window_get(sess, &bus->pio_win);
714 if (rc != EOK) {
715 ddf_msg(LVL_ERROR, "pci_dev_add failed to get PIO window "
716 "for the device.");
717 goto fail;
718 }
719
720 rc = hw_res_get_resource_list(sess, &hw_resources);
721 if (rc != EOK) {
722 ddf_msg(LVL_ERROR, "pci_dev_add failed to get hw resources "
723 "for the device.");
724 goto fail;
725 }
726 got_res = true;
727
728 assert(hw_resources.count >= 1);
729
730 if (hw_resources.count == 1) {
731 assert(hw_resources.resources[0].type == MEM_RANGE);
732
733 ddf_msg(LVL_DEBUG, "conf_addr_space = %" PRIx64 ".",
734 hw_resources.resources[0].res.mem_range.address);
735
736 if (pio_enable_resource(&bus->pio_win,
737 &hw_resources.resources[0], (void **) &bus->conf_space,
738 NULL, NULL)) {
739 ddf_msg(LVL_ERROR,
740 "Failed to map configuration space.");
741 rc = EADDRNOTAVAIL;
742 goto fail;
743 }
744
745 } else {
746 assert(hw_resources.resources[0].type == IO_RANGE);
747 assert(hw_resources.resources[0].res.io_range.size >= 4);
748
749 assert(hw_resources.resources[1].type == IO_RANGE);
750 assert(hw_resources.resources[1].res.io_range.size >= 4);
751
752 ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
753 hw_resources.resources[0].res.io_range.address);
754 ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
755 hw_resources.resources[1].res.io_range.address);
756
757 if (pio_enable_resource(&bus->pio_win,
758 &hw_resources.resources[0], (void **) &bus->conf_addr_reg,
759 NULL, NULL)) {
760 ddf_msg(LVL_ERROR,
761 "Failed to enable configuration ports.");
762 rc = EADDRNOTAVAIL;
763 goto fail;
764 }
765 if (pio_enable_resource(&bus->pio_win,
766 &hw_resources.resources[1], (void **) &bus->conf_data_reg,
767 NULL, NULL)) {
768 ddf_msg(LVL_ERROR,
769 "Failed to enable configuration ports.");
770 rc = EADDRNOTAVAIL;
771 goto fail;
772 }
773 }
774
775 /* Make the bus device more visible. It has no use yet. */
776 ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
777
778 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
779 if (ctl == NULL) {
780 ddf_msg(LVL_ERROR, "Failed creating control function.");
781 rc = ENOMEM;
782 goto fail;
783 }
784
785 rc = ddf_fun_bind(ctl);
786 if (rc != EOK) {
787 ddf_msg(LVL_ERROR, "Failed binding control function.");
788 goto fail;
789 }
790
791 /* Enumerate functions. */
792 ddf_msg(LVL_DEBUG, "Scanning the bus");
793 pci_bus_scan(bus, 0);
794
795 hw_res_clean_resource_list(&hw_resources);
796
797 return EOK;
798
799fail:
800 if (got_res)
801 hw_res_clean_resource_list(&hw_resources);
802
803 if (ctl != NULL)
804 ddf_fun_destroy(ctl);
805
806 return rc;
807}
808
809static errno_t pci_fun_online(ddf_fun_t *fun)
810{
811 ddf_msg(LVL_DEBUG, "pci_fun_online()");
812 return ddf_fun_online(fun);
813}
814
815static errno_t pci_fun_offline(ddf_fun_t *fun)
816{
817 ddf_msg(LVL_DEBUG, "pci_fun_offline()");
818 return ddf_fun_offline(fun);
819}
820
821static void pciintel_init(void)
822{
823 ddf_log_init(NAME);
824}
825
826pci_fun_t *pci_fun_new(pci_bus_t *bus)
827{
828 pci_fun_t *fun;
829 ddf_fun_t *fnode;
830
831 fnode = ddf_fun_create(bus->dnode, fun_inner, NULL);
832 if (fnode == NULL)
833 return NULL;
834
835 fun = ddf_fun_data_alloc(fnode, sizeof(pci_fun_t));
836 if (fun == NULL)
837 return NULL;
838
839 fun->busptr = bus;
840 fun->fnode = fnode;
841 return fun;
842}
843
844void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
845{
846 fun->bus = bus;
847 fun->dev = dev;
848 fun->fn = fn;
849 fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
850 fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
851
852 /* Explicitly enable PCI bus mastering */
853 fun->command = pci_conf_read_16(fun, PCI_COMMAND) |
854 PCI_COMMAND_MASTER;
855 pci_conf_write_16(fun, PCI_COMMAND, fun->command);
856
857 fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
858 fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
859 fun->prog_if = pci_conf_read_8(fun, PCI_PROG_IF);
860 fun->revision = pci_conf_read_8(fun, PCI_REVISION_ID);
861}
862
863void pci_fun_delete(pci_fun_t *fun)
864{
865 hw_res_clean_resource_list(&fun->hw_resources);
866 if (fun->fnode != NULL)
867 ddf_fun_destroy(fun->fnode);
868}
869
870char *pci_fun_create_name(pci_fun_t *fun)
871{
872 char *name = NULL;
873
874 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
875 fun->fn);
876 return name;
877}
878
879bool pci_alloc_resource_list(pci_fun_t *fun)
880{
881 fun->hw_resources.resources = fun->resources;
882 return true;
883}
884
885void pci_clean_resource_list(pci_fun_t *fun)
886{
887 fun->hw_resources.resources = NULL;
888}
889
890/** Read the base address registers (BARs) of the function and add the addresses
891 * to its HW resource list.
892 *
893 * @param fun PCI function
894 */
895void pci_read_bars(pci_fun_t *fun)
896{
897 /*
898 * Position of the BAR in the PCI configuration address space of the
899 * device.
900 */
901 int addr = PCI_BASE_ADDR_0;
902
903 while (addr <= PCI_BASE_ADDR_5)
904 addr = pci_read_bar(fun, addr);
905}
906
907size_t pci_bar_mask_to_size(uint32_t mask)
908{
909 size_t size = mask & ~(mask - 1);
910 return size;
911}
912
913int main(int argc, char *argv[])
914{
915 printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
916 pciintel_init();
917 return ddf_driver_main(&pci_driver);
918}
919
920/**
921 * @}
922 */
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