source: mainline/uspace/drv/bus/pci/pciintel/pci.c@ 4621d23

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Last change on this file since 4621d23 was 4122410, checked in by Jakub Jermar <jakub@…>, 7 years ago

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1/*
2 * Copyright (c) 2010 Lenka Trochtova
3 * Copyright (c) 2011 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/**
31 * @addtogroup pciintel
32 * @{
33 */
34
35/** @file
36 */
37
38#include <assert.h>
39#include <byteorder.h>
40#include <stdio.h>
41#include <errno.h>
42#include <stdbool.h>
43#include <fibril_synch.h>
44#include <str.h>
45#include <ctype.h>
46#include <macros.h>
47#include <str_error.h>
48
49#include <ddf/driver.h>
50#include <ddf/log.h>
51#include <ipc/dev_iface.h>
52#include <irc.h>
53#include <ops/hw_res.h>
54#include <device/hw_res.h>
55#include <ops/pio_window.h>
56#include <device/pio_window.h>
57#include <ddi.h>
58#include <pci_dev_iface.h>
59
60#include "pci.h"
61
62#define NAME "pciintel"
63
64#define CONF_ADDR_ENABLE (((unsigned)1) << 31)
65#define CONF_ADDR(bus, dev, fn, reg) \
66 ((bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
67
68/** Obtain PCI function soft-state from DDF function node */
69static pci_fun_t *pci_fun(ddf_fun_t *fnode)
70{
71 return ddf_fun_data_get(fnode);
72}
73
74/** Obtain PCI bus soft-state from DDF device node */
75#if 0
76static pci_bus_t *pci_bus(ddf_dev_t *dnode)
77{
78 return ddf_dev_data_get(dnode);
79}
80#endif
81
82/** Obtain PCI bus soft-state from function soft-state */
83static pci_bus_t *pci_bus_from_fun(pci_fun_t *fun)
84{
85 return fun->busptr;
86}
87
88/** Max is 47, align to something nice. */
89#define ID_MAX_STR_LEN 50
90
91static hw_resource_list_t *pciintel_get_resources(ddf_fun_t *fnode)
92{
93 pci_fun_t *fun = pci_fun(fnode);
94
95 if (fun == NULL)
96 return NULL;
97 return &fun->hw_resources;
98}
99
100static bool pciintel_fun_owns_interrupt(pci_fun_t *fun, int irq)
101{
102 size_t i;
103 hw_resource_list_t *res = &fun->hw_resources;
104
105 for (i = 0; i < res->count; i++) {
106 if (res->resources[i].type == INTERRUPT &&
107 res->resources[i].res.interrupt.irq == irq) {
108 return true;
109 }
110 }
111
112 return false;
113}
114
115static errno_t pciintel_enable_interrupt(ddf_fun_t *fnode, int irq)
116{
117 pci_fun_t *fun = pci_fun(fnode);
118
119 if (!pciintel_fun_owns_interrupt(fun, irq))
120 return EINVAL;
121
122 return irc_enable_interrupt(irq);
123}
124
125static errno_t pciintel_disable_interrupt(ddf_fun_t *fnode, int irq)
126{
127 pci_fun_t *fun = pci_fun(fnode);
128
129 if (!pciintel_fun_owns_interrupt(fun, irq))
130 return EINVAL;
131
132 return irc_disable_interrupt(irq);
133}
134
135static errno_t pciintel_clear_interrupt(ddf_fun_t *fnode, int irq)
136{
137 pci_fun_t *fun = pci_fun(fnode);
138
139 if (!pciintel_fun_owns_interrupt(fun, irq))
140 return EINVAL;
141
142 return irc_clear_interrupt(irq);
143}
144
145static pio_window_t *pciintel_get_pio_window(ddf_fun_t *fnode)
146{
147 pci_fun_t *fun = pci_fun(fnode);
148
149 if (fun == NULL)
150 return NULL;
151 return &fun->pio_window;
152}
153
154
155static errno_t config_space_write_32(ddf_fun_t *fun, uint32_t address,
156 uint32_t data)
157{
158 if (address > 252)
159 return EINVAL;
160 pci_conf_write_32(pci_fun(fun), address, data);
161 return EOK;
162}
163
164static errno_t config_space_write_16(
165 ddf_fun_t *fun, uint32_t address, uint16_t data)
166{
167 if (address > 254)
168 return EINVAL;
169 pci_conf_write_16(pci_fun(fun), address, data);
170 return EOK;
171}
172
173static errno_t config_space_write_8(
174 ddf_fun_t *fun, uint32_t address, uint8_t data)
175{
176 if (address > 255)
177 return EINVAL;
178 pci_conf_write_8(pci_fun(fun), address, data);
179 return EOK;
180}
181
182static errno_t config_space_read_32(
183 ddf_fun_t *fun, uint32_t address, uint32_t *data)
184{
185 if (address > 252)
186 return EINVAL;
187 *data = pci_conf_read_32(pci_fun(fun), address);
188 return EOK;
189}
190
191static errno_t config_space_read_16(
192 ddf_fun_t *fun, uint32_t address, uint16_t *data)
193{
194 if (address > 254)
195 return EINVAL;
196 *data = pci_conf_read_16(pci_fun(fun), address);
197 return EOK;
198}
199
200static errno_t config_space_read_8(
201 ddf_fun_t *fun, uint32_t address, uint8_t *data)
202{
203 if (address > 255)
204 return EINVAL;
205 *data = pci_conf_read_8(pci_fun(fun), address);
206 return EOK;
207}
208
209static hw_res_ops_t pciintel_hw_res_ops = {
210 .get_resource_list = &pciintel_get_resources,
211 .enable_interrupt = &pciintel_enable_interrupt,
212 .disable_interrupt = &pciintel_disable_interrupt,
213 .clear_interrupt = &pciintel_clear_interrupt,
214};
215
216static pio_window_ops_t pciintel_pio_window_ops = {
217 .get_pio_window = &pciintel_get_pio_window
218};
219
220static pci_dev_iface_t pci_dev_ops = {
221 .config_space_read_8 = &config_space_read_8,
222 .config_space_read_16 = &config_space_read_16,
223 .config_space_read_32 = &config_space_read_32,
224 .config_space_write_8 = &config_space_write_8,
225 .config_space_write_16 = &config_space_write_16,
226 .config_space_write_32 = &config_space_write_32
227};
228
229static ddf_dev_ops_t pci_fun_ops = {
230 .interfaces[HW_RES_DEV_IFACE] = &pciintel_hw_res_ops,
231 .interfaces[PIO_WINDOW_DEV_IFACE] = &pciintel_pio_window_ops,
232 .interfaces[PCI_DEV_IFACE] = &pci_dev_ops
233};
234
235static errno_t pci_dev_add(ddf_dev_t *);
236static errno_t pci_fun_online(ddf_fun_t *);
237static errno_t pci_fun_offline(ddf_fun_t *);
238
239/** PCI bus driver standard operations */
240static driver_ops_t pci_ops = {
241 .dev_add = &pci_dev_add,
242 .fun_online = &pci_fun_online,
243 .fun_offline = &pci_fun_offline,
244};
245
246/** PCI bus driver structure */
247static driver_t pci_driver = {
248 .name = NAME,
249 .driver_ops = &pci_ops
250};
251
252static void pci_conf_read(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
253{
254 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
255 pci_bus_t *bus = pci_bus_from_fun(fun);
256 uint32_t val;
257
258 fibril_mutex_lock(&bus->conf_mutex);
259
260 if (bus->conf_addr_reg) {
261 pio_write_32(bus->conf_addr_reg,
262 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
263 /*
264 * Always read full 32-bits from the PCI conf_data_port
265 * register and get the desired portion of it afterwards. Some
266 * architectures do not support shorter PIO reads offset from
267 * this register.
268 */
269 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
270 } else {
271 val = uint32_t_le2host(pio_read_32(
272 &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
273 }
274
275 switch (len) {
276 case 1:
277 *buf = (uint8_t) (val >> ((reg & 3) * 8));
278 break;
279 case 2:
280 *((uint16_t *) buf) = (uint16_t) (val >> ((reg & 3)) * 8);
281 break;
282 case 4:
283 *((uint32_t *) buf) = (uint32_t) val;
284 break;
285 }
286
287 fibril_mutex_unlock(&bus->conf_mutex);
288}
289
290static void pci_conf_write(pci_fun_t *fun, int reg, uint8_t *buf, size_t len)
291{
292 const uint32_t conf_addr = CONF_ADDR(fun->bus, fun->dev, fun->fn, reg);
293 pci_bus_t *bus = pci_bus_from_fun(fun);
294 uint32_t val = 0;
295
296 fibril_mutex_lock(&bus->conf_mutex);
297
298 /*
299 * Prepare to write full 32-bits to the PCI conf_data_port register.
300 * Some architectures do not support shorter PIO writes offset from this
301 * register.
302 */
303
304 if (len < 4) {
305 /*
306 * We have fewer than full 32-bits, so we need to read the
307 * missing bits first.
308 */
309 if (bus->conf_addr_reg) {
310 pio_write_32(bus->conf_addr_reg,
311 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
312 val = uint32_t_le2host(pio_read_32(bus->conf_data_reg));
313 } else {
314 val = uint32_t_le2host(pio_read_32(
315 &bus->conf_space[conf_addr / sizeof(ioport32_t)]));
316 }
317 }
318
319 switch (len) {
320 case 1:
321 val &= ~(0xffU << ((reg & 3) * 8));
322 val |= *buf << ((reg & 3) * 8);
323 break;
324 case 2:
325 val &= ~(0xffffU << ((reg & 3) * 8));
326 val |= *((uint16_t *) buf) << ((reg & 3) * 8);
327 break;
328 case 4:
329 val = *((uint32_t *) buf);
330 break;
331 }
332
333 if (bus->conf_addr_reg) {
334 pio_write_32(bus->conf_addr_reg,
335 host2uint32_t_le(CONF_ADDR_ENABLE | conf_addr));
336 pio_write_32(bus->conf_data_reg, host2uint32_t_le(val));
337 } else {
338 pio_write_32(&bus->conf_space[conf_addr / sizeof(ioport32_t)],
339 host2uint32_t_le(val));
340 }
341
342 fibril_mutex_unlock(&bus->conf_mutex);
343}
344
345uint8_t pci_conf_read_8(pci_fun_t *fun, int reg)
346{
347 uint8_t res;
348 pci_conf_read(fun, reg, &res, 1);
349 return res;
350}
351
352uint16_t pci_conf_read_16(pci_fun_t *fun, int reg)
353{
354 uint16_t res;
355 pci_conf_read(fun, reg, (uint8_t *) &res, 2);
356 return res;
357}
358
359uint32_t pci_conf_read_32(pci_fun_t *fun, int reg)
360{
361 uint32_t res;
362 pci_conf_read(fun, reg, (uint8_t *) &res, 4);
363 return res;
364}
365
366void pci_conf_write_8(pci_fun_t *fun, int reg, uint8_t val)
367{
368 pci_conf_write(fun, reg, (uint8_t *) &val, 1);
369}
370
371void pci_conf_write_16(pci_fun_t *fun, int reg, uint16_t val)
372{
373 pci_conf_write(fun, reg, (uint8_t *) &val, 2);
374}
375
376void pci_conf_write_32(pci_fun_t *fun, int reg, uint32_t val)
377{
378 pci_conf_write(fun, reg, (uint8_t *) &val, 4);
379}
380
381void pci_fun_create_match_ids(pci_fun_t *fun)
382{
383 errno_t rc;
384 int ret;
385 char match_id_str[ID_MAX_STR_LEN];
386
387 /* Vendor ID & Device ID, length(incl \0) 22 */
388 ret = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/ven=%04"
389 PRIx16 "&dev=%04" PRIx16, fun->vendor_id, fun->device_id);
390 if (ret < 0) {
391 ddf_msg(LVL_ERROR, "Failed creating match ID str");
392 }
393
394 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 90);
395 if (rc != EOK) {
396 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
397 }
398
399 /* Class, subclass, prog IF, revision, length(incl \0) 47 */
400 ret = snprintf(match_id_str, ID_MAX_STR_LEN,
401 "pci/class=%02x&subclass=%02x&progif=%02x&revision=%02x",
402 fun->class_code, fun->subclass_code, fun->prog_if, fun->revision);
403 if (ret < 0) {
404 ddf_msg(LVL_ERROR, "Failed creating match ID str");
405 }
406
407 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 70);
408 if (rc != EOK) {
409 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
410 }
411
412 /* Class, subclass, prog IF, length(incl \0) 35 */
413 ret = snprintf(match_id_str, ID_MAX_STR_LEN,
414 "pci/class=%02x&subclass=%02x&progif=%02x",
415 fun->class_code, fun->subclass_code, fun->prog_if);
416 if (ret < 0) {
417 ddf_msg(LVL_ERROR, "Failed creating match ID str");
418 }
419
420 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 60);
421 if (rc != EOK) {
422 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
423 }
424
425 /* Class, subclass, length(incl \0) 25 */
426 ret = snprintf(match_id_str, ID_MAX_STR_LEN,
427 "pci/class=%02x&subclass=%02x",
428 fun->class_code, fun->subclass_code);
429 if (ret < 0) {
430 ddf_msg(LVL_ERROR, "Failed creating match ID str");
431 }
432
433 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 50);
434 if (rc != EOK) {
435 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
436 }
437
438 /* Class, length(incl \0) 13 */
439 ret = snprintf(match_id_str, ID_MAX_STR_LEN, "pci/class=%02x",
440 fun->class_code);
441 if (ret < 0) {
442 ddf_msg(LVL_ERROR, "Failed creating match ID str");
443 }
444
445 rc = ddf_fun_add_match_id(fun->fnode, match_id_str, 40);
446 if (rc != EOK) {
447 ddf_msg(LVL_ERROR, "Failed adding match ID: %s", str_error(rc));
448 }
449
450 /* TODO add subsys ids, but those exist only in header type 0 */
451}
452
453void pci_add_range(pci_fun_t *fun, uint64_t range_addr, size_t range_size,
454 bool io)
455{
456 hw_resource_list_t *hw_res_list = &fun->hw_resources;
457 hw_resource_t *hw_resources = hw_res_list->resources;
458 size_t count = hw_res_list->count;
459
460 assert(hw_resources != NULL);
461 assert(count < PCI_MAX_HW_RES);
462
463 if (io) {
464 hw_resources[count].type = IO_RANGE;
465 hw_resources[count].res.io_range.address = range_addr;
466 hw_resources[count].res.io_range.size = range_size;
467 hw_resources[count].res.io_range.relative = true;
468 hw_resources[count].res.io_range.endianness = LITTLE_ENDIAN;
469 } else {
470 hw_resources[count].type = MEM_RANGE;
471 hw_resources[count].res.mem_range.address = range_addr;
472 hw_resources[count].res.mem_range.size = range_size;
473 hw_resources[count].res.mem_range.relative = false;
474 hw_resources[count].res.mem_range.endianness = LITTLE_ENDIAN;
475 }
476
477 hw_res_list->count++;
478}
479
480/** Read the base address register (BAR) of the device and if it contains valid
481 * address add it to the devices hw resource list.
482 *
483 * @param fun PCI function
484 * @param addr The address of the BAR in the PCI configuration address space of
485 * the device
486 * @return The addr the address of the BAR which should be read next
487 */
488int pci_read_bar(pci_fun_t *fun, int addr)
489{
490 /* Value of the BAR */
491 uint32_t val;
492 uint32_t bar;
493 uint32_t mask;
494
495 /* IO space address */
496 bool io;
497 /* 64-bit wide address */
498 bool addrw64;
499
500 /* Size of the io or memory range specified by the BAR */
501 size_t range_size;
502 /* Beginning of the io or memory range specified by the BAR */
503 uint64_t range_addr;
504
505 /* Get the value of the BAR. */
506 val = pci_conf_read_32(fun, addr);
507
508#define IO_MASK (~0x3)
509#define MEM_MASK (~0xf)
510
511 io = (val & 1) != 0;
512 if (io) {
513 addrw64 = false;
514 mask = IO_MASK;
515 } else {
516 mask = MEM_MASK;
517 switch ((val >> 1) & 3) {
518 case 0:
519 addrw64 = false;
520 break;
521 case 2:
522 addrw64 = true;
523 break;
524 default:
525 /* reserved, go to the next BAR */
526 return addr + 4;
527 }
528 }
529
530 /* Get the address mask. */
531 pci_conf_write_32(fun, addr, 0xffffffff);
532 bar = pci_conf_read_32(fun, addr);
533
534 /*
535 * Unimplemented BARs read back as all 0's.
536 */
537 if (!bar)
538 return addr + (addrw64 ? 8 : 4);
539
540 mask &= bar;
541
542 /* Restore the original value. */
543 pci_conf_write_32(fun, addr, val);
544 val = pci_conf_read_32(fun, addr);
545
546 range_size = pci_bar_mask_to_size(mask);
547
548 if (addrw64) {
549 range_addr = ((uint64_t)pci_conf_read_32(fun, addr + 4) << 32) |
550 (val & 0xfffffff0);
551 } else {
552 range_addr = (val & 0xfffffff0);
553 }
554
555 if (range_addr != 0) {
556 ddf_msg(LVL_DEBUG, "Function %s : address = %" PRIx64
557 ", size = %x", ddf_fun_get_name(fun->fnode), range_addr,
558 (unsigned int) range_size);
559 }
560
561 pci_add_range(fun, range_addr, range_size, io);
562
563 if (addrw64)
564 return addr + 8;
565
566 return addr + 4;
567}
568
569void pci_add_interrupt(pci_fun_t *fun, int irq)
570{
571 hw_resource_list_t *hw_res_list = &fun->hw_resources;
572 hw_resource_t *hw_resources = hw_res_list->resources;
573 size_t count = hw_res_list->count;
574
575 assert(NULL != hw_resources);
576 assert(count < PCI_MAX_HW_RES);
577
578 hw_resources[count].type = INTERRUPT;
579 hw_resources[count].res.interrupt.irq = irq;
580
581 hw_res_list->count++;
582
583 ddf_msg(LVL_NOTE, "Function %s uses irq %x.", ddf_fun_get_name(fun->fnode), irq);
584}
585
586void pci_read_interrupt(pci_fun_t *fun)
587{
588 uint8_t irq = pci_conf_read_8(fun, PCI_BRIDGE_INT_LINE);
589 uint8_t pin = pci_conf_read_8(fun, PCI_BRIDGE_INT_PIN);
590
591 if (pin != 0 && irq != 0xff)
592 pci_add_interrupt(fun, irq);
593}
594
595/** Enumerate (recursively) and register the devices connected to a pci bus.
596 *
597 * @param bus Host-to-PCI bridge
598 * @param bus_num Bus number
599 */
600void pci_bus_scan(pci_bus_t *bus, int bus_num)
601{
602 pci_fun_t *fun;
603 errno_t rc;
604
605 int child_bus = 0;
606 int dnum, fnum;
607 bool multi;
608 uint8_t header_type;
609
610 for (dnum = 0; dnum < 32; dnum++) {
611 multi = true;
612 for (fnum = 0; multi && fnum < 8; fnum++) {
613 fun = pci_fun_new(bus);
614
615 pci_fun_init(fun, bus_num, dnum, fnum);
616 if (fun->vendor_id == 0xffff) {
617 pci_fun_delete(fun);
618 /*
619 * The device is not present, go on scanning the
620 * bus.
621 */
622 if (fnum == 0)
623 break;
624 else
625 continue;
626 }
627
628 header_type = pci_conf_read_8(fun, PCI_HEADER_TYPE);
629 if (fnum == 0) {
630 /* Is the device multifunction? */
631 multi = header_type >> 7;
632 }
633 /* Clear the multifunction bit. */
634 header_type = header_type & 0x7F;
635
636 char *fun_name = pci_fun_create_name(fun);
637 if (fun_name == NULL) {
638 ddf_msg(LVL_ERROR, "Out of memory.");
639 pci_fun_delete(fun);
640 return;
641 }
642
643 rc = ddf_fun_set_name(fun->fnode, fun_name);
644 free(fun_name);
645 if (rc != EOK) {
646 ddf_msg(LVL_ERROR, "Failed setting function name.");
647 pci_fun_delete(fun);
648 return;
649 }
650
651 pci_alloc_resource_list(fun);
652 pci_read_bars(fun);
653 pci_read_interrupt(fun);
654
655 /* Propagate the PIO window to the function. */
656 fun->pio_window = bus->pio_win;
657
658 ddf_fun_set_ops(fun->fnode, &pci_fun_ops);
659
660 ddf_msg(LVL_DEBUG, "Adding new function %s.",
661 ddf_fun_get_name(fun->fnode));
662
663 pci_fun_create_match_ids(fun);
664
665 if (ddf_fun_bind(fun->fnode) != EOK) {
666 pci_clean_resource_list(fun);
667 pci_fun_delete(fun);
668 continue;
669 }
670
671 if (header_type == PCI_HEADER_TYPE_BRIDGE ||
672 header_type == PCI_HEADER_TYPE_CARDBUS) {
673 child_bus = pci_conf_read_8(fun,
674 PCI_BRIDGE_SEC_BUS_NUM);
675 ddf_msg(LVL_DEBUG, "Device is pci-to-pci "
676 "bridge, secondary bus number = %d.",
677 bus_num);
678 if (child_bus > bus_num)
679 pci_bus_scan(bus, child_bus);
680 }
681 }
682 }
683}
684
685static errno_t pci_dev_add(ddf_dev_t *dnode)
686{
687 hw_resource_list_t hw_resources;
688 pci_bus_t *bus = NULL;
689 ddf_fun_t *ctl = NULL;
690 bool got_res = false;
691 async_sess_t *sess;
692 errno_t rc;
693
694 ddf_msg(LVL_DEBUG, "pci_dev_add");
695
696 bus = ddf_dev_data_alloc(dnode, sizeof(pci_bus_t));
697 if (bus == NULL) {
698 ddf_msg(LVL_ERROR, "pci_dev_add allocation failed.");
699 rc = ENOMEM;
700 goto fail;
701 }
702 fibril_mutex_initialize(&bus->conf_mutex);
703
704 bus->dnode = dnode;
705
706 sess = ddf_dev_parent_sess_get(dnode);
707 if (sess == NULL) {
708 ddf_msg(LVL_ERROR, "pci_dev_add failed to connect to the "
709 "parent driver.");
710 rc = ENOENT;
711 goto fail;
712 }
713
714 rc = pio_window_get(sess, &bus->pio_win);
715 if (rc != EOK) {
716 ddf_msg(LVL_ERROR, "pci_dev_add failed to get PIO window "
717 "for the device.");
718 goto fail;
719 }
720
721 rc = hw_res_get_resource_list(sess, &hw_resources);
722 if (rc != EOK) {
723 ddf_msg(LVL_ERROR, "pci_dev_add failed to get hw resources "
724 "for the device.");
725 goto fail;
726 }
727 got_res = true;
728
729
730 assert(hw_resources.count >= 1);
731
732 if (hw_resources.count == 1) {
733 assert(hw_resources.resources[0].type == MEM_RANGE);
734
735 ddf_msg(LVL_DEBUG, "conf_addr_space = %" PRIx64 ".",
736 hw_resources.resources[0].res.mem_range.address);
737
738 if (pio_enable_resource(&bus->pio_win,
739 &hw_resources.resources[0], (void **) &bus->conf_space,
740 NULL, NULL)) {
741 ddf_msg(LVL_ERROR,
742 "Failed to map configuration space.");
743 rc = EADDRNOTAVAIL;
744 goto fail;
745 }
746
747 } else {
748 assert(hw_resources.resources[0].type == IO_RANGE);
749 assert(hw_resources.resources[0].res.io_range.size >= 4);
750
751 assert(hw_resources.resources[1].type == IO_RANGE);
752 assert(hw_resources.resources[1].res.io_range.size >= 4);
753
754 ddf_msg(LVL_DEBUG, "conf_addr = %" PRIx64 ".",
755 hw_resources.resources[0].res.io_range.address);
756 ddf_msg(LVL_DEBUG, "data_addr = %" PRIx64 ".",
757 hw_resources.resources[1].res.io_range.address);
758
759 if (pio_enable_resource(&bus->pio_win,
760 &hw_resources.resources[0], (void **) &bus->conf_addr_reg,
761 NULL, NULL)) {
762 ddf_msg(LVL_ERROR,
763 "Failed to enable configuration ports.");
764 rc = EADDRNOTAVAIL;
765 goto fail;
766 }
767 if (pio_enable_resource(&bus->pio_win,
768 &hw_resources.resources[1], (void **) &bus->conf_data_reg,
769 NULL, NULL)) {
770 ddf_msg(LVL_ERROR,
771 "Failed to enable configuration ports.");
772 rc = EADDRNOTAVAIL;
773 goto fail;
774 }
775 }
776
777 /* Make the bus device more visible. It has no use yet. */
778 ddf_msg(LVL_DEBUG, "Adding a 'ctl' function");
779
780 ctl = ddf_fun_create(bus->dnode, fun_exposed, "ctl");
781 if (ctl == NULL) {
782 ddf_msg(LVL_ERROR, "Failed creating control function.");
783 rc = ENOMEM;
784 goto fail;
785 }
786
787 rc = ddf_fun_bind(ctl);
788 if (rc != EOK) {
789 ddf_msg(LVL_ERROR, "Failed binding control function.");
790 goto fail;
791 }
792
793 /* Enumerate functions. */
794 ddf_msg(LVL_DEBUG, "Scanning the bus");
795 pci_bus_scan(bus, 0);
796
797 hw_res_clean_resource_list(&hw_resources);
798
799 return EOK;
800
801fail:
802 if (got_res)
803 hw_res_clean_resource_list(&hw_resources);
804
805 if (ctl != NULL)
806 ddf_fun_destroy(ctl);
807
808 return rc;
809}
810
811static errno_t pci_fun_online(ddf_fun_t *fun)
812{
813 ddf_msg(LVL_DEBUG, "pci_fun_online()");
814 return ddf_fun_online(fun);
815}
816
817static errno_t pci_fun_offline(ddf_fun_t *fun)
818{
819 ddf_msg(LVL_DEBUG, "pci_fun_offline()");
820 return ddf_fun_offline(fun);
821}
822
823static void pciintel_init(void)
824{
825 ddf_log_init(NAME);
826}
827
828pci_fun_t *pci_fun_new(pci_bus_t *bus)
829{
830 pci_fun_t *fun;
831 ddf_fun_t *fnode;
832
833 fnode = ddf_fun_create(bus->dnode, fun_inner, NULL);
834 if (fnode == NULL)
835 return NULL;
836
837 fun = ddf_fun_data_alloc(fnode, sizeof(pci_fun_t));
838 if (fun == NULL)
839 return NULL;
840
841 fun->busptr = bus;
842 fun->fnode = fnode;
843 return fun;
844}
845
846void pci_fun_init(pci_fun_t *fun, int bus, int dev, int fn)
847{
848 fun->bus = bus;
849 fun->dev = dev;
850 fun->fn = fn;
851 fun->vendor_id = pci_conf_read_16(fun, PCI_VENDOR_ID);
852 fun->device_id = pci_conf_read_16(fun, PCI_DEVICE_ID);
853
854 /* Explicitly enable PCI bus mastering */
855 fun->command = pci_conf_read_16(fun, PCI_COMMAND) |
856 PCI_COMMAND_MASTER;
857 pci_conf_write_16(fun, PCI_COMMAND, fun->command);
858
859 fun->class_code = pci_conf_read_8(fun, PCI_BASE_CLASS);
860 fun->subclass_code = pci_conf_read_8(fun, PCI_SUB_CLASS);
861 fun->prog_if = pci_conf_read_8(fun, PCI_PROG_IF);
862 fun->revision = pci_conf_read_8(fun, PCI_REVISION_ID);
863}
864
865void pci_fun_delete(pci_fun_t *fun)
866{
867 hw_res_clean_resource_list(&fun->hw_resources);
868 if (fun->fnode != NULL)
869 ddf_fun_destroy(fun->fnode);
870}
871
872char *pci_fun_create_name(pci_fun_t *fun)
873{
874 char *name = NULL;
875
876 asprintf(&name, "%02x:%02x.%01x", fun->bus, fun->dev,
877 fun->fn);
878 return name;
879}
880
881bool pci_alloc_resource_list(pci_fun_t *fun)
882{
883 fun->hw_resources.resources = fun->resources;
884 return true;
885}
886
887void pci_clean_resource_list(pci_fun_t *fun)
888{
889 fun->hw_resources.resources = NULL;
890}
891
892/** Read the base address registers (BARs) of the function and add the addresses
893 * to its HW resource list.
894 *
895 * @param fun PCI function
896 */
897void pci_read_bars(pci_fun_t *fun)
898{
899 /*
900 * Position of the BAR in the PCI configuration address space of the
901 * device.
902 */
903 int addr = PCI_BASE_ADDR_0;
904
905 while (addr <= PCI_BASE_ADDR_5)
906 addr = pci_read_bar(fun, addr);
907}
908
909size_t pci_bar_mask_to_size(uint32_t mask)
910{
911 size_t size = mask & ~(mask - 1);
912 return size;
913}
914
915int main(int argc, char *argv[])
916{
917 printf(NAME ": HelenOS PCI bus driver (Intel method 1).\n");
918 pciintel_init();
919 return ddf_driver_main(&pci_driver);
920}
921
922/**
923 * @}
924 */
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