source: mainline/uspace/drv/bus/isa/i8237.c@ 8486c07

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8486c07 was d9cf684a, checked in by Martin Decky <martin@…>, 14 years ago

cherrypick and adopt Intel 8237A DMA controller support from bzr://krabicka.net/orome/helenos/audio/
  • Property mode set to 100644
File size: 10.9 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup isa
30 * @{
31 */
32
33/** @file
34 * @brief DMA controller management
35 */
36
37#include <assert.h>
38#include <bool.h>
39#include <errno.h>
40#include <fibril_synch.h>
41#include <ddi.h>
42#include <libarch/ddi.h>
43#include <ddf/log.h>
44#include "i8237.h"
45
46/** DMA Slave controller I/O Address. */
47#define DMA_CONTROLLER_FIRST_BASE ((void *) 0x00)
48
49/** DMA Master controller I/O Address. */
50#define DMA_CONTROLLER_SECOND_BASE ((void *) 0xc0)
51
52/** Shared DMA page address register I/O address. */
53#define DMA_CONTROLLER_PAGE_BASE ((void *) 0x81)
54
55#define DMA_STATUS_REQ(x) (1 << (((x) % 4) + 4))
56#define DMA_STATUS_COMPLETE(x) (1 << ((x) % 4))
57
58/** http://wiki.osdev.org/DMA: The only bit that works is COND (bit 2) */
59#define DMA_COMMAND_COND (1 << 2) /**< Disables DMA controller */
60
61#define DMA_SINGLE_MASK_CHAN_SEL_MASK 0x03
62#define DMA_SINGLE_MASK_CHAN_SEL_SHIFT 0
63
64#define DMA_SINGLE_MASK_CHAN_TO_REG(x) \
65 (((x) & DMA_SINGLE_MASK_CHAN_SEL_MASK) << DMA_SINGLE_MASK_CHAN_SEL_SHIFT)
66
67#define DMA_SINGLE_MASK_MASKED_FLAG (1 << 2)
68
69#define DMA_MODE_CHAN_SELECT_MASK 0x03
70#define DMA_MODE_CHAN_SELECT_SHIFT 0
71
72#define DMA_MODE_CHAN_TO_REG(x) \
73 (((x) & DMA_MODE_CHAN_SELECT_MASK) << DMA_MODE_CHAN_SELECT_SHIFT)
74
75#define DMA_MODE_CHAN_TRA_MASK 0x03
76#define DMA_MODE_CHAN_TRA_SHIFT 2
77#define DMA_MODE_CHAN_TRA_SELF_TEST 0
78#define DMA_MODE_CHAN_TRA_WRITE 0x01
79#define DMA_MODE_CHAN_TRA_READ 0x02
80
81#define DMA_MODE_CHAN_AUTO_FLAG (1 << 4)
82#define DMA_MODE_CHAN_DOWN_FLAG (1 << 5)
83
84#define DMA_MODE_CHAN_MODE_MASK 0x03
85#define DMA_MODE_CHAN_MODE_SHIFT 6
86#define DMA_MODE_CHAN_MODE_DEMAND 0
87#define DMA_MODE_CHAN_MODE_SINGLE 1
88#define DMA_MODE_CHAN_MODE_BLOCK 2
89#define DMA_MODE_CHAN_MODE_CASCADE 3
90
91#define DMA_MULTI_MASK_CHAN(x) (1 << ((x) % 4))
92
93typedef struct {
94 uint8_t channel_start0;
95 uint8_t channel_count0;
96 uint8_t channel_start1;
97 uint8_t channel_count1;
98 uint8_t channel_start2;
99 uint8_t channel_count2;
100 uint8_t channel_start3;
101 uint8_t channel_count3;
102
103 uint8_t command_status;
104
105 /** Memory to memory transfers, NOT implemented on PCs */
106 uint8_t request;
107 uint8_t single_mask;
108 uint8_t mode;
109 uint8_t flip_flop;
110
111 /*
112 * Master reset sets Flip-Flop low, clears status,
113 * sets all mask bits on.
114 *
115 * Intermediate is not implemented on PCs.
116 *
117 */
118 uint8_t master_reset;
119 uint8_t mask_reset;
120 uint8_t multi_mask;
121} dma_controller_regs_first_t;
122
123typedef struct {
124 uint8_t channel_start4;
125 uint8_t reserved0;
126 uint8_t channel_count4;
127 uint8_t reserved1;
128 uint8_t channel_start5;
129 uint8_t reserved2;
130 uint8_t channel_count5;
131 uint8_t reserved3;
132 uint8_t channel_start6;
133 uint8_t reserved4;
134 uint8_t channel_count6;
135 uint8_t reserved5;
136 uint8_t channel_start7;
137 uint8_t reserved6;
138 uint8_t channel_count7;
139
140 uint8_t command_status;
141 uint8_t reserved8;
142 uint8_t request;
143 uint8_t reserved9;
144 uint8_t single_mask;
145 uint8_t reserveda;
146 uint8_t mode;
147 uint8_t reservedb;
148 uint8_t flip_flop;
149 uint8_t reservedc;
150 uint8_t master_reset;
151 uint8_t reservedd;
152 uint8_t multi_mask;
153} dma_controller_regs_second_t;
154
155typedef struct {
156 uint8_t channel2;
157 uint8_t channel3;
158 uint8_t channel1;
159 uint8_t reserved0;
160 uint8_t reserved1;
161 uint8_t reserved2;
162 uint8_t channel0;
163 uint8_t reserved3;
164 uint8_t channel6;
165 uint8_t channel7;
166 uint8_t channel5;
167 uint8_t reserved4;
168 uint8_t reserved5;
169 uint8_t reserved6;
170 uint8_t channel4;
171} dma_page_regs_t;
172
173/** Addresses needed to setup a DMA channel. */
174typedef struct {
175 ioport8_t *offset_reg_address;
176 ioport8_t *size_reg_address;
177 ioport8_t *page_reg_address;
178 ioport8_t *single_mask_address;
179 ioport8_t *mode_address;
180 ioport8_t *flip_flop_address;
181} dma_channel_t;
182
183typedef struct {
184 dma_channel_t channels[8];
185 dma_page_regs_t *page_table;
186 dma_controller_regs_first_t *first;
187 dma_controller_regs_second_t *second;
188 bool initialized;
189} dma_controller_t;
190
191static fibril_mutex_t guard = FIBRIL_MUTEX_INITIALIZER(guard);
192
193/** Standard i8237 DMA controller.
194 *
195 * http://zet.aluzina.org/index.php/8237_DMA_controller#DMA_Channel_Registers
196 *
197 */
198static dma_controller_t controller_8237 = {
199 .channels = {
200 /* The first chip 8-bit */
201 {
202 (uint8_t *) 0x00,
203 (uint8_t *) 0x01,
204 (uint8_t *) 0x87,
205 (uint8_t *) 0x0a,
206 (uint8_t *) 0x0b,
207 (uint8_t *) 0x0c,
208 },
209 {
210 (uint8_t *) 0x02,
211 (uint8_t *) 0x03,
212 (uint8_t *) 0x83,
213 (uint8_t *) 0x0a,
214 (uint8_t *) 0x0b,
215 (uint8_t *) 0x0c,
216 },
217 {
218 (uint8_t *) 0x04,
219 (uint8_t *) 0x05,
220 (uint8_t *) 0x81,
221 (uint8_t *) 0x0a,
222 (uint8_t *) 0x0b,
223 (uint8_t *) 0x0c,
224 },
225 {
226 (uint8_t *) 0x06,
227 (uint8_t *) 0x07,
228 (uint8_t *) 0x82,
229 (uint8_t *) 0x0a,
230 (uint8_t *) 0x0b,
231 (uint8_t *) 0x0c,
232 },
233
234 /* The second chip 16-bit */
235 {
236 (uint8_t *) 0xc0,
237 (uint8_t *) 0xc2,
238 (uint8_t *) 0x8f,
239 (uint8_t *) 0xd4,
240 (uint8_t *) 0xd6,
241 (uint8_t *) 0xd8,
242 },
243 {
244 (uint8_t *) 0xc4,
245 (uint8_t *) 0xc6,
246 (uint8_t *) 0x8b,
247 (uint8_t *) 0xd4,
248 (uint8_t *) 0xd6,
249 (uint8_t *) 0xd8,
250 },
251 {
252 (uint8_t *) 0xc8,
253 (uint8_t *) 0xca,
254 (uint8_t *) 0x89,
255 (uint8_t *) 0xd4,
256 (uint8_t *) 0xd6,
257 (uint8_t *) 0xd8,
258 },
259 {
260 (uint8_t *) 0xcc,
261 (uint8_t *) 0xce,
262 (uint8_t *) 0x8a,
263 (uint8_t *) 0xd4,
264 (uint8_t *) 0xd6,
265 (uint8_t *) 0xd8,
266 },
267 },
268
269 .page_table = NULL,
270 .first = NULL,
271 .second = NULL,
272 .initialized = false,
273};
274
275/* Initialize I/O access to DMA controller I/O ports.
276 *
277 * @param controller DMA Controller structure to initialize.
278 *
279 * @return Error code.
280 *
281 */
282static inline int dma_controller_init(dma_controller_t *controller)
283{
284 assert(controller);
285 int ret = pio_enable(DMA_CONTROLLER_PAGE_BASE, sizeof(dma_page_regs_t),
286 (void **) &controller->page_table);
287 if (ret != EOK)
288 return EIO;
289
290 ret = pio_enable(DMA_CONTROLLER_FIRST_BASE,
291 sizeof(dma_controller_regs_first_t), (void **) &controller->first);
292 if (ret != EOK)
293 return EIO;
294
295 ret = pio_enable(DMA_CONTROLLER_SECOND_BASE,
296 sizeof(dma_controller_regs_second_t), (void **) &controller->second);
297 if (ret != EOK)
298 return EIO;
299
300 controller->initialized = true;
301
302 /* Reset the controller */
303 pio_write_8(&controller->second->master_reset, 0xff);
304 pio_write_8(&controller->first->master_reset, 0xff);
305
306 return EOK;
307}
308
309/** Setup DMA channel to specified place and mode.
310 *
311 * @param channel DMA Channel 1, 2, 3 for 8 bit transfers,
312 * 5, 6, 7 for 16 bit.
313 * @param pa Physical address of the buffer. Must be < 16 MB
314 * for 16 bit and < 1 MB for 8 bit transfers.
315 * @param size DMA buffer size, limited to 64 KB.
316 * @param mode Mode of the DMA channel:
317 * - Read or Write
318 * - Allow automatic reset
319 * - Use address decrement instead of increment
320 * - Use SINGLE/BLOCK/ON DEMAND transfer mode
321 *
322 * @return Error code.
323 *
324 */
325int dma_setup_channel(unsigned int channel, uint32_t pa, uint16_t size,
326 uint8_t mode)
327{
328 if ((channel == 0) || (channel == 4))
329 return ENOTSUP;
330
331 if (channel > 7)
332 return ENOENT;
333
334 /* DMA is limited to 24bit addresses. */
335 if (pa >= (1 << 24))
336 return EINVAL;
337
338 /* 8 bit channels use only 4 bits from the page register. */
339 if ((channel > 0) && (channel < 4) && (pa >= (1 << 20)))
340 return EINVAL;
341
342 fibril_mutex_lock(&guard);
343
344 if (!controller_8237.initialized)
345 dma_controller_init(&controller_8237);
346
347 if (!controller_8237.initialized) {
348 fibril_mutex_unlock(&guard);
349 return EIO;
350 }
351
352 /* 16 bit transfers are a bit special */
353 ddf_msg(LVL_DEBUG, "Unspoiled address: %p and size: %zu.", pa, size);
354 if (channel > 4) {
355 /* Size must be aligned to 16 bits */
356 if ((size & 1) != 0) {
357 fibril_mutex_unlock(&guard);
358 return EINVAL;
359 }
360
361 size >>= 1;
362
363 /* Address is fun: lower 16 bits need to be shifted by 1 */
364 pa = ((pa & 0xffff) >> 1) | (pa & 0xff0000);
365 }
366
367 const dma_channel_t dma_channel = controller_8237.channels[channel];
368
369 ddf_msg(LVL_DEBUG, "Setting channel %u, to address %p(%zu), mode %hhx.",
370 channel, pa, size, mode);
371
372 /* Mask DMA request */
373 uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel) |
374 DMA_SINGLE_MASK_MASKED_FLAG;
375 pio_write_8(dma_channel.single_mask_address, value);
376
377 /* Set mode */
378 value = DMA_MODE_CHAN_TO_REG(channel) | mode;
379 ddf_msg(LVL_DEBUG2, "Writing mode byte: %p:%hhx.",
380 dma_channel.mode_address, value);
381 pio_write_8(dma_channel.mode_address, value);
382
383 /* Set address - reset flip-flop */
384 pio_write_8(dma_channel.flip_flop_address, 0);
385
386 /* Low byte */
387 value = pa & 0xff;
388 ddf_msg(LVL_DEBUG2, "Writing address low byte: %p:%hhx.",
389 dma_channel.offset_reg_address, value);
390 pio_write_8(dma_channel.offset_reg_address, value);
391
392 /* High byte */
393 value = (pa >> 8) & 0xff;
394 ddf_msg(LVL_DEBUG2, "Writing address high byte: %p:%hhx.",
395 dma_channel.offset_reg_address, value);
396 pio_write_8(dma_channel.offset_reg_address, value);
397
398 /* Page address - third byte */
399 value = (pa >> 16) & 0xff;
400 ddf_msg(LVL_DEBUG2, "Writing address page byte: %p:%hhx.",
401 dma_channel.page_reg_address, value);
402 pio_write_8(dma_channel.page_reg_address, value);
403
404 /* Set size - reset flip-flop */
405 pio_write_8(dma_channel.flip_flop_address, 0);
406
407 /* Low byte */
408 value = (size - 1) & 0xff;
409 ddf_msg(LVL_DEBUG2, "Writing size low byte: %p:%hhx.",
410 dma_channel.size_reg_address, value);
411 pio_write_8(dma_channel.size_reg_address, value);
412
413 /* High byte */
414 value = ((size - 1) >> 8) & 0xff;
415 ddf_msg(LVL_DEBUG2, "Writing size high byte: %p:%hhx.",
416 dma_channel.size_reg_address, value);
417 pio_write_8(dma_channel.size_reg_address, value);
418
419 /* Unmask DMA request */
420 value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
421 pio_write_8(dma_channel.single_mask_address, value);
422
423 fibril_mutex_unlock(&guard);
424
425 return EOK;
426}
427
428/**
429 * @}
430 */
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