| 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup isa
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| 30 | * @{
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| 31 | */
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| 32 |
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| 33 | /** @file
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| 34 | * @brief DMA controller management
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| 35 | */
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| 36 |
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| 37 | #include <assert.h>
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| 38 | #include <stdbool.h>
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| 39 | #include <errno.h>
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| 40 | #include <ddi.h>
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| 41 | #include <ddf/log.h>
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| 42 | #include <fibril_synch.h>
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| 43 | #include <ddi.h>
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| 44 | #include <ddf/log.h>
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| 45 | #include "i8237.h"
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| 46 |
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| 47 | /** DMA Slave controller I/O Address. */
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| 48 | #define DMA_CONTROLLER_FIRST_BASE ((void *) 0x00)
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| 49 |
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| 50 | /** DMA Master controller I/O Address. */
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| 51 | #define DMA_CONTROLLER_SECOND_BASE ((void *) 0xc0)
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| 52 |
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| 53 | /** Shared DMA page address register I/O address. */
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| 54 | #define DMA_CONTROLLER_PAGE_BASE ((void *) 0x81)
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| 55 |
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| 56 | #define DMA_STATUS_REQ(x) (1 << (((x) % 4) + 4))
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| 57 | #define DMA_STATUS_COMPLETE(x) (1 << ((x) % 4))
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| 58 |
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| 59 | /** http://wiki.osdev.org/DMA: The only bit that works is COND (bit 2) */
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| 60 | #define DMA_COMMAND_COND (1 << 2) /**< Disables DMA controller */
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| 61 |
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| 62 | #define DMA_SINGLE_MASK_CHAN_SEL_MASK 0x03
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| 63 | #define DMA_SINGLE_MASK_CHAN_SEL_SHIFT 0
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| 64 |
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| 65 | #define DMA_SINGLE_MASK_CHAN_TO_REG(x) \
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| 66 | (((x) & DMA_SINGLE_MASK_CHAN_SEL_MASK) << DMA_SINGLE_MASK_CHAN_SEL_SHIFT)
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| 67 |
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| 68 | #define DMA_SINGLE_MASK_MASKED_FLAG (1 << 2)
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| 69 |
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| 70 | #define DMA_MODE_CHAN_SELECT_MASK 0x03
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| 71 | #define DMA_MODE_CHAN_SELECT_SHIFT 0
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| 72 |
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| 73 | #define DMA_MODE_CHAN_TO_REG(x) \
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| 74 | (((x) & DMA_MODE_CHAN_SELECT_MASK) << DMA_MODE_CHAN_SELECT_SHIFT)
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| 75 |
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| 76 | #define DMA_MODE_CHAN_TRA_MASK 0x03
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| 77 | #define DMA_MODE_CHAN_TRA_SHIFT 2
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| 78 | #define DMA_MODE_CHAN_TRA_SELF_TEST 0
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| 79 | #define DMA_MODE_CHAN_TRA_WRITE 0x01
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| 80 | #define DMA_MODE_CHAN_TRA_READ 0x02
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| 81 |
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| 82 | #define DMA_MODE_CHAN_AUTO_FLAG (1 << 4)
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| 83 | #define DMA_MODE_CHAN_DOWN_FLAG (1 << 5)
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| 84 |
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| 85 | #define DMA_MODE_CHAN_MODE_MASK 0x03
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| 86 | #define DMA_MODE_CHAN_MODE_SHIFT 6
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| 87 | #define DMA_MODE_CHAN_MODE_DEMAND 0
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| 88 | #define DMA_MODE_CHAN_MODE_SINGLE 1
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| 89 | #define DMA_MODE_CHAN_MODE_BLOCK 2
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| 90 | #define DMA_MODE_CHAN_MODE_CASCADE 3
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| 91 |
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| 92 | #define DMA_MULTI_MASK_CHAN(x) (1 << ((x) % 4))
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| 93 |
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| 94 | typedef struct {
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| 95 | uint8_t channel_start0;
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| 96 | uint8_t channel_count0;
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| 97 | uint8_t channel_start1;
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| 98 | uint8_t channel_count1;
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| 99 | uint8_t channel_start2;
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| 100 | uint8_t channel_count2;
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| 101 | uint8_t channel_start3;
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| 102 | uint8_t channel_count3;
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| 103 |
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| 104 | uint8_t command_status;
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| 105 |
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| 106 | /** Memory to memory transfers, NOT implemented on PCs */
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| 107 | uint8_t request;
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| 108 | uint8_t single_mask;
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| 109 | uint8_t mode;
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| 110 | uint8_t flip_flop;
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| 111 |
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| 112 | /*
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| 113 | * Master reset sets Flip-Flop low, clears status,
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| 114 | * sets all mask bits on.
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| 115 | *
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| 116 | * Intermediate is not implemented on PCs.
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| 117 | *
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| 118 | */
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| 119 | uint8_t master_reset;
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| 120 | uint8_t mask_reset;
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| 121 | uint8_t multi_mask;
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| 122 | } dma_controller_regs_first_t;
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| 123 |
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| 124 | typedef struct {
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| 125 | uint8_t channel_start4;
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| 126 | uint8_t reserved0;
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| 127 | uint8_t channel_count4;
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| 128 | uint8_t reserved1;
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| 129 | uint8_t channel_start5;
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| 130 | uint8_t reserved2;
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| 131 | uint8_t channel_count5;
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| 132 | uint8_t reserved3;
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| 133 | uint8_t channel_start6;
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| 134 | uint8_t reserved4;
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| 135 | uint8_t channel_count6;
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| 136 | uint8_t reserved5;
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| 137 | uint8_t channel_start7;
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| 138 | uint8_t reserved6;
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| 139 | uint8_t channel_count7;
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| 140 |
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| 141 | uint8_t command_status;
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| 142 | uint8_t reserved8;
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| 143 | uint8_t request;
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| 144 | uint8_t reserved9;
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| 145 | uint8_t single_mask;
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| 146 | uint8_t reserveda;
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| 147 | uint8_t mode;
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| 148 | uint8_t reservedb;
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| 149 | uint8_t flip_flop;
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| 150 | uint8_t reservedc;
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| 151 | uint8_t master_reset;
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| 152 | uint8_t reservedd;
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| 153 | uint8_t multi_mask;
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| 154 | } dma_controller_regs_second_t;
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| 155 |
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| 156 | typedef struct {
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| 157 | uint8_t channel2;
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| 158 | uint8_t channel3;
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| 159 | uint8_t channel1;
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| 160 | uint8_t reserved0;
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| 161 | uint8_t reserved1;
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| 162 | uint8_t reserved2;
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| 163 | uint8_t channel0;
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| 164 | uint8_t reserved3;
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| 165 | uint8_t channel6;
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| 166 | uint8_t channel7;
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| 167 | uint8_t channel5;
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| 168 | uint8_t reserved4;
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| 169 | uint8_t reserved5;
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| 170 | uint8_t reserved6;
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| 171 | uint8_t channel4;
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| 172 | } dma_page_regs_t;
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| 173 |
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| 174 | /** Addresses needed to setup a DMA channel. */
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| 175 | typedef struct {
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| 176 | ioport8_t *offset_reg_address;
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| 177 | ioport8_t *size_reg_address;
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| 178 | ioport8_t *page_reg_address;
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| 179 | ioport8_t *single_mask_address;
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| 180 | ioport8_t *mode_address;
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| 181 | ioport8_t *flip_flop_address;
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| 182 | } dma_channel_t;
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| 183 |
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| 184 | typedef struct {
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| 185 | dma_channel_t channels[8];
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| 186 | dma_page_regs_t *page_table;
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| 187 | dma_controller_regs_first_t *first;
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| 188 | dma_controller_regs_second_t *second;
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| 189 | bool initialized;
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| 190 | } dma_controller_t;
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| 191 |
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| 192 | static fibril_mutex_t guard = FIBRIL_MUTEX_INITIALIZER(guard);
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| 193 |
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| 194 | /** Standard i8237 DMA controller.
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| 195 | *
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| 196 | * http://zet.aluzina.org/index.php/8237_DMA_controller#DMA_Channel_Registers
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| 197 | *
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| 198 | */
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| 199 | static dma_controller_t controller_8237 = {
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| 200 | .channels = {
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| 201 | /* The first chip 8-bit */
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| 202 | { /* Channel 0 - Unusable*/
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| 203 | .offset_reg_address = (uint8_t *) 0x00,
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| 204 | .size_reg_address = (uint8_t *) 0x01,
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| 205 | .page_reg_address = (uint8_t *) 0x87,
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| 206 | .single_mask_address = (uint8_t *) 0x0a,
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| 207 | .mode_address = (uint8_t *) 0x0b,
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| 208 | .flip_flop_address = (uint8_t *) 0x0c,
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| 209 | },
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| 210 | { /* Channel 1 */
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| 211 | .offset_reg_address = (uint8_t *) 0x02,
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| 212 | .size_reg_address = (uint8_t *) 0x03,
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| 213 | .page_reg_address = (uint8_t *) 0x83,
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| 214 | .single_mask_address = (uint8_t *) 0x0a,
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| 215 | .mode_address = (uint8_t *) 0x0b,
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| 216 | .flip_flop_address = (uint8_t *) 0x0c,
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| 217 | },
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| 218 | { /* Channel 2 */
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| 219 | .offset_reg_address = (uint8_t *) 0x04,
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| 220 | .size_reg_address = (uint8_t *) 0x05,
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| 221 | .page_reg_address = (uint8_t *) 0x81,
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| 222 | .single_mask_address = (uint8_t *) 0x0a,
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| 223 | .mode_address = (uint8_t *) 0x0b,
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| 224 | .flip_flop_address = (uint8_t *) 0x0c,
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| 225 | },
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| 226 | { /* Channel 3 */
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| 227 | .offset_reg_address = (uint8_t *) 0x06,
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| 228 | .size_reg_address = (uint8_t *) 0x07,
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| 229 | .page_reg_address = (uint8_t *) 0x82,
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| 230 | .single_mask_address = (uint8_t *) 0x0a,
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| 231 | .mode_address = (uint8_t *) 0x0b,
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| 232 | .flip_flop_address = (uint8_t *) 0x0c,
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| 233 | },
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| 234 |
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| 235 | /* The second chip 16-bit */
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| 236 | { /* Channel 4 - Unusable */
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| 237 | .offset_reg_address = (uint8_t *) 0xc0,
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| 238 | .size_reg_address = (uint8_t *) 0xc2,
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| 239 | .page_reg_address = (uint8_t *) 0x8f,
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| 240 | .single_mask_address = (uint8_t *) 0xd4,
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| 241 | .mode_address = (uint8_t *) 0xd6,
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| 242 | .flip_flop_address = (uint8_t *) 0xd8,
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| 243 | },
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| 244 | { /* Channel 5 */
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| 245 | .offset_reg_address = (uint8_t *) 0xc4,
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| 246 | .size_reg_address = (uint8_t *) 0xc6,
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| 247 | .page_reg_address = (uint8_t *) 0x8b,
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| 248 | .single_mask_address = (uint8_t *) 0xd4,
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| 249 | .mode_address = (uint8_t *) 0xd6,
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| 250 | .flip_flop_address = (uint8_t *) 0xd8,
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| 251 | },
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| 252 | { /* Channel 6 */
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| 253 | .offset_reg_address = (uint8_t *) 0xc8,
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| 254 | .size_reg_address = (uint8_t *) 0xca,
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| 255 | .page_reg_address = (uint8_t *) 0x89,
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| 256 | .single_mask_address = (uint8_t *) 0xd4,
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| 257 | .mode_address = (uint8_t *) 0xd6,
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| 258 | .flip_flop_address = (uint8_t *) 0xd8,
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| 259 | },
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| 260 | { /* Channel 7 */
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| 261 | .offset_reg_address = (uint8_t *) 0xcc,
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| 262 | .size_reg_address = (uint8_t *) 0xce,
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| 263 | .page_reg_address = (uint8_t *) 0x8a,
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| 264 | .single_mask_address = (uint8_t *) 0xd4,
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| 265 | .mode_address = (uint8_t *) 0xd6,
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| 266 | .flip_flop_address = (uint8_t *) 0xd8,
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| 267 | },
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| 268 | },
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| 269 |
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| 270 | .page_table = NULL,
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| 271 | .first = NULL,
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| 272 | .second = NULL,
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| 273 | .initialized = false,
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| 274 | };
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| 275 |
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| 276 | /** Initialize I/O access to DMA controller I/O ports.
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| 277 | *
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| 278 | * @param controller DMA Controller structure to initialize.
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| 279 | *
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| 280 | * @return Error code.
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| 281 | */
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| 282 | static inline int dma_controller_init(dma_controller_t *controller)
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| 283 | {
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| 284 | assert(controller);
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| 285 | int ret = pio_enable(DMA_CONTROLLER_PAGE_BASE, sizeof(dma_page_regs_t),
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| 286 | (void **) &controller->page_table);
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| 287 | if (ret != EOK)
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| 288 | return EIO;
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| 289 |
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| 290 | ret = pio_enable(DMA_CONTROLLER_FIRST_BASE,
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| 291 | sizeof(dma_controller_regs_first_t), (void **) &controller->first);
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| 292 | if (ret != EOK)
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| 293 | return EIO;
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| 294 |
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| 295 | ret = pio_enable(DMA_CONTROLLER_SECOND_BASE,
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| 296 | sizeof(dma_controller_regs_second_t), (void **) &controller->second);
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| 297 | if (ret != EOK)
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| 298 | return EIO;
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| 299 |
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| 300 | controller->initialized = true;
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| 301 |
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| 302 | /* Reset the controller */
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| 303 | pio_write_8(&controller->second->master_reset, 0xff);
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| 304 | pio_write_8(&controller->first->master_reset, 0xff);
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| 305 |
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| 306 | return EOK;
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| 307 | }
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| 308 |
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| 309 | /** Helper function. Channels 4,5,6, and 7 are 8 bit DMA.
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| 310 | * @pram channel DMA channel.
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| 311 | * @reutrn True, if channel is 4,5,6, or 7, false otherwise.
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| 312 | */
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| 313 | static inline bool is_dma16(unsigned channel)
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| 314 | {
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| 315 | return (channel >= 4) && (channel < 8);
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| 316 | }
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| 317 |
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| 318 | /** Helper function. Channels 0,1,2, and 3 are 8 bit DMA.
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| 319 | * @pram channel DMA channel.
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| 320 | * @reutrn True, if channel is 0,1,2, or 3, false otherwise.
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| 321 | */
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| 322 | static inline bool is_dma8(unsigned channel)
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| 323 | {
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| 324 | return (channel < 4);
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| 325 | }
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| 326 |
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| 327 | /** Setup DMA channel to specified place and mode.
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| 328 | *
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| 329 | * @param channel DMA Channel 1, 2, 3 for 8 bit transfers,
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| 330 | * 5, 6, 7 for 16 bit.
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| 331 | * @param pa Physical address of the buffer. Must be < 16 MB
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| 332 | * for 16 bit and < 1 MB for 8 bit transfers.
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| 333 | * @param size DMA buffer size, limited to 64 KB.
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| 334 | * @param mode Mode of the DMA channel:
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| 335 | * - Read or Write
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| 336 | * - Allow automatic reset
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| 337 | * - Use address decrement instead of increment
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| 338 | * - Use SINGLE/BLOCK/ON DEMAND transfer mode
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| 339 | *
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| 340 | * @return Error code.
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| 341 | */
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| 342 | int dma_channel_setup(unsigned int channel, uint32_t pa, uint32_t size,
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| 343 | uint8_t mode)
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| 344 | {
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| 345 | if (!is_dma8(channel) && !is_dma16(channel))
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| 346 | return ENOENT;
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| 347 |
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| 348 | if ((channel == 0) || (channel == 4))
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| 349 | return ENOTSUP;
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| 350 |
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| 351 | /* DMA is limited to 24bit addresses. */
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| 352 | if (pa >= (1 << 24))
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| 353 | return EINVAL;
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| 354 |
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| 355 | /* 8 bit channels use only 4 bits from the page register. */
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| 356 | if (is_dma8(channel) && (pa >= (1 << 20)))
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| 357 | return EINVAL;
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| 358 |
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| 359 | /* Buffers cannot cross 64K page boundaries */
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| 360 | if ((pa & 0xffff0000) != ((pa + size - 1) & 0xffff0000))
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| 361 | return EINVAL;
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| 362 |
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| 363 | fibril_mutex_lock(&guard);
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| 364 |
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| 365 | if (!controller_8237.initialized)
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| 366 | dma_controller_init(&controller_8237);
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| 367 |
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| 368 | if (!controller_8237.initialized) {
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| 369 | fibril_mutex_unlock(&guard);
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| 370 | return EIO;
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| 371 | }
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| 372 |
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| 373 | /* 16 bit transfers are a bit special */
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| 374 | ddf_msg(LVL_DEBUG, "Unspoiled address %#" PRIx32 " (size %" PRIu16 ")",
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| 375 | pa, size);
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| 376 | if (is_dma16(channel)) {
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| 377 | /* Size must be aligned to 16 bits */
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| 378 | if ((size & 1) != 0) {
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| 379 | fibril_mutex_unlock(&guard);
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| 380 | return EINVAL;
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| 381 | }
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| 382 | /* Size is in 2byte words */
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| 383 | size >>= 1;
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| 384 | /* Address is fun: lower 16 bits need to be shifted by 1 */
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| 385 | pa = ((pa & 0xffff) >> 1) | (pa & 0xff0000);
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| 386 | }
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| 387 |
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| 388 | const dma_channel_t dma_channel = controller_8237.channels[channel];
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| 389 |
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| 390 | ddf_msg(LVL_DEBUG, "Setting channel %u to address %#" PRIx32 " "
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| 391 | "(size %" PRIu16 "), mode %hhx.", channel, pa, size, mode);
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| 392 |
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| 393 | /* Mask DMA request */
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| 394 | uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel) |
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| 395 | DMA_SINGLE_MASK_MASKED_FLAG;
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| 396 | pio_write_8(dma_channel.single_mask_address, value);
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| 397 |
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| 398 | /* Set mode */
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| 399 | value = DMA_MODE_CHAN_TO_REG(channel) | mode;
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| 400 | ddf_msg(LVL_DEBUG2, "Writing mode byte: %p:%hhx.",
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| 401 | dma_channel.mode_address, value);
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| 402 | pio_write_8(dma_channel.mode_address, value);
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| 403 |
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| 404 | /* Set address - reset flip-flop */
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| 405 | pio_write_8(dma_channel.flip_flop_address, 0);
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| 406 |
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| 407 | /* Low byte */
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| 408 | value = pa & 0xff;
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| 409 | ddf_msg(LVL_DEBUG2, "Writing address low byte: %p:%hhx.",
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| 410 | dma_channel.offset_reg_address, value);
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| 411 | pio_write_8(dma_channel.offset_reg_address, value);
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| 412 |
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| 413 | /* High byte */
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| 414 | value = (pa >> 8) & 0xff;
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| 415 | ddf_msg(LVL_DEBUG2, "Writing address high byte: %p:%hhx.",
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| 416 | dma_channel.offset_reg_address, value);
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| 417 | pio_write_8(dma_channel.offset_reg_address, value);
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| 418 |
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| 419 | /* Page address - third byte */
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| 420 | value = (pa >> 16) & 0xff;
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| 421 | ddf_msg(LVL_DEBUG2, "Writing address page byte: %p:%hhx.",
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| 422 | dma_channel.page_reg_address, value);
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| 423 | pio_write_8(dma_channel.page_reg_address, value);
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| 424 |
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| 425 | /* Set size - reset flip-flop */
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| 426 | pio_write_8(dma_channel.flip_flop_address, 0);
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|---|
| 427 |
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|---|
| 428 | /* Low byte */
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|---|
| 429 | value = (size - 1) & 0xff;
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|---|
| 430 | ddf_msg(LVL_DEBUG2, "Writing size low byte: %p:%hhx.",
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|---|
| 431 | dma_channel.size_reg_address, value);
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|---|
| 432 | pio_write_8(dma_channel.size_reg_address, value);
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|---|
| 433 |
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|---|
| 434 | /* High byte */
|
|---|
| 435 | value = ((size - 1) >> 8) & 0xff;
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|---|
| 436 | ddf_msg(LVL_DEBUG2, "Writing size high byte: %p:%hhx.",
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|---|
| 437 | dma_channel.size_reg_address, value);
|
|---|
| 438 | pio_write_8(dma_channel.size_reg_address, value);
|
|---|
| 439 |
|
|---|
| 440 | /* Unmask DMA request */
|
|---|
| 441 | value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
|
|---|
| 442 | pio_write_8(dma_channel.single_mask_address, value);
|
|---|
| 443 |
|
|---|
| 444 | fibril_mutex_unlock(&guard);
|
|---|
| 445 |
|
|---|
| 446 | return EOK;
|
|---|
| 447 | }
|
|---|
| 448 |
|
|---|
| 449 | /** Query remaining buffer size.
|
|---|
| 450 | *
|
|---|
| 451 | * @param channel DMA Channel 1, 2, 3 for 8 bit transfers,
|
|---|
| 452 | * 5, 6, 7 for 16 bit.
|
|---|
| 453 | * @param size Place to store number of bytes pending in the assigned buffer.
|
|---|
| 454 | *
|
|---|
| 455 | * @return Error code.
|
|---|
| 456 | */
|
|---|
| 457 | int dma_channel_remain(unsigned channel, size_t *size)
|
|---|
| 458 | {
|
|---|
| 459 | assert(size);
|
|---|
| 460 | if (!is_dma8(channel) && !is_dma16(channel))
|
|---|
| 461 | return ENOENT;
|
|---|
| 462 |
|
|---|
| 463 | if ((channel == 0) || (channel == 4))
|
|---|
| 464 | return ENOTSUP;
|
|---|
| 465 |
|
|---|
| 466 | fibril_mutex_lock(&guard);
|
|---|
| 467 | if (!controller_8237.initialized) {
|
|---|
| 468 | fibril_mutex_unlock(&guard);
|
|---|
| 469 | return EIO;
|
|---|
| 470 | }
|
|---|
| 471 |
|
|---|
| 472 | const dma_channel_t dma_channel = controller_8237.channels[channel];
|
|---|
| 473 | /* Get size - reset flip-flop */
|
|---|
| 474 | pio_write_8(dma_channel.flip_flop_address, 0);
|
|---|
| 475 |
|
|---|
| 476 | /* Low byte */
|
|---|
| 477 | const uint8_t value_low = pio_read_8(dma_channel.size_reg_address);
|
|---|
| 478 | ddf_msg(LVL_DEBUG2, "Read size low byte: %p:%x.",
|
|---|
| 479 | dma_channel.size_reg_address, value_low);
|
|---|
| 480 |
|
|---|
| 481 | /* High byte */
|
|---|
| 482 | const uint8_t value_high = pio_read_8(dma_channel.size_reg_address);
|
|---|
| 483 | ddf_msg(LVL_DEBUG2, "Read size high byte: %p:%x.",
|
|---|
| 484 | dma_channel.size_reg_address, value_high);
|
|---|
| 485 | fibril_mutex_unlock(&guard);
|
|---|
| 486 |
|
|---|
| 487 | uint16_t remain = (value_high << 8 | value_low) ;
|
|---|
| 488 | /* 16 bit DMA size is in words,
|
|---|
| 489 | * the upper bits are bogus for 16bit transfers so we need to get
|
|---|
| 490 | * rid of them. Using limited type works well.*/
|
|---|
| 491 | if (is_dma16(channel))
|
|---|
| 492 | remain <<= 1;
|
|---|
| 493 | *size = is_dma16(channel) ? remain + 2: remain + 1;
|
|---|
| 494 | return EOK;
|
|---|
| 495 | }
|
|---|
| 496 | /**
|
|---|
| 497 | * @}
|
|---|
| 498 | */
|
|---|
