| 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup isa
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| 30 | * @{
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| 31 | */
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| 32 |
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| 33 | /** @file
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| 34 | * @brief DMA controller management
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| 35 | */
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| 36 |
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| 37 | #include <assert.h>
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| 38 | #include <stdbool.h>
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| 39 | #include <errno.h>
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| 40 | #include <fibril_synch.h>
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| 41 | #include <ddi.h>
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| 42 | #include <ddf/log.h>
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| 43 | #include "i8237.h"
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| 44 |
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| 45 | /** DMA Slave controller I/O Address. */
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| 46 | #define DMA_CONTROLLER_FIRST_BASE ((void *) 0x00)
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| 47 |
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| 48 | /** DMA Master controller I/O Address. */
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| 49 | #define DMA_CONTROLLER_SECOND_BASE ((void *) 0xc0)
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| 50 |
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| 51 | /** Shared DMA page address register I/O address. */
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| 52 | #define DMA_CONTROLLER_PAGE_BASE ((void *) 0x81)
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| 53 |
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| 54 | #define DMA_STATUS_REQ(x) (1 << (((x) % 4) + 4))
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| 55 | #define DMA_STATUS_COMPLETE(x) (1 << ((x) % 4))
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| 56 |
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| 57 | /** http://wiki.osdev.org/DMA: The only bit that works is COND (bit 2) */
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| 58 | #define DMA_COMMAND_COND (1 << 2) /**< Disables DMA controller */
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| 59 |
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| 60 | #define DMA_SINGLE_MASK_CHAN_SEL_MASK 0x03
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| 61 | #define DMA_SINGLE_MASK_CHAN_SEL_SHIFT 0
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| 62 |
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| 63 | #define DMA_SINGLE_MASK_CHAN_TO_REG(x) \
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| 64 | (((x) & DMA_SINGLE_MASK_CHAN_SEL_MASK) << DMA_SINGLE_MASK_CHAN_SEL_SHIFT)
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| 65 |
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| 66 | #define DMA_SINGLE_MASK_MASKED_FLAG (1 << 2)
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| 67 |
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| 68 | #define DMA_MODE_CHAN_SELECT_MASK 0x03
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| 69 | #define DMA_MODE_CHAN_SELECT_SHIFT 0
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| 70 |
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| 71 | #define DMA_MODE_CHAN_TO_REG(x) \
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| 72 | (((x) & DMA_MODE_CHAN_SELECT_MASK) << DMA_MODE_CHAN_SELECT_SHIFT)
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| 73 |
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| 74 | #define DMA_MODE_CHAN_TRA_MASK 0x03
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| 75 | #define DMA_MODE_CHAN_TRA_SHIFT 2
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| 76 | #define DMA_MODE_CHAN_TRA_SELF_TEST 0
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| 77 | #define DMA_MODE_CHAN_TRA_WRITE 0x01
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| 78 | #define DMA_MODE_CHAN_TRA_READ 0x02
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| 79 |
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| 80 | #define DMA_MODE_CHAN_AUTO_FLAG (1 << 4)
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| 81 | #define DMA_MODE_CHAN_DOWN_FLAG (1 << 5)
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| 82 |
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| 83 | #define DMA_MODE_CHAN_MODE_MASK 0x03
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| 84 | #define DMA_MODE_CHAN_MODE_SHIFT 6
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| 85 | #define DMA_MODE_CHAN_MODE_DEMAND 0
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| 86 | #define DMA_MODE_CHAN_MODE_SINGLE 1
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| 87 | #define DMA_MODE_CHAN_MODE_BLOCK 2
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| 88 | #define DMA_MODE_CHAN_MODE_CASCADE 3
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| 89 |
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| 90 | #define DMA_MULTI_MASK_CHAN(x) (1 << ((x) % 4))
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| 91 |
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| 92 | typedef struct {
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| 93 | uint8_t channel_start0;
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| 94 | uint8_t channel_count0;
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| 95 | uint8_t channel_start1;
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| 96 | uint8_t channel_count1;
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| 97 | uint8_t channel_start2;
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| 98 | uint8_t channel_count2;
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| 99 | uint8_t channel_start3;
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| 100 | uint8_t channel_count3;
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| 101 |
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| 102 | uint8_t command_status;
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| 103 |
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| 104 | /** Memory to memory transfers, NOT implemented on PCs */
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| 105 | uint8_t request;
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| 106 | uint8_t single_mask;
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| 107 | uint8_t mode;
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| 108 | uint8_t flip_flop;
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| 109 |
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| 110 | /*
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| 111 | * Master reset sets Flip-Flop low, clears status,
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| 112 | * sets all mask bits on.
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| 113 | *
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| 114 | * Intermediate is not implemented on PCs.
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| 115 | *
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| 116 | */
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| 117 | uint8_t master_reset;
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| 118 | uint8_t mask_reset;
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| 119 | uint8_t multi_mask;
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| 120 | } dma_controller_regs_first_t;
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| 121 |
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| 122 | typedef struct {
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| 123 | uint8_t channel_start4;
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| 124 | uint8_t reserved0;
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| 125 | uint8_t channel_count4;
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| 126 | uint8_t reserved1;
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| 127 | uint8_t channel_start5;
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| 128 | uint8_t reserved2;
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| 129 | uint8_t channel_count5;
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| 130 | uint8_t reserved3;
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| 131 | uint8_t channel_start6;
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| 132 | uint8_t reserved4;
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| 133 | uint8_t channel_count6;
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| 134 | uint8_t reserved5;
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| 135 | uint8_t channel_start7;
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| 136 | uint8_t reserved6;
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| 137 | uint8_t channel_count7;
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| 138 |
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| 139 | uint8_t command_status;
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| 140 | uint8_t reserved8;
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| 141 | uint8_t request;
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| 142 | uint8_t reserved9;
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| 143 | uint8_t single_mask;
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| 144 | uint8_t reserveda;
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| 145 | uint8_t mode;
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| 146 | uint8_t reservedb;
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| 147 | uint8_t flip_flop;
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| 148 | uint8_t reservedc;
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| 149 | uint8_t master_reset;
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| 150 | uint8_t reservedd;
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| 151 | uint8_t multi_mask;
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| 152 | } dma_controller_regs_second_t;
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| 153 |
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| 154 | typedef struct {
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| 155 | uint8_t channel2;
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| 156 | uint8_t channel3;
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| 157 | uint8_t channel1;
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| 158 | uint8_t reserved0;
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| 159 | uint8_t reserved1;
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| 160 | uint8_t reserved2;
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| 161 | uint8_t channel0;
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| 162 | uint8_t reserved3;
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| 163 | uint8_t channel6;
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| 164 | uint8_t channel7;
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| 165 | uint8_t channel5;
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| 166 | uint8_t reserved4;
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| 167 | uint8_t reserved5;
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| 168 | uint8_t reserved6;
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| 169 | uint8_t channel4;
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| 170 | } dma_page_regs_t;
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| 171 |
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| 172 | /** Addresses needed to setup a DMA channel. */
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| 173 | typedef struct {
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| 174 | ioport8_t *offset_reg_address;
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| 175 | ioport8_t *size_reg_address;
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| 176 | ioport8_t *page_reg_address;
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| 177 | ioport8_t *single_mask_address;
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| 178 | ioport8_t *mode_address;
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| 179 | ioport8_t *flip_flop_address;
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| 180 | } dma_channel_t;
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| 181 |
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| 182 | typedef struct {
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| 183 | dma_channel_t channels[8];
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| 184 | dma_page_regs_t *page_table;
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| 185 | dma_controller_regs_first_t *first;
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| 186 | dma_controller_regs_second_t *second;
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| 187 | bool initialized;
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| 188 | } dma_controller_t;
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| 189 |
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| 190 | static fibril_mutex_t guard = FIBRIL_MUTEX_INITIALIZER(guard);
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| 191 |
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| 192 | /** Standard i8237 DMA controller.
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| 193 | *
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| 194 | * http://zet.aluzina.org/index.php/8237_DMA_controller#DMA_Channel_Registers
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| 195 | *
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| 196 | */
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| 197 | static dma_controller_t controller_8237 = {
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| 198 | .channels = {
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| 199 | /* The first chip 8-bit */
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| 200 | {
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| 201 | (uint8_t *) 0x00,
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| 202 | (uint8_t *) 0x01,
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| 203 | (uint8_t *) 0x87,
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| 204 | (uint8_t *) 0x0a,
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| 205 | (uint8_t *) 0x0b,
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| 206 | (uint8_t *) 0x0c,
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| 207 | },
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| 208 | {
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| 209 | (uint8_t *) 0x02,
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| 210 | (uint8_t *) 0x03,
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| 211 | (uint8_t *) 0x83,
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| 212 | (uint8_t *) 0x0a,
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| 213 | (uint8_t *) 0x0b,
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| 214 | (uint8_t *) 0x0c,
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| 215 | },
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| 216 | {
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| 217 | (uint8_t *) 0x04,
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| 218 | (uint8_t *) 0x05,
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| 219 | (uint8_t *) 0x81,
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| 220 | (uint8_t *) 0x0a,
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| 221 | (uint8_t *) 0x0b,
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| 222 | (uint8_t *) 0x0c,
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| 223 | },
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| 224 | {
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| 225 | (uint8_t *) 0x06,
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| 226 | (uint8_t *) 0x07,
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| 227 | (uint8_t *) 0x82,
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| 228 | (uint8_t *) 0x0a,
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| 229 | (uint8_t *) 0x0b,
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| 230 | (uint8_t *) 0x0c,
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| 231 | },
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| 232 |
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| 233 | /* The second chip 16-bit */
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| 234 | {
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| 235 | (uint8_t *) 0xc0,
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| 236 | (uint8_t *) 0xc2,
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| 237 | (uint8_t *) 0x8f,
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| 238 | (uint8_t *) 0xd4,
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| 239 | (uint8_t *) 0xd6,
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| 240 | (uint8_t *) 0xd8,
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| 241 | },
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| 242 | {
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| 243 | (uint8_t *) 0xc4,
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| 244 | (uint8_t *) 0xc6,
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| 245 | (uint8_t *) 0x8b,
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| 246 | (uint8_t *) 0xd4,
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| 247 | (uint8_t *) 0xd6,
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| 248 | (uint8_t *) 0xd8,
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| 249 | },
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| 250 | {
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| 251 | (uint8_t *) 0xc8,
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| 252 | (uint8_t *) 0xca,
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| 253 | (uint8_t *) 0x89,
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| 254 | (uint8_t *) 0xd4,
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| 255 | (uint8_t *) 0xd6,
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| 256 | (uint8_t *) 0xd8,
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| 257 | },
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| 258 | {
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| 259 | (uint8_t *) 0xcc,
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| 260 | (uint8_t *) 0xce,
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| 261 | (uint8_t *) 0x8a,
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| 262 | (uint8_t *) 0xd4,
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| 263 | (uint8_t *) 0xd6,
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| 264 | (uint8_t *) 0xd8,
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| 265 | },
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| 266 | },
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| 267 |
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| 268 | .page_table = NULL,
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| 269 | .first = NULL,
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| 270 | .second = NULL,
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| 271 | .initialized = false,
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| 272 | };
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| 273 |
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| 274 | /* Initialize I/O access to DMA controller I/O ports.
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| 275 | *
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| 276 | * @param controller DMA Controller structure to initialize.
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| 277 | *
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| 278 | * @return Error code.
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| 279 | *
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| 280 | */
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| 281 | static inline int dma_controller_init(dma_controller_t *controller)
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| 282 | {
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| 283 | assert(controller);
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| 284 | int ret = pio_enable(DMA_CONTROLLER_PAGE_BASE, sizeof(dma_page_regs_t),
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| 285 | (void **) &controller->page_table);
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| 286 | if (ret != EOK)
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| 287 | return EIO;
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| 288 |
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| 289 | ret = pio_enable(DMA_CONTROLLER_FIRST_BASE,
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| 290 | sizeof(dma_controller_regs_first_t), (void **) &controller->first);
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| 291 | if (ret != EOK)
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| 292 | return EIO;
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| 293 |
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| 294 | ret = pio_enable(DMA_CONTROLLER_SECOND_BASE,
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| 295 | sizeof(dma_controller_regs_second_t), (void **) &controller->second);
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| 296 | if (ret != EOK)
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| 297 | return EIO;
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| 298 |
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| 299 | controller->initialized = true;
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| 300 |
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| 301 | /* Reset the controller */
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| 302 | pio_write_8(&controller->second->master_reset, 0xff);
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| 303 | pio_write_8(&controller->first->master_reset, 0xff);
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| 304 |
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| 305 | return EOK;
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| 306 | }
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| 307 |
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| 308 | /** Setup DMA channel to specified place and mode.
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| 309 | *
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| 310 | * @param channel DMA Channel 1, 2, 3 for 8 bit transfers,
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| 311 | * 5, 6, 7 for 16 bit.
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| 312 | * @param pa Physical address of the buffer. Must be < 16 MB
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| 313 | * for 16 bit and < 1 MB for 8 bit transfers.
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| 314 | * @param size DMA buffer size, limited to 64 KB.
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| 315 | * @param mode Mode of the DMA channel:
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| 316 | * - Read or Write
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| 317 | * - Allow automatic reset
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| 318 | * - Use address decrement instead of increment
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| 319 | * - Use SINGLE/BLOCK/ON DEMAND transfer mode
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| 320 | *
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| 321 | * @return Error code.
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| 322 | *
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| 323 | */
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| 324 | int dma_setup_channel(unsigned int channel, uint32_t pa, uint16_t size,
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| 325 | uint8_t mode)
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| 326 | {
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| 327 | if ((channel == 0) || (channel == 4))
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| 328 | return ENOTSUP;
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| 329 |
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| 330 | if (channel > 7)
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| 331 | return ENOENT;
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| 332 |
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| 333 | /* DMA is limited to 24bit addresses. */
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| 334 | if (pa >= (1 << 24))
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| 335 | return EINVAL;
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| 336 |
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| 337 | /* 8 bit channels use only 4 bits from the page register. */
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| 338 | if ((channel > 0) && (channel < 4) && (pa >= (1 << 20)))
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| 339 | return EINVAL;
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| 340 |
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| 341 | fibril_mutex_lock(&guard);
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| 342 |
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| 343 | if (!controller_8237.initialized)
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| 344 | dma_controller_init(&controller_8237);
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| 345 |
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| 346 | if (!controller_8237.initialized) {
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| 347 | fibril_mutex_unlock(&guard);
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| 348 | return EIO;
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| 349 | }
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| 350 |
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| 351 | /* 16 bit transfers are a bit special */
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| 352 | ddf_msg(LVL_DEBUG, "Unspoiled address %#" PRIx32 " (size %" PRIu16 ")",
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| 353 | pa, size);
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| 354 | if (channel > 4) {
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| 355 | /* Size must be aligned to 16 bits */
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| 356 | if ((size & 1) != 0) {
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| 357 | fibril_mutex_unlock(&guard);
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| 358 | return EINVAL;
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| 359 | }
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| 360 |
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| 361 | size >>= 1;
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| 362 |
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| 363 | /* Address is fun: lower 16 bits need to be shifted by 1 */
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| 364 | pa = ((pa & 0xffff) >> 1) | (pa & 0xff0000);
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| 365 | }
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| 366 |
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| 367 | const dma_channel_t dma_channel = controller_8237.channels[channel];
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| 368 |
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| 369 | ddf_msg(LVL_DEBUG, "Setting channel %u to address %#" PRIx32 " "
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| 370 | "(size %" PRIu16 "), mode %hhx.", channel, pa, size, mode);
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| 371 |
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| 372 | /* Mask DMA request */
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| 373 | uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel) |
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| 374 | DMA_SINGLE_MASK_MASKED_FLAG;
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| 375 | pio_write_8(dma_channel.single_mask_address, value);
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| 376 |
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| 377 | /* Set mode */
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| 378 | value = DMA_MODE_CHAN_TO_REG(channel) | mode;
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| 379 | ddf_msg(LVL_DEBUG2, "Writing mode byte: %p:%hhx.",
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| 380 | dma_channel.mode_address, value);
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| 381 | pio_write_8(dma_channel.mode_address, value);
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| 382 |
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| 383 | /* Set address - reset flip-flop */
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| 384 | pio_write_8(dma_channel.flip_flop_address, 0);
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| 385 |
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| 386 | /* Low byte */
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| 387 | value = pa & 0xff;
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| 388 | ddf_msg(LVL_DEBUG2, "Writing address low byte: %p:%hhx.",
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| 389 | dma_channel.offset_reg_address, value);
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| 390 | pio_write_8(dma_channel.offset_reg_address, value);
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| 391 |
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| 392 | /* High byte */
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| 393 | value = (pa >> 8) & 0xff;
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| 394 | ddf_msg(LVL_DEBUG2, "Writing address high byte: %p:%hhx.",
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| 395 | dma_channel.offset_reg_address, value);
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| 396 | pio_write_8(dma_channel.offset_reg_address, value);
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| 397 |
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| 398 | /* Page address - third byte */
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| 399 | value = (pa >> 16) & 0xff;
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| 400 | ddf_msg(LVL_DEBUG2, "Writing address page byte: %p:%hhx.",
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| 401 | dma_channel.page_reg_address, value);
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| 402 | pio_write_8(dma_channel.page_reg_address, value);
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| 403 |
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| 404 | /* Set size - reset flip-flop */
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| 405 | pio_write_8(dma_channel.flip_flop_address, 0);
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| 406 |
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| 407 | /* Low byte */
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| 408 | value = (size - 1) & 0xff;
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| 409 | ddf_msg(LVL_DEBUG2, "Writing size low byte: %p:%hhx.",
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| 410 | dma_channel.size_reg_address, value);
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| 411 | pio_write_8(dma_channel.size_reg_address, value);
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| 412 |
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| 413 | /* High byte */
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|---|
| 414 | value = ((size - 1) >> 8) & 0xff;
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|---|
| 415 | ddf_msg(LVL_DEBUG2, "Writing size high byte: %p:%hhx.",
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|---|
| 416 | dma_channel.size_reg_address, value);
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|---|
| 417 | pio_write_8(dma_channel.size_reg_address, value);
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| 418 |
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|---|
| 419 | /* Unmask DMA request */
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|---|
| 420 | value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
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|---|
| 421 | pio_write_8(dma_channel.single_mask_address, value);
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|---|
| 422 |
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|---|
| 423 | fibril_mutex_unlock(&guard);
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|---|
| 424 |
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|---|
| 425 | return EOK;
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|---|
| 426 | }
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|---|
| 427 |
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|---|
| 428 | /**
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|---|
| 429 | * @}
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|---|
| 430 | */
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|---|
