| 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 | /** @addtogroup isa
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| 29 | * @{
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| 30 | */
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| 31 | /** @file
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| 32 | * @brief DMA controller management
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| 33 | */
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| 34 | #include <assert.h>
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| 35 | #include <bool.h>
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| 36 | #include <errno.h>
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| 37 | #include <fibril_synch.h>
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| 38 | #include <ddi.h> /* pio_enable */
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| 39 | #include <libarch/ddi.h> /* pio_write */
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| 40 | #include <ddf/log.h>
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| 41 |
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| 42 | #include "dma_controller.h"
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| 43 |
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| 44 | /** DMA Slave controller I/O Address. */
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| 45 | #define DMA_CONTROLLER_FIRST_BASE ((void*)0x0)
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| 46 | typedef struct dma_controller_regs_first {
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| 47 | uint8_t channel_start0;
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| 48 | uint8_t channel_count0;
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| 49 | uint8_t channel_start1;
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| 50 | uint8_t channel_count1;
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| 51 | uint8_t channel_start2;
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| 52 | uint8_t channel_count2;
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| 53 | uint8_t channel_start3;
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| 54 | uint8_t channel_count3;
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| 55 |
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| 56 | uint8_t command_status;
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| 57 | #define DMA_STATUS_REQ(x) (1 << ((x % 4) + 4))
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| 58 | #define DMA_STATUS_COMPLETE(x) (1 << (x % 4))
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| 59 | /* http://wiki.osdev.org/DMA: The only bit that works is COND(bit 2) */
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| 60 | #define DMA_COMMAND_COND (1 << 2) /* Disables DMA controller */
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| 61 |
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| 62 | uint8_t request; /* Memory to memory transfers, NOT implemented on PCs*/
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| 63 | uint8_t single_mask;
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| 64 | #define DMA_SINGLE_MASK_CHAN_SEL_MASK (0x3)
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| 65 | #define DMA_SINGLE_MASK_CHAN_SEL_SHIFT (0)
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| 66 | #define DMA_SINGLE_MASK_CHAN_TO_REG(x) \
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| 67 | ((x & DMA_SINGLE_MASK_CHAN_SEL_MASK) << DMA_SINGLE_MASK_CHAN_SEL_SHIFT)
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| 68 | #define DMA_SINGLE_MASK_MASKED_FLAG (1 << 2)
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| 69 |
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| 70 | uint8_t mode;
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| 71 | #define DMA_MODE_CHAN_SELECT_MASK (0x3)
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| 72 | #define DMA_MODE_CHAN_SELECT_SHIFT (0)
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| 73 | #define DMA_MODE_CHAN_TO_REG(x) \
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| 74 | ((x & DMA_MODE_CHAN_SELECT_MASK) << DMA_MODE_CHAN_SELECT_SHIFT)
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| 75 | #define DMA_MODE_CHAN_TRA_MASK (0x3)
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| 76 | #define DMA_MODE_CHAN_TRA_SHIFT (2)
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| 77 | #define DMA_MODE_CHAN_TRA_SELF_TEST (0)
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| 78 | #define DMA_MODE_CHAN_TRA_WRITE (0x1)
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| 79 | #define DMA_MODE_CHAN_TRA_READ (0x2)
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| 80 | #define DMA_MODE_CHAN_AUTO_FLAG (1 << 4)
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| 81 | #define DMA_MODE_CHAN_DOWN_FLAG (1 << 5)
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| 82 | #define DMA_MODE_CHAN_MODE_MASK (0x3)
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| 83 | #define DMA_MODE_CHAN_MODE_SHIFT (6)
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| 84 | #define DMA_MODE_CHAN_MODE_DEMAND (0)
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| 85 | #define DMA_MODE_CHAN_MODE_SINGLE (1)
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| 86 | #define DMA_MODE_CHAN_MODE_BLOCK (2)
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| 87 | #define DMA_MODE_CHAN_MODE_CASCADE (3)
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| 88 |
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| 89 | uint8_t flip_flop;
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| 90 | /* Master reset sets Flip-Flop low, clears status,
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| 91 | * sets all mask bits on */
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| 92 | uint8_t master_reset; /* Intermediate is not implemented on PCs */
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| 93 | uint8_t mask_reset;
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| 94 |
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| 95 | uint8_t multi_mask;
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| 96 | #define DMA_MULTI_MASK_CHAN(x) (1 << (x % 4))
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| 97 |
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| 98 | } dma_controller_regs_first_t;
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| 99 |
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| 100 | /** DMA Master controller I/O Address. */
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| 101 | #define DMA_CONTROLLER_SECOND_BASE ((void*)0xc0)
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| 102 | /* See dma_controller_regs_first_t for register values */
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| 103 | typedef struct dma_controller_regs_second {
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| 104 | uint8_t channel_start4;
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| 105 | uint8_t reserved0;
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| 106 | uint8_t channel_count4;
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| 107 | uint8_t reserved1;
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| 108 | uint8_t channel_start5;
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| 109 | uint8_t reserved2;
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| 110 | uint8_t channel_count5;
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| 111 | uint8_t reserved3;
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| 112 | uint8_t channel_start6;
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| 113 | uint8_t reserved4;
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| 114 | uint8_t channel_count6;
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| 115 | uint8_t reserved5;
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| 116 | uint8_t channel_start7;
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| 117 | uint8_t reserved6;
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| 118 | uint8_t channel_count7;
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| 119 |
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| 120 | uint8_t command_status;
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| 121 | uint8_t reserved8;
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| 122 | uint8_t request;
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| 123 | uint8_t reserved9;
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| 124 | uint8_t single_mask;
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| 125 | uint8_t reserveda;
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| 126 | uint8_t mode;
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| 127 | uint8_t reservedb;
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| 128 | uint8_t flip_flop;
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| 129 | uint8_t reservedc;
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| 130 | uint8_t master_reset;
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| 131 | uint8_t reservedd;
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| 132 | uint8_t multi_mask;
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| 133 | } dma_controller_regs_second_t;
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| 134 |
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| 135 | /** Shared DMA page address register I/O address. */
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| 136 | #define DMA_CONTROLLER_PAGE_BASE ((void*)0x81)
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| 137 | typedef struct dma_page_regs {
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| 138 | uint8_t channel2;
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| 139 | uint8_t channel3;
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| 140 | uint8_t channel1;
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| 141 | uint8_t reserved0;
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| 142 | uint8_t reserved1;
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| 143 | uint8_t reserved2;
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| 144 | uint8_t channel0;
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| 145 | uint8_t reserved3;
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| 146 | uint8_t channel6;
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| 147 | uint8_t channel7;
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| 148 | uint8_t channel5;
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| 149 | uint8_t reserved4;
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| 150 | uint8_t reserved5;
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| 151 | uint8_t reserved6;
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| 152 | uint8_t channel4;
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| 153 | } dma_page_regs_t;
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| 154 |
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| 155 | /** Addresses needed to setup a DMA channel. */
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| 156 | typedef struct dma_channel {
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| 157 | ioport8_t *offset_reg_address;
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| 158 | ioport8_t *size_reg_address;
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| 159 | ioport8_t *page_reg_address;
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| 160 | ioport8_t *single_mask_address;
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| 161 | ioport8_t *mode_address;
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| 162 | ioport8_t *flip_flop_address;
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| 163 | } dma_channel_t;
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| 164 |
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| 165 | typedef struct dma_controller {
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| 166 | dma_channel_t channels[8];
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| 167 | dma_page_regs_t *page_table;
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| 168 | dma_controller_regs_first_t *first;
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| 169 | dma_controller_regs_second_t *second;
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| 170 | bool initialized;
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| 171 | } dma_controller_t;
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| 172 |
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| 173 |
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| 174 | /** Standard i8237 DMA controller.
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| 175 | * http://zet.aluzina.org/index.php/8237_DMA_controller#DMA_Channel_Registers
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| 176 | */
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| 177 | static dma_controller_t controller_8237 = {
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| 178 | .channels = {
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| 179 | /* The first chip 8-bit */
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| 180 | { (uint8_t*)0x00, (uint8_t*)0x01, (uint8_t*)0x87,
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| 181 | (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
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| 182 | { (uint8_t*)0x02, (uint8_t*)0x03, (uint8_t*)0x83,
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| 183 | (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
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| 184 | { (uint8_t*)0x04, (uint8_t*)0x05, (uint8_t*)0x81,
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| 185 | (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
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| 186 | { (uint8_t*)0x06, (uint8_t*)0x07, (uint8_t*)0x82,
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| 187 | (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
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| 188 |
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| 189 | /* The second chip 16-bit */
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| 190 | { (uint8_t*)0xc0, (uint8_t*)0xc2, (uint8_t*)0x8f,
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| 191 | (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, },
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| 192 | { (uint8_t*)0xc4, (uint8_t*)0xc6, (uint8_t*)0x8b,
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| 193 | (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, },
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| 194 | { (uint8_t*)0xc8, (uint8_t*)0xca, (uint8_t*)0x89,
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| 195 | (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, },
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| 196 | { (uint8_t*)0xcc, (uint8_t*)0xce, (uint8_t*)0x8a,
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| 197 | (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, }, },
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| 198 |
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| 199 | .page_table = NULL,
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| 200 | .first = NULL,
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| 201 | .second = NULL,
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| 202 | .initialized = false,
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| 203 | };
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| 204 |
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| 205 | /* Initialize I/O access to DMA controller I/O ports.
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| 206 | * param controller DMA Controller structure to initialize.
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| 207 | * return Error code.
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| 208 | */
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| 209 | static inline int dma_controller_init(dma_controller_t *controller)
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| 210 | {
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| 211 | assert(controller);
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| 212 | int ret = pio_enable(
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| 213 | DMA_CONTROLLER_PAGE_BASE, sizeof(dma_page_regs_t),
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| 214 | (void**)&controller->page_table);
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| 215 | if (ret != EOK)
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| 216 | return EIO;
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| 217 |
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| 218 | ret = pio_enable(
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| 219 | DMA_CONTROLLER_FIRST_BASE, sizeof(dma_controller_regs_first_t),
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| 220 | (void**)&controller->first);
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| 221 | if (ret != EOK)
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| 222 | return EIO;
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| 223 |
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| 224 | ret = pio_enable(
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| 225 | DMA_CONTROLLER_SECOND_BASE, sizeof(dma_controller_regs_second_t),
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| 226 | (void**)&controller->second);
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| 227 | if (ret != EOK)
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| 228 | return EIO;
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| 229 | controller->initialized = true;
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| 230 |
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| 231 | /* Reset the controller */
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| 232 | pio_write_8(&controller->second->master_reset, 0xff);
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| 233 | pio_write_8(&controller->first->master_reset, 0xff);
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| 234 |
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| 235 |
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| 236 | return EOK;
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| 237 | }
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| 238 | /*----------------------------------------------------------------------------*/
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| 239 | /**
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| 240 | * Setup DMA channel to specified place and mode.
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| 241 | * @param channel DMA Channel 1,2,3 for 8 bit transfers, 5,6,7 for 16 bit.
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| 242 | * @param pa Physical address of the buffer. Must be < 16MB for 16 bit and < 1MB
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| 243 | * for 8 bit transfers.
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| 244 | * @param size DMA buffer size, limited to 64K.
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| 245 | * @param mode Mode of the DMA channel:
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| 246 | * - Read or Write
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| 247 | * - Allow automatic reset
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| 248 | * - Use address decrement instead of increment
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| 249 | * - Use SINGLE/BLOCK/ON DEMAND transfer mode
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| 250 | * @return Error code.
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| 251 | */
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| 252 | int dma_setup_channel(
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| 253 | unsigned channel, uint32_t pa, uint16_t size, uint8_t mode)
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| 254 | {
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| 255 | if (channel == 0 || channel == 4)
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| 256 | return ENOTSUP;
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| 257 | if (channel > 7)
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| 258 | return ENOENT;
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| 259 |
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| 260 | /* DMA is limited to 24 but addresses. */
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| 261 | if (pa >= (1 << 24))
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| 262 | return EINVAL;
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| 263 |
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| 264 | /* 8 bit channels use only 4 bits from the page register. */
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| 265 | if (channel > 0 && channel < 4 && pa >= (1 << 20))
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| 266 | return EINVAL;
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| 267 |
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| 268 | static fibril_mutex_t guard = FIBRIL_MUTEX_INITIALIZER(guard);
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| 269 |
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| 270 | fibril_mutex_lock(&guard);
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| 271 |
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| 272 | if (!controller_8237.initialized)
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| 273 | dma_controller_init(&controller_8237);
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| 274 |
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| 275 | if (!controller_8237.initialized) {
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| 276 | fibril_mutex_unlock(&guard);
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| 277 | return EIO;
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| 278 | }
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| 279 |
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| 280 | /* 16 bit transfers are a bit special */
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| 281 | ddf_msg(LVL_DEBUG, "Unspoiled address: %p and size: %zu.", pa, size);
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| 282 | if (channel > 4) {
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| 283 | /* Size must be aligned to 16 bits */
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| 284 | if ((size & 1) != 0) {
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| 285 | fibril_mutex_unlock(&guard);
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| 286 | return EINVAL;
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| 287 | }
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| 288 | size >>= 1;
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| 289 | /* Address is fun: lower 16bits need to be shifted by 1 */
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| 290 | pa = ((pa & 0xffff) >> 1) | (pa & 0xff0000);
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| 291 | }
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| 292 |
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| 293 | const dma_channel_t dma_channel = controller_8237.channels[channel];
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| 294 |
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| 295 | ddf_msg(LVL_DEBUG,
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| 296 | "Setting channel %u, to address %p(%zu), mode %hhx.",
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| 297 | channel, pa, size, mode);
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| 298 |
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| 299 | /* Mask DMA request */
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| 300 | uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel)
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| 301 | | DMA_SINGLE_MASK_MASKED_FLAG;
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| 302 | pio_write_8(dma_channel.single_mask_address, value);
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| 303 |
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| 304 | /* Set mode */
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| 305 | value = DMA_MODE_CHAN_TO_REG(channel) | mode;
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| 306 | ddf_msg(LVL_DEBUG2, "Writing mode byte: %p:%hhx.",
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| 307 | dma_channel.mode_address, value);
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| 308 | pio_write_8(dma_channel.mode_address, value);
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| 309 |
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| 310 | /* Set address -- reset flip-flop*/
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| 311 | pio_write_8(dma_channel.flip_flop_address, 0);
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| 312 |
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| 313 | /* Low byte */
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| 314 | value = pa & 0xff;
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| 315 | ddf_msg(LVL_DEBUG2, "Writing address low byte: %p:%hhx.",
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| 316 | dma_channel.offset_reg_address, value);
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| 317 | pio_write_8(dma_channel.offset_reg_address, value);
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| 318 |
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| 319 | /* High byte */
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| 320 | value = (pa >> 8) & 0xff;
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| 321 | ddf_msg(LVL_DEBUG2, "Writing address high byte: %p:%hhx.",
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| 322 | dma_channel.offset_reg_address, value);
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| 323 | pio_write_8(dma_channel.offset_reg_address, value);
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| 324 |
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| 325 | /* Page address - third byte */
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| 326 | value = (pa >> 16) & 0xff;
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| 327 | ddf_msg(LVL_DEBUG2, "Writing address page byte: %p:%hhx.",
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| 328 | dma_channel.page_reg_address, value);
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| 329 | pio_write_8(dma_channel.page_reg_address, value);
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| 330 |
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| 331 | /* Set size -- reset flip-flop */
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| 332 | pio_write_8(dma_channel.flip_flop_address, 0);
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| 333 |
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| 334 | /* Low byte */
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| 335 | value = (size - 1) & 0xff;
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| 336 | ddf_msg(LVL_DEBUG2, "Writing size low byte: %p:%hhx.",
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| 337 | dma_channel.size_reg_address, value);
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| 338 | pio_write_8(dma_channel.size_reg_address, value);
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| 339 |
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| 340 | /* High byte */
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| 341 | value = ((size - 1) >> 8) & 0xff;
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| 342 | ddf_msg(LVL_DEBUG2, "Writing size high byte: %p:%hhx.",
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| 343 | dma_channel.size_reg_address, value);
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| 344 | pio_write_8(dma_channel.size_reg_address, value);
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| 345 |
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| 346 | /* Unmask DMA request */
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| 347 | value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
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| 348 | pio_write_8(dma_channel.single_mask_address, value);
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| 349 |
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| 350 | fibril_mutex_unlock(&guard);
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| 351 |
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| 352 | return EOK;
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| 353 | }
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| 354 | /**
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| 355 | * @}
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| 356 | */
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