| 1 | /*
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| 2 | * Copyright (c) 2006 Martin Decky
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| 3 | * Copyright (c) 2010 Jiri Svoboda
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| 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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| 30 | /** @addtogroup uspace_drv_cuda_adb
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| 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | */
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| 35 |
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| 36 | #ifndef CUDA_HW_H_
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| 37 | #define CUDA_HW_H_
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| 38 |
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| 39 | #include <ddi.h>
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| 40 |
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| 41 | #include <stdint.h>
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| 42 |
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| 43 | typedef struct cuda_regs {
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| 44 | ioport8_t b;
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| 45 | uint8_t pad0[0x1ff];
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| 46 |
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| 47 | ioport8_t a;
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| 48 | uint8_t pad1[0x1ff];
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| 49 |
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| 50 | ioport8_t dirb;
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| 51 | uint8_t pad2[0x1ff];
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| 52 |
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| 53 | ioport8_t dira;
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| 54 | uint8_t pad3[0x1ff];
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| 55 |
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| 56 | ioport8_t t1cl;
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| 57 | uint8_t pad4[0x1ff];
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| 58 |
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| 59 | ioport8_t t1ch;
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| 60 | uint8_t pad5[0x1ff];
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| 61 |
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| 62 | ioport8_t t1ll;
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| 63 | uint8_t pad6[0x1ff];
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| 64 |
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| 65 | ioport8_t t1lh;
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| 66 | uint8_t pad7[0x1ff];
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| 67 |
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| 68 | ioport8_t t2cl;
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| 69 | uint8_t pad8[0x1ff];
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| 70 |
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| 71 | ioport8_t t2ch;
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| 72 | uint8_t pad9[0x1ff];
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| 73 |
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| 74 | ioport8_t sr;
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| 75 | uint8_t pad10[0x1ff];
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| 76 |
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| 77 | ioport8_t acr;
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| 78 | uint8_t pad11[0x1ff];
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| 79 |
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| 80 | ioport8_t pcr;
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| 81 | uint8_t pad12[0x1ff];
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| 82 |
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| 83 | ioport8_t ifr;
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| 84 | uint8_t pad13[0x1ff];
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| 85 |
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| 86 | ioport8_t ier;
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| 87 | uint8_t pad14[0x1ff];
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| 88 |
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| 89 | ioport8_t anh;
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| 90 | uint8_t pad15[0x1ff];
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| 91 | } cuda_regs_t;
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| 92 |
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| 93 | /** B register fields */
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| 94 | enum {
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| 95 | TREQ = 0x08,
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| 96 | TACK = 0x10,
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| 97 | TIP = 0x20
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| 98 | };
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| 99 |
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| 100 | /** IER register fields */
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| 101 | enum {
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| 102 | IER_CLR = 0x00,
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| 103 | IER_SET = 0x80,
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| 104 |
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| 105 | SR_INT = 0x04,
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| 106 | ALL_INT = 0x7f
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| 107 | };
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| 108 |
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| 109 | /** ACR register fields */
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| 110 | enum {
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| 111 | SR_OUT = 0x10
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| 112 | };
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| 113 |
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| 114 | /** Packet types */
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| 115 | enum {
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| 116 | PT_ADB = 0x00,
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| 117 | PT_CUDA = 0x01
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| 118 | };
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| 119 |
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| 120 | /** CUDA packet types */
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| 121 | enum {
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| 122 | CPT_AUTOPOLL = 0x01
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| 123 | };
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| 124 |
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| 125 | enum {
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| 126 | ADB_MAX_ADDR = 16
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| 127 | };
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| 128 |
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| 129 | #endif
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| 130 |
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| 131 | /** @}
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| 132 | */
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