source: mainline/uspace/drv/block/pc-floppy/pc-floppy_hw.h

Last change on this file was dc5647e, checked in by Jiri Svoboda <jiri@…>, 13 months ago

PC floppy disk driver

Bare minimum implemented.
  • Property mode set to 100644
File size: 8.9 KB
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[dc5647e]1/*
2 * Copyright (c) 2024 Jiri Svoboda
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup pci-ide
30 * @{
31 */
32/** @file PC Floppy Disk hardware definitions
33 *
34 * Based on
35 * - NEC uPD765A datasheet
36 * - Intel 82077AA Floppy Controller Datasheet
37 */
38
39#ifndef PC_FLOPPY_HW_H
40#define PC_FLOPPY_HW_H
41
42/** Command Codes */
43typedef enum {
44 /** Read Data */
45 fcc_read_data = 0x06,
46 /** Read Delete Data */
47 fcc_read_ddata = 0x0c,
48 /** Write Data */
49 fcc_write_data = 0x05,
50 /** Write Deleted Data */
51 fcc_write_ddata = 0x09,
52 /** Read a Track */
53 fcc_read_track = 0x02,
54 /** Read ID */
55 fcc_read_id = 0x0a,
56 /** Format a Track */
57 fcc_format_track = 0x0d,
58 /** Scan Equal */
59 fcc_scan_equal = 0x11,
60 /** Scan Low or Equal */
61 fcc_scan_lequal = 0x19,
62 /** Scan High or Equal */
63 fcc_scan_hequal = 0x1d,
64 /** Recalibrate */
65 fcc_recalibrate = 0x07,
66 /** Sense Interrupt Status */
67 fcc_sense_int_sts = 0x08,
68 /** Specify */
69 fcc_specify = 0x03,
70 /** Sense Drive Status */
71 fcc_sense_drv_sts = 0x04,
72 /** Seek */
73 fcc_seek = 0x0f
74} pc_fdc_cmd_code_t;
75
76/** MT|MF|SK flags used in flags_cc byte */
77typedef enum {
78 /** Multi Track */
79 fcf_mt = 0x80,
80 /** FM or MFM mode */
81 fcf_mf = 0x40,
82 /** Skip deleted address mark */
83 fcf_sk = 0x20
84} pc_fcd_flags_t;
85
86/** Command parameters common for most data commands */
87typedef struct {
88 /** [MT] | MF | [SK] | command code */
89 uint8_t flags_cc;
90 /** XXXXX | HD | US1 | US0 */
91 uint8_t hd_us;
92 /** Cylinder number */
93 uint8_t cyl;
94 /** Head number */
95 uint8_t head;
96 /** Record number */
97 uint8_t rec;
98 /** Number */
99 uint8_t number;
100 /** End of Track */
101 uint8_t eot;
102 /** Gap Length */
103 uint8_t gpl;
104 /** Data Length */
105 uint8_t dtl;
106} pc_fdc_cmd_data_t;
107
108/** Status data common for most commands */
109typedef struct {
110 /** Status 0 */
111 uint8_t st0;
112 /** Status 1 */
113 uint8_t st1;
114 /** Status 2 */
115 uint8_t st2;
116 /** Cylinder number */
117 uint8_t cyl;
118 /** Head number */
119 uint8_t head;
120 /** Record number */
121 uint8_t rec;
122 /** Number */
123 uint8_t number;
124} pc_fdc_cmd_status_t;
125
126/** Command parameters for Read ID command */
127typedef struct {
128 /** 0 | MF | 0 | command code */
129 uint8_t flags_cc;
130 /** XXXXX | HD | US1 | US0 */
131 uint8_t hd_us;
132} pc_fdc_read_id_data_t;
133
134/** Command parameters for Format a Track command */
135typedef struct {
136 /** 0 | MF | 0 | command code */
137 uint8_t flags_cc;
138 /** XXXXX | HD | US1 | US0 */
139 uint8_t hd_us;
140 /** Number */
141 uint8_t number;
142 /** Sectors per Cylinder */
143 uint8_t sec_cyl;
144 /** Gap Length */
145 uint8_t gpl;
146 /** Data Pattern */
147 uint8_t dpat;
148} pc_fdc_format_track_data_t;
149
150/** Command parameters for Recalibrate command */
151typedef struct {
152 /** 0 | 0 | 0 | command code */
153 uint8_t cc;
154 /** XXXXX | 0 | US1 | US0 */
155 uint8_t us;
156} pc_fdc_recalibrate_data_t;
157
158/** Command parameters for Sense Interrupt Status command */
159typedef struct {
160 /** 0 | 0 | 0 | command code */
161 uint8_t cc;
162} pc_fdc_sense_int_sts_data_t;
163
164/** Status data common for Sense Interrupt Status command */
165typedef struct {
166 /** Status 0 */
167 uint8_t st0;
168 /** Present Cylinder Number */
169 uint8_t pcn;
170} pc_fdc_sense_int_sts_status_t;
171
172/** Command parameters for Specify command */
173typedef struct {
174 /** 0 | 0 | 0 | command code */
175 uint8_t cc;
176 /** Step Rate Time, Head Unload Time */
177 uint8_t srt_hut;
178 /** Head Load Time, Non-DMA Mode */
179 uint8_t hlt_nd;
180} pc_fdc_secify_data_t;
181
182/** Command parameters for Sense Drive Status command */
183typedef struct {
184 /** 0 | 0 | 0 | command code */
185 uint8_t cc;
186 /** XXXXX | HD | US1 | US0 */
187 uint8_t hd_us;
188} pc_fdc_sense_drive_sts_data_t;
189
190/** Command parameters for Seek command */
191typedef struct {
192 /** 0 | 0 | 0 | command code */
193 uint8_t cc;
194 /** XXXXX | HD | US1 | US0 */
195 uint8_t hd_us;
196} pc_fdc_seek_data_t;
197
198/** Bits in Status Register A (SRA) PS/2 Mode */
199enum {
200 fsra2_int_pending = 0x80,
201 fsra2_ndrv2 = 0x40,
202 fsra2_step = 0x20,
203 fsra2_ntrk0 = 0x10,
204 fsra2_hdsel = 0x08,
205 fsra2_nindx = 0x04,
206 fsra2_nwp = 0x02,
207 fsra2_dir = 0x01
208};
209
210/** Bits in Status Register A (SRA) Model 30 Mode */
211enum {
212 fsra3_int_pending = 0x80,
213 fsra3_drq = 0x40,
214 fsra3_step_ff = 0x20,
215 fsra3_trko = 0x10,
216 fsra3_nhdsel = 0x08,
217 fsra3_index = 0x04,
218 fsra3_wp = 0x02,
219 fsra3_ndir = 0x01
220};
221
222/** Bits in Status Register B (SRB) PS/2 Mode */
223enum {
224 fsrb_d0sel = 0x20,
225 fsrb_wrd_tgl = 0x10,
226 fsrb_rdd_tgl = 0x08,
227 fsrb_we = 0x04,
228 fsrb_me1 = 0x02,
229 fsrb_me0 = 0x01
230};
231
232/** Bits in Status Register B (SRB) Model 30 Mode */
233enum {
234 fsrb_ndrv2 = 0x80,
235 fsrb_nds1 = 0x40,
236 fsrb_nds0 = 0x20,
237 fsrb_wrd_ff = 0x10,
238 fsrb_rdd_ff = 0x08,
239 fsrb_we_ff = 0x04,
240 fsrb_nds3 = 0x02,
241 fsrb_nds2 = 0x01
242};
243
244/** Bits in Digital Output Register (DOR) */
245enum {
246 fdor_me3 = 0x80,
247 fdor_me2 = 0x40,
248 fdor_me1 = 0x20,
249 fdor_me0 = 0x10,
250 fdor_ndmagate = 0x08,
251 fdor_nreset = 0x04,
252 fdor_ds1 = 0x02,
253 fdor_ds0 = 0x01
254};
255
256/** Bits in Tape Drive Register (TDR) */
257enum {
258 ftdr_ts1 = 0x02,
259 ftdr_ts0 = 0x01
260};
261
262/** Bits in Datarate Select Register (DSR) */
263enum {
264 fdsr_sw_reset = 0x80,
265 fdsr_power_down = 0x40,
266 fdsr_precomp2 = 0x10,
267 fdsr_precomp1 = 0x08,
268 fdsr_precomp0 = 0x04,
269 fdsr_drate_sel1 = 0x02,
270 fdsr_drate_sel0 = 0x01
271};
272
273/** Combined values of DSR.DRATE_SEL1/0 */
274enum {
275 fdsr_drate_1mbps = 0x03,
276 fdsr_drate_500kbps = 0x00,
277 fdsr_drate_300kbps = 0x01,
278 fdsr_drate_250kbps = 0x02
279};
280
281/** Bits in Main Status Register (MSR) */
282enum {
283 /** Request for Master */
284 fmsr_rqm = 0x80,
285 /** Data Input/Output */
286 fmsr_dio = 0x40,
287 /** Execution Mode */
288 fmsr_exm = 0x20,
289 /** FDC Busy */
290 fmsr_cb = 0x10,
291 /** FDD 3 Busy */
292 fmsr_d3b = 0x08,
293 /** FDD 2 Busy */
294 fmsr_d2b = 0x04,
295 /** FDD 1 Busy */
296 fmsr_d1b = 0x02,
297 /** FDD 0 Busy */
298 fmsr_d0b = 0x01,
299};
300
301/** Bits in Digital Input Register, PC-AT Mode */
302enum {
303 fdira_dsk_chg = 0x80
304};
305
306/** Bits in Digital Input Register, PS/2 Mode */
307enum {
308 fdir2_dsk_chg = 0x80,
309 fdir2_drate_sel1 = 0x04,
310 fdir2_drate_sel0 = 0x02,
311 fdir2_nhigh_dens = 0x01
312};
313
314/** Bits in Digital Input Register, Model 30 Mode */
315enum {
316 fdir3_dsk_chg = 0x80,
317 fdir3_ndma_gate = 0x08,
318 fdir3_noprec = 0x04,
319 fdir3_drate_sel1 = 0x02,
320 fdir3_drate_sel0 = 0x01
321};
322
323/** Bits in Configuration Control Register (CCR) */
324enum {
325 fccr_noprec = 0x04,
326 fccr_drate_sel1 = 0x02,
327 fccr_drate_sel0 = 0x01
328};
329
330/** Bits in Status Register 0 (SR0) */
331enum {
332 fsr0_ic_mask = 0xc0,
333 fsr0_ic_normal = 0x00,
334 fsr0_ic_abnormal = 0x40,
335 fsr0_ic_invcmd = 0x80,
336 fsr0_ic_abnormal_poll = 0xc0,
337 fsr0_seek_end = 0x20,
338 fsr0_equip_check = 0x10,
339 fsr0_head_addr = 0x04,
340 fsr0_ds1 = 0x02,
341 fsr0_ds0 = 0x01
342};
343
344/** Bits in Status Register 1 (SR1) */
345enum {
346 fsr1_end_of_cyl = 0x80,
347 fsr1_data_error = 0x20,
348 fsr1_overr_underr = 0x10,
349 fsr1_no_data = 0x04,
350 fsr1_not_writable = 0x02,
351 fsr1_missing_am = 0x01
352};
353
354/** Bits in Status Register 2 (SR2) */
355enum {
356 fsr2_control_mark = 0x40,
357 fsr1_derr_df = 0x20,
358 fsr1_wrong_cyl = 0x10,
359 fsr1_bad_cyl = 0x02,
360 fsr1_missing_dam = 0x01
361};
362
363/** Registers */
364typedef union {
365 struct { /* read only */
366 /** Status Register A */
367 uint8_t sra;
368 /** Starus Register B */
369 uint8_t srb;
370 /** Padding */
371 uint8_t ro_pad2[2];
372 /** Main Status Register */
373 uint8_t msr;
374 /** Padding */
375 uint8_t ro_pad5[2];
376 /** Digital Inut Register */
377 uint8_t dir;
378 };
379 struct { /* write only */
380 /** Padding */
381 uint8_t wo_pad0[4];
382 /** Datarate Select Register */
383 uint8_t dsr;
384 /** Padding */
385 uint8_t wo_pad5[2];
386 /** Configuration Control Register */
387 uint8_t ccr;
388 };
389 struct { /* read/write */
390 /** Padding */
391 uint8_t rw_pad0[2];
392 /** Digital Output Register */
393 uint8_t dor;
394 /** Tape Drive Register */
395 uint8_t tdr;
396 /** Padding */
397 uint8_t rw_pad4;
398 /** Data (FIFO) */
399 uint8_t data;
400 };
401} pc_fdc_regs_t;
402
403enum {
404 /** Max. time we need to wait for MSR status */
405 msr_max_wait_usec = 250
406};
407
408#endif
409
410/** @}
411 */
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