source: mainline/uspace/drv/block/ahci/ahci_hw.h@ 2ab8ab3

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 2ab8ab3 was d1582b50, checked in by Jiri Svoboda <jiri@…>, 5 years ago

Fix spacing in single-line comments using latest ccheck

This found incorrectly formatted section comments (with blocks of
asterisks or dashes). I strongly believe against using section comments
but I am not simply removing them since that would probably be
controversial.
  • Property mode set to 100644
File size: 28.1 KB
Line 
1/*
2 * Copyright (c) 2012 Petr Jerman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Header for AHCI driver (AHCI 1.3 specification).
31 */
32
33#ifndef __AHCI_HW_H__
34#define __AHCI_HW_H__
35
36#include <stdint.h>
37
38/*
39 * AHCI standard constants
40 */
41
42/** AHCI standard 1.3 - maximum ports. */
43#define AHCI_MAX_PORTS 32
44
45/*
46 * AHCI PCI Registers
47 */
48
49/** AHCI PCI register Identifiers offset. */
50#define AHCI_PCI_ID 0x00
51/** AHCI PCI register Command offset. */
52#define AHCI_PCI_CMD 0x04
53/** AHCI PCI register Device Status offset. */
54#define AHCI_PCI_STS 0x06
55/** AHCI PCI register Revision ID offset. */
56#define AHCI_PCI_RID 0x08
57/** AHCI PCI register Class Codes offset. */
58#define AHCI_PCI_CC 0x09
59/** AHCI PCI register Cache Line Size offset. */
60#define AHCI_PCI_CLS 0x0C
61/** AHCI PCI register Master Latency Timer offset. */
62#define AHCI_PCI_MLT 0x0D
63/** AHCI PCI register Header Type offset. */
64#define AHCI_PCI_HTYPE 0x0E
65/** AHCI PCI register Built In Self Test (Optional) offset. */
66#define AHCI_PCI_BIST 0x0F
67/** AHCI PCI register Other Base Address Registres (Optional). */
68#define AHCI_PCI_BAR0 0x10
69/** AHCI PCI register Other Base Address Registres (Optional). */
70#define AHCI_PCI_BAR1 0x14
71/** AHCI PCI register Other Base Address Registres (Optional). */
72#define AHCI_PCI_BAR2 0x18
73/** AHCI PCI register Other Base Address Registres (Optional). */
74#define AHCI_PCI_BAR3 0x1C
75/** AHCI PCI register Other Base Address Registres (Optional). */
76#define AHCI_PCI_BAR4 0x20
77/** AHCI PCI register AHCI Base Address offset. */
78#define AHCI_PCI_ABAR 0x24
79/** AHCI PCI register Subsystem Identifiers offset. */
80#define AHCI_PCI_SS 0x2C
81/** AHCI PCI register Expansion ROM Base Address (Optional) offset. */
82#define AHCI_PCI_EROM 0x30
83/** AHCI PCI register Capabilities Pointer offset. */
84#define AHCI_PCI_CAP 0x34
85/** AHCI PCI register Interrupt Information offset. */
86#define AHCI_PCI_INTR 0x3C
87/** AHCI PCI register Min Grant (Optional) offset. */
88#define AHCI_PCI_MGNT 0x3E
89/** AHCI PCI register Max Latency (Optional) offset. */
90#define AHCI_PCI_MLAT 0x3F
91
92/** AHCI PCI register Identifiers. */
93typedef struct {
94 /** Indicates the company vendor assigned by the PCI SIG. */
95 uint16_t vendorid;
96 /** Indicates what device number assigned by the vendor */
97 uint16_t deviceid;
98} ahci_pcireg_id_t;
99
100/** AHCI PCI register Command. */
101typedef union {
102 struct {
103 /** I/O Space Enable. */
104 unsigned int iose : 1;
105 /** Memory Space Enable. */
106 unsigned int mse : 1;
107 /** Bus Master Enable. */
108 unsigned int bme : 1;
109 /** Special Cycle Enable. */
110 unsigned int sce : 1;
111 /** Memory Write and Invalidate Enable. */
112 unsigned int mwie : 1;
113 /** VGA Palette Snooping Enable. */
114 unsigned int vga : 1;
115 /** Parity Error Response Enable. */
116 unsigned int pee : 1;
117 /** Wait Cycle Enable. */
118 unsigned int wcc : 1;
119 /** SERR# Enable. */
120 unsigned int see : 1;
121 /** Fast Back-to-Back Enable. */
122 unsigned int fbe : 1;
123 /** Interrupt Disable - disables the HBA from generating interrupts.
124 * This bit does not have any effect on MSI operation.
125 */
126 unsigned int id : 1;
127 /** Reserved. */
128 unsigned int reserved : 5;
129 };
130 uint16_t u16;
131} ahci_pcireg_cmd_t;
132
133/** AHCI PCI register Command - Interrupt Disable bit. */
134#define AHCI_PCIREG_CMD_ID 0x0400
135
136/** AHCI PCI register Command - Bus Master Enable bit. */
137#define AHCI_PCIREG_CMD_BME 0x0004
138
139/** AHCI PCI register Device status. */
140typedef union {
141 struct {
142 /** Reserved. */
143 unsigned int reserved1 : 3;
144 /** Indicate the interrupt status of the device (1 = asserted). */
145 unsigned int is : 1;
146 /** Indicates presence of capatibility list. */
147 unsigned int cl : 1;
148 /** 66 Mhz capable. */
149 unsigned int c66 : 1;
150 /** Reserved. */
151 unsigned int reserved2 : 1;
152 /** Fast back to back capable. */
153 unsigned int fbc : 1;
154 /** Master data parity error detected. */
155 unsigned int dpd : 1;
156 /** Device select timing. */
157 unsigned int devt : 2;
158 /** Signaled target abort. */
159 unsigned int sta : 1;
160 /** Received target abort. */
161 unsigned int rta : 1;
162 /** Received master abort. */
163 unsigned int rma : 1;
164 /** Signaled system error. */
165 unsigned int sse : 1;
166 /** Detected parity error. */
167 unsigned int dpe : 1;
168 };
169 uint16_t u16;
170} ahci_pcireg_sts_t;
171
172/** AHCI PCI register Revision ID. */
173typedef struct {
174 /** Indicates stepping of the HBA hardware. */
175 uint8_t u8;
176} ahci_pcireg_rid_t;
177
178/** AHCI PCI register Class Codes. */
179typedef struct {
180 /** Programing interface, when set to 01h and the scc is set to 06h,
181 * indicates that this an AHCI HBA major revision 1.
182 */
183 uint8_t pi;
184 /** When set to 06h, indicates that is a SATA device. */
185 uint8_t scc;
186 /** Value 01 indicates that is a mass storage device. */
187 uint8_t bcc;
188} ahci_pcireg_cc_t_t;
189
190/** AHCI PCI register Cache Line Size. */
191typedef struct {
192 /** Cache line size for use with the memory write and invalidate command. */
193 uint8_t u8;
194} ahci_pcireg_cls_t;
195
196/** AHCI PCI register Master Latency Timer. */
197typedef struct {
198 /** Master latency timer,indicates the number of clocks the HBA is allowed
199 * to acts as master on PCI.
200 */
201 uint8_t u8;
202} ahci_pcireg_mlt_t;
203
204/** AHCI PCI register Header Type. */
205typedef union {
206 struct {
207 /** Header layout. */
208 unsigned int hl : 7;
209 /** Multi function device flag. */
210 unsigned int mfd : 1;
211 };
212 uint8_t u8;
213} ahci_pciregs_htype_t;
214
215/** AHCI PCI register Built in self test. */
216typedef union {
217 struct {
218 /** Indicates the completion status of BIST
219 * non-zero value indicates a failure.
220 */
221 unsigned int cc : 4;
222 /** Reserved. */
223 unsigned int reserved : 2;
224 /** Software sets this bit to 1 to invoke BIST,
225 * the HBA clears this bit to 0 when BIST is complete.
226 */
227 unsigned int sb : 1;
228 /** BIST capable. */
229 unsigned int bc : 1;
230 };
231 uint8_t u8;
232} ahci_pciregs_bist_t;
233
234/** AHCI PCI register AHCI Base Address <BAR 5>. */
235typedef union {
236 struct {
237 /** Indicates a request for register memory space. */
238 unsigned int rte : 1;
239 /** Indicates the this range can be mapped anywhere in 32-bit address
240 * space.
241 */
242 unsigned int tp : 2;
243 /** Indicate that this range is not prefetchable. */
244 unsigned int pf : 1;
245 /** Reserved. */
246 unsigned int reserved : 9;
247 /** Base address of registry memory space. */
248 unsigned int ba : 19;
249 };
250 uint32_t u32;
251} ahci_pciregs_abar_t;
252
253/** AHCI PCI register Subsystem Identifiers. */
254typedef struct {
255 /** Sub system vendor identifier. */
256 uint8_t ssvid;
257 /** Sub system identifier. */
258 uint8_t ssid;
259} ahci_pcireg_ss_t;
260
261/** AHCI PCI registers Expansion ROM Base Address. */
262typedef struct {
263 /** Indicates the base address of the HBA expansion ROM. */
264 uint32_t u32;
265} ahci_pcireg_erom_t;
266
267/** AHCI PCI register Capabilities Pointer. */
268typedef struct {
269 /** Indicates the first capability pointer offset. */
270 uint8_t u8;
271} ahci_pcireg_cap_t;
272
273/** AHCI PCI register Interrupt Information. */
274typedef struct {
275 /*
276 * Software written value to indicate which interrupt vector
277 * the interrupt is connected to.
278 */
279 uint8_t iline;
280 /** This indicates the interrupt pin the HBA uses. */
281 uint8_t ipin;
282} ahci_pcireg_intr;
283
284/** AHCI PCI register Min Grant (Optional). */
285typedef struct {
286 /** Indicates the minimum grant time that the device
287 * wishes grant asserted.
288 */
289 uint8_t u8;
290} ahci_pcireg_mgnt_t;
291
292/** AHCI PCI register Max Latency (Optional). */
293typedef struct {
294 /** Indicates the maximum latency that the device can withstand. */
295 uint8_t u8;
296} ahci_pcireg_mlat_t;
297
298/*
299 * AHCI Memory Registers
300 */
301
302/** Number of pages for ahci memory registers. */
303#define AHCI_MEMREGS_PAGES_COUNT 8
304
305/** AHCI Memory register Generic Host Control - HBA Capabilities. */
306typedef union {
307 struct {
308 /** Number of Ports. */
309 unsigned int np : 5;
310 /** Supports External SATA. */
311 unsigned int sxs : 1;
312 /** Enclosure Management Supported. */
313 unsigned int ems : 1;
314 /** Command Completion Coalescing Supported. */
315 unsigned int cccs : 1;
316 /** Number of Command Slots. */
317 unsigned int ncs : 5;
318 /** Partial State Capable. */
319 unsigned int psc : 1;
320 /** Slumber State Capable. */
321 unsigned int ssc : 1;
322 /** PIO Multiple DRQ Block. */
323 unsigned int pmd : 1;
324 /** FIS-based Switching Supported. */
325 unsigned int fbss : 1;
326 /** Supports Port Multiplier. */
327 unsigned int spm : 1;
328 /** Supports AHCI mode only. */
329 unsigned int sam : 1;
330 /** Reserved. */
331 unsigned int reserved : 1;
332 /** Interface Speed Support. */
333 unsigned int iss : 4;
334 /** Supports Command List Override. */
335 unsigned int sclo : 1;
336 /** Supports Activity LED. */
337 unsigned int sal : 1;
338 /** Supports Aggressive Link Power Management. */
339 unsigned int salp : 1;
340 /** Supports Staggered Spin-up. */
341 unsigned int sss : 1;
342 /** Supports Mechanical Presence Switch. */
343 unsigned int smps : 1;
344 /** Supports SNotification Register. */
345 unsigned int ssntf : 1;
346 /** Supports Native Command Queuing. */
347 unsigned int sncq : 1;
348 /** Supports 64-bit Addressing. */
349 unsigned int s64a : 1;
350 };
351 uint32_t u32;
352} ahci_ghc_cap_t;
353
354/** AHCI Memory register Generic Host Control Global Host Control. */
355typedef union {
356 struct {
357 /** HBA Reset. */
358 unsigned int hr : 1;
359 /** Interrupt Enable. */
360 unsigned int ie : 1;
361 /** MSI Revert to Single Message. */
362 unsigned int mrsm : 1;
363 /** Reserved. */
364 unsigned int reserved : 28;
365 /** AHCI Enable. */
366 unsigned int ae : 1;
367 };
368 uint32_t u32;
369} ahci_ghc_ghc_t;
370
371/** AHCI Enable mask bit. */
372#define AHCI_GHC_GHC_AE 0x80000000
373
374/** AHCI Interrupt Enable mask bit. */
375#define AHCI_GHC_GHC_IE 0x00000002
376
377/** AHCI Memory register Interrupt pending register. */
378typedef uint32_t ahci_ghc_is_t;
379
380/** AHCI GHC register offset. */
381#define AHCI_GHC_IS_REGISTER_OFFSET 2
382
383/** AHCI ports registers offset. */
384#define AHCI_PORTS_REGISTERS_OFFSET 64
385
386/** AHCI port registers size. */
387#define AHCI_PORT_REGISTERS_SIZE 32
388
389/** AHCI port IS register offset. */
390#define AHCI_PORT_IS_REGISTER_OFFSET 4
391
392/** AHCI Memory register Ports implemented. */
393typedef struct {
394 /** If a bit is set to 1, the corresponding port
395 * is available for software use.
396 */
397 uint32_t u32;
398} ahci_ghc_pi_t;
399
400/** AHCI Memory register AHCI version. */
401typedef struct {
402 /** Indicates the minor version */
403 uint16_t mnr;
404 /** Indicates the major version */
405 uint16_t mjr;
406} ahci_ghc_vs_t;
407
408/** AHCI Memory register Command completion coalesce control. */
409typedef union {
410 struct {
411 /** Enable CCC features. */
412 unsigned int en : 1;
413 /** Reserved. */
414 unsigned int reserved : 2;
415 /** Interrupt number for CCC. */
416 unsigned int intr : 5;
417 /** Number of command completions that are necessary to cause
418 * a CCC interrupt.
419 */
420 uint8_t cc;
421 /** Timeout value in ms. */
422 uint16_t tv;
423 };
424 uint32_t u32;
425} ahci_ghc_ccc_ctl_t;
426
427/** AHCI Memory register Command completion coalescing ports. */
428typedef struct {
429 /** If a bit is set to 1, the corresponding port is
430 * part of the command completion coalescing feature.
431 */
432 uint32_t u32;
433} ahci_ghc_ccc_ports_t;
434
435/** AHCI Memory register Enclosure management location. */
436typedef struct {
437 /** Size of the transmit message buffer area in dwords. */
438 uint16_t sz;
439 /*
440 * Offset of the transmit message buffer area in dwords
441 * from the beginning of ABAR
442 */
443 uint16_t ofst;
444} ahci_ghc_em_loc;
445
446/** AHCI Memory register Enclosure management control. */
447typedef union {
448 struct {
449 /** Message received. */
450 unsigned int mr : 1;
451 /** Reserved. */
452 unsigned int reserved : 7;
453 /** Transmit message. */
454 unsigned int tm : 1;
455 /** Reset. */
456 unsigned int rst : 1;
457 /** Reserved. */
458 unsigned int reserved2 : 6;
459 /** LED message types. */
460 unsigned int led : 1;
461 /** Support SAFT-TE message type. */
462 unsigned int safte : 1;
463 /** Support SES-2 message type. */
464 unsigned int ses2 : 1;
465 /** Support SGPIO register. */
466 unsigned int sgpio : 1;
467 /** Reserved. */
468 unsigned int reserved3 : 4;
469 /** Single message buffer. */
470 unsigned int smb : 1;
471 /** Support transmitting only. */
472 unsigned int xmt : 1;
473 /** Activity LED hardware driven. */
474 unsigned int alhd : 1;
475 /** Port multiplier support. */
476 unsigned int pm : 1;
477 /** Reserved. */
478 unsigned int reserved4 : 4;
479 };
480 uint32_t u32;
481} ahci_ghc_em_ctl_t;
482
483/** AHCI Memory register HBA capatibilities extended. */
484typedef union {
485 struct {
486 /** HBA support BIOS/OS handoff mechanism,
487 * implemented BOHC register.
488 */
489 unsigned int boh : 1;
490 /** Support for NVMHCI register. */
491 unsigned int nvmp : 1;
492 /** Automatic partial to slumber transition support. */
493 unsigned int apst : 1;
494 /** Reserved. */
495 unsigned int reserved : 29;
496 };
497 uint32_t u32;
498} ahci_ghc_cap2_t;
499
500/** AHCI Memory register BIOS/OS Handoff control and status. */
501typedef union {
502 struct {
503 /** BIOS Owned semaphore. */
504 unsigned int bos : 1;
505 /** OS Owned semaphore. */
506 unsigned int oos : 1;
507 /** SMI on OS ownership change enable. */
508 unsigned int sooe : 1;
509 /** OS ownership change. */
510 unsigned int ooc : 1;
511 /** BIOS Busy. */
512 unsigned int bb : 1;
513 /** Reserved. */
514 unsigned int reserved : 27;
515 };
516 uint32_t u32;
517} ahci_ghc_bohc_t;
518
519/** AHCI Memory register Generic Host Control. */
520typedef struct {
521 /** Host Capabilities */
522 uint32_t cap;
523 /** Global Host Control */
524 uint32_t ghc;
525 /** Interrupt Status */
526 ahci_ghc_is_t is;
527 /** Ports Implemented */
528 uint32_t pi;
529 /** Version */
530 uint32_t vs;
531 /** Command Completion Coalescing Control */
532 uint32_t ccc_ctl;
533 /** Command Completion Coalescing Ports */
534 uint32_t ccc_ports;
535 /** Enclosure Management Location */
536 uint32_t em_loc;
537 /** Enclosure Management Control */
538 uint32_t em_ctl;
539 /** Host Capabilities Extended */
540 uint32_t cap2;
541 /** BIOS/OS Handoff Control and Status */
542 uint32_t bohc;
543} ahci_ghc_t;
544
545/** AHCI Memory register Port x Command List Base Address. */
546typedef union {
547 struct {
548 /** Reserved. */
549 unsigned int reserved : 10;
550 /** Command List Base Address (CLB) - Indicates the 32-bit base physical
551 * address for the command list for this port. This base is used when
552 * fetching commands to execute. The structure pointed to by this
553 * address range is 1K-bytes in length. This address must be 1K-byte
554 * aligned as indicated by bits 09:00 being read only.
555 */
556 unsigned int clb : 22;
557 };
558 uint32_t u32;
559} ahci_port_clb_t;
560
561/** AHCI Memory register Port x Command List Base Address Upper 32-Bits. */
562typedef struct {
563 /** Command List Base Address Upper (CLBU): Indicates the upper 32-bits
564 * for the command list base physical address for this port. This base
565 * is used when fetching commands to execute. This register shall
566 * be read only for HBAs that do not support 64-bit addressing.
567 */
568 uint32_t u32;
569} ahci_port_clbu_t;
570
571/** AHCI Memory register Port x FIS Base Address. */
572typedef union {
573 struct {
574 /** Reserved. */
575 unsigned int reserved : 8;
576 /** FIS Base Address (FB) - Indicates the 32-bit base physical address
577 * for received FISes. The structure pointed to by this address range
578 * is 256 bytes in length. This address must be 256-byte aligned as
579 * indicated by bits 07:00 being read only. When FIS-based switching
580 * is in use, this structure is 4KB in length and the address shall be
581 * 4KB aligned.
582 */
583 unsigned int fb : 24;
584 };
585 uint32_t u32;
586} ahci_port_fb_t;
587
588/** AHCI Memory register Port x FIS Base Address Upper 32-Bits. */
589typedef struct {
590 /** FIS Base Address Upper (FBU) - Indicates the upper 32-bits
591 * for the received FIS base physical address for this port. This register
592 * shall be read only for HBAs that do not support 64-bit addressing.
593 */
594 uint32_t u32;
595} ahci_port_fbu_t;
596
597/** AHCI Memory register Port x Interrupt Status. */
598typedef uint32_t ahci_port_is_t;
599
600#define AHCI_PORT_IS_DHRS (1 << 0)
601#define AHCI_PORT_IS_PSS (1 << 1)
602#define AHCI_PORT_IS_DSS (1 << 2)
603#define AHCI_PORT_IS_SDBS (1 << 3)
604#define AHCI_PORT_IS_UFS (1 << 4)
605#define AHCI_PORT_IS_DPS (1 << 5)
606#define AHCI_PORT_IS_PCS (1 << 6)
607#define AHCI_PORT_IS_DMPS (1 << 7)
608
609#define AHCI_PORT_IS_PRCS (1 << 22)
610#define AHCI_PORT_IS_IPMS (1 << 23)
611#define AHCI_PORT_IS_OFS (1 << 24)
612#define AHCI_PORT_IS_INFS (1 << 26)
613#define AHCI_PORT_IS_IFS (1 << 27)
614#define AHCI_PORT_IS_HDBS (1 << 28)
615#define AHCI_PORT_IS_HBFS (1 << 29)
616#define AHCI_PORT_IS_TFES (1 << 30)
617#define AHCI_PORT_IS_CPDS (1 << 31)
618
619#define AHCI_PORT_END_OF_OPERATION \
620 (AHCI_PORT_IS_DHRS | \
621 AHCI_PORT_IS_SDBS )
622
623#define AHCI_PORT_IS_ERROR \
624 (AHCI_PORT_IS_UFS | \
625 AHCI_PORT_IS_PCS | \
626 AHCI_PORT_IS_DMPS | \
627 AHCI_PORT_IS_PRCS | \
628 AHCI_PORT_IS_IPMS | \
629 AHCI_PORT_IS_OFS | \
630 AHCI_PORT_IS_INFS | \
631 AHCI_PORT_IS_IFS | \
632 AHCI_PORT_IS_HDBS | \
633 AHCI_PORT_IS_HBFS | \
634 AHCI_PORT_IS_TFES | \
635 AHCI_PORT_IS_CPDS)
636
637#define AHCI_PORT_IS_PERMANENT_ERROR \
638 (AHCI_PORT_IS_PCS | \
639 AHCI_PORT_IS_DMPS | \
640 AHCI_PORT_IS_PRCS | \
641 AHCI_PORT_IS_IPMS | \
642 AHCI_PORT_IS_CPDS )
643
644/** Evaluate end of operation status from port interrupt status.
645 *
646 * @param port_is Value of port interrupt status.
647 *
648 * @return Indicate end of operation status.
649 *
650 */
651static inline int ahci_port_is_end_of_operation(ahci_port_is_t port_is)
652{
653 return port_is & AHCI_PORT_END_OF_OPERATION;
654}
655
656/** Evaluate error status from port interrupt status.
657 *
658 * @param port_is Value of port interrupt status.
659 *
660 * @return Indicate error status.
661 *
662 */
663static inline int ahci_port_is_error(ahci_port_is_t port_is)
664{
665 return port_is & AHCI_PORT_IS_ERROR;
666}
667
668/** Evaluate permanent error status from port interrupt status.
669 *
670 * @param port_is Value of port interrupt status.
671 *
672 * @return Indicate permanent error status.
673 *
674 */
675static inline int ahci_port_is_permanent_error(ahci_port_is_t port_is)
676{
677 return port_is & AHCI_PORT_IS_PERMANENT_ERROR;
678}
679
680/** Evaluate task file error status from port interrupt status.
681 *
682 * @param port_is Value of port interrupt status.
683 *
684 * @return Indicate error status.
685 *
686 */
687static inline int ahci_port_is_tfes(ahci_port_is_t port_is)
688{
689 return port_is & AHCI_PORT_IS_TFES;
690}
691
692/** AHCI Memory register Port x Interrupt Enable. */
693typedef union {
694 struct {
695 /** Device to Host Register FIS Interrupt Enable. */
696 unsigned int dhre : 1;
697 /** PIO Setup FIS Interrupt Enable. */
698 unsigned int pse : 1;
699 /** DMA Setup FIS Interrupt Enable. */
700 unsigned int dse : 1;
701 /** Set Device Bits Interrupt Eenable. */
702 unsigned int sdbe : 1;
703 /** Unknown FIS Interrupt Enable. */
704 unsigned int ufe : 1;
705 /** Descriptor Processed Interrupt Enable. */
706 unsigned int dpe : 1;
707 /** Port Change Interrupt Enable. */
708 unsigned int pce : 1;
709 /** Device Mechanical Presence Enable. */
710 unsigned int dmpe : 1;
711 /** Reserved. */
712 unsigned int reserved1 : 14;
713 /** PhyRdy Change Interrupt Enable. */
714 unsigned int prce : 1;
715 /** Incorrect Port Multiplier Enable. */
716 unsigned int ipme : 1;
717 /** Overflow Status Enable. */
718 unsigned int ofe : 1;
719 /** Reserved. */
720 unsigned int reserved2 : 1;
721 /** Interface Non-fatal Error Enable. */
722 unsigned int infe : 1;
723 /** Interface Fatal Error Enable. */
724 unsigned int ife : 1;
725 /** Host Bus Data Error Enable. */
726 unsigned int hbde : 1;
727 /** Host Bus Fatal Error Enable. */
728 unsigned int hbfe : 1;
729 /** Task File Error Enable. */
730 unsigned int tfee : 1;
731 /** Cold Port Detect Enable. */
732 unsigned int cpde : 1;
733 };
734 uint32_t u32;
735} ahci_port_ie_t;
736
737/** AHCI Memory register Port x Command and Status. */
738typedef union {
739 struct {
740 /** Start - when set, the HBA may process the command list. */
741 unsigned int st : 1;
742 /** Spin-Up Device. */
743 unsigned int sud : 1;
744 /** Power On Device. */
745 unsigned int pod : 1;
746 /** Command List Override. */
747 unsigned int clo : 1;
748 /** FIS Receive Enable. */
749 unsigned int fre : 1;
750 /** Reserved. */
751 unsigned int reserved : 3;
752 /** Current Command Slot. */
753 unsigned int ccs : 5;
754 /** Mechanical Presence Switch State. */
755 unsigned int mpss : 1;
756 /** FIS Receive Running. */
757 unsigned int fr : 1;
758 /** Command List Running. */
759 unsigned int cr : 1;
760 /** Cold Presence State. */
761 unsigned int cps : 1;
762 /** Port Multiplier Attached. */
763 unsigned int pma : 1;
764 /** Hot Plug Capable Port. */
765 unsigned int hpcp : 1;
766 /** Mechanical Presence Switch Attached to Port. */
767 unsigned int mpsp : 1;
768 /** Cold Presence Detection. */
769 unsigned int cpd : 1;
770 /** External SATA Port. */
771 unsigned int esp : 1;
772 /** FIS-based Switching Capable Port. */
773 unsigned int fbscp : 1;
774 /** Automatic Partial to Slumber Transitions Enabled. */
775 unsigned int apste : 1;
776 /** Device is ATAPI. */
777 unsigned int atapi : 1;
778 /** Drive LED on ATAPI Enable. */
779 unsigned int dlae : 1;
780 /** Aggressive Link Power Management Enable. */
781 unsigned int alpe : 1;
782 /** Aggressive Slumber / Partial. */
783 unsigned int asp : 1;
784 /** Interface Communication Control.
785 * Values:
786 * 7h - fh Reserved,
787 * 6h Slumber - This shall cause the HBA to request a transition
788 * of the interface to the Slumber state,
789 * 3h - 5h Reserved,
790 * 2h Partial - This shall cause the HBA to request a transition
791 * of the interface to the Partial state,
792 * 1h Active,
793 * 0h No-Op / Idle.
794 */
795 unsigned int icc : 4;
796 };
797 uint32_t u32;
798} ahci_port_cmd_t;
799
800/** AHCI Memory register Port x Task File Data. */
801typedef union {
802 struct {
803 /** Status (STS): Contains the latest copy of the task file
804 * status register.
805 */
806 uint8_t sts;
807 /** Error (ERR) - Contains the latest copy of the task file
808 * error register.
809 */
810 uint8_t err;
811 /** Reserved. */
812 uint16_t reserved;
813 };
814 uint32_t u32;
815} ahci_port_tfd_t;
816
817/** AHCI Memory register Port x Signature. */
818typedef union {
819 struct {
820 /** Sector Count Register */
821 uint8_t sector_count;
822 /** LBA Low Register */
823 uint8_t lba_lr;
824 /** LBA Mid Register */
825 uint8_t lba_mr;
826 /** LBA High Register */
827 uint8_t lba_hr;
828 };
829 uint32_t u32;
830} ahci_port_sig_t;
831
832/** AHCI Memory register Port x Serial ATA Status (SCR0: SStatus). */
833typedef union {
834 struct {
835 /** Device Detection */
836 unsigned int det : 4;
837 /** Current Interface Speed */
838 unsigned int spd : 4;
839 /** Interface Power Management */
840 unsigned int ipm : 4;
841 /** Reserved. */
842 unsigned int reserved : 20;
843 };
844 uint32_t u32;
845} ahci_port_ssts_t;
846
847/** Device detection active status. */
848#define AHCI_PORT_SSTS_DET_ACTIVE 3
849
850/** AHCI Memory register Port x Serial ATA Control (SCR2: SControl). */
851typedef union {
852 struct {
853 /** Device Detection Initialization */
854 unsigned int det : 4;
855 /** Speed Allowed */
856 unsigned int spd : 4;
857 /** Interface Power Management Transitions Allowed */
858 unsigned int ipm : 4;
859 /** Reserved. */
860 unsigned int reserved : 20;
861 };
862 uint32_t u32;
863} ahci_port_sctl_t;
864
865/** AHCI Memory register Port x Port x Serial ATA Error (SCR1: SError). */
866typedef struct {
867 /** Error (ERR) - The ERR field contains error information for use
868 * by host software in determining the appropriate response to the
869 * error condition.
870 */
871 uint16_t err;
872 /** Diagnostics (DIAG) - Contains diagnostic error information for use
873 * by diagnostic software in validating correct operation or isolating
874 * failure modes.
875 */
876 uint16_t diag;
877} ahci_port_serr_t;
878
879/** AHCI Memory register Port x Serial ATA Active (SCR3: SActive). */
880typedef struct {
881 /** Device Status - Each bit corresponds to the TAG and
882 * command slot of a native queued command, where bit 0 corresponds
883 * to TAG 0 and command slot 0.
884 */
885 uint32_t u32;
886} ahci_port_sact_t;
887
888/** AHCI Memory register Port x Command Issue. */
889typedef struct {
890 /** Commands Issued - Each bit corresponds to a command slot,
891 * where bit 0 corresponds to command slot 0.
892 */
893 uint32_t u32;
894} ahci_port_ci_t;
895
896/** AHCI Memory register Port x Serial ATA Notification
897 * (SCR4: SNotification).
898 */
899typedef struct {
900 /** PM Notify (PMN): This field indicates whether a particular device with
901 * the corresponding PM Port number issued a Set Device Bits FIS
902 * to the host with the Notification bit set.
903 */
904 uint16_t pmn;
905 /** Reserved. */
906 uint16_t reserved;
907} ahci_port_sntf_t;
908
909/** AHCI Memory register Port x FIS-based Switching Control.
910 * This register is used to control and obtain status
911 * for Port Multiplier FIS-based switching.
912 */
913typedef union {
914 struct {
915 /** Enable */
916 unsigned int en : 1;
917 /** Device Error Clear */
918 unsigned int dec : 1;
919 /** Single Device Error */
920 unsigned int sde : 1;
921 /** Reserved. */
922 unsigned int reserved1 : 5;
923 /** Device To Issue */
924 unsigned int dev : 1;
925 /** Active Device Optimization */
926 unsigned int ado : 1;
927 /** Device With Error */
928 unsigned int dwe : 1;
929 /** Reserved. */
930 unsigned int reserved2 : 1;
931 };
932 uint32_t u32;
933} ahci_port_fbs_t;
934
935/** AHCI Memory register Port. */
936typedef volatile struct {
937 /** Port x Command List Base Address. */
938 uint32_t pxclb;
939 /** Port x Command List Base Address Upper 32-Bits. */
940 uint32_t pxclbu;
941 /** Port x FIS Base Address. */
942 uint32_t pxfb;
943 /** Port x FIS Base Address Upper 32-Bits. */
944 uint32_t pxfbu;
945 /** Port x Interrupt Status. */
946 ahci_port_is_t pxis;
947 /** Port x Interrupt Enable. */
948 uint32_t pxie;
949 /** Port x Command and Status. */
950 uint32_t pxcmd;
951 /** Reserved. */
952 uint32_t reserved1;
953 /** Port x Task File Data. */
954 uint32_t pxtfd;
955 /** Port x Signature. */
956 uint32_t pxsig;
957 /** Port x Serial ATA Status (SCR0: SStatus). */
958 uint32_t pxssts;
959 /** Port x Serial ATA Control (SCR2: SControl). */
960 uint32_t pxsctl;
961 /** Port x Serial ATA Error (SCR1: SError). */
962 uint32_t pxserr;
963 /** Port x Serial ATA Active (SCR3: SActive). */
964 uint32_t pxsact;
965 /** Port x Command Issue. */
966 uint32_t pxci;
967 /** Port x Serial ATA Notification (SCR4: SNotification). */
968 uint32_t pxsntf;
969 /** Port x FIS-based Switching Control. */
970 uint32_t pxfbs;
971 /** Reserved. */
972 uint32_t reserved2[11];
973 /** Port x Vendor Specific. */
974 uint32_t pxvs[4];
975} ahci_port_t;
976
977/** AHCI Memory Registers. */
978typedef volatile struct {
979 /** Generic Host Control. */
980 ahci_ghc_t ghc;
981 /** Reserved. */
982 uint32_t reserved[13];
983 /** Reserved for NVMHCI. */
984 uint32_t reservedfornvmhci[16];
985 /** Vendor Specific registers. */
986 uint32_t vendorspecificsregs[24];
987 /** Ports. */
988 ahci_port_t ports[AHCI_MAX_PORTS];
989} ahci_memregs_t;
990
991/** AHCI Command header entry.
992 *
993 * This structure is not an AHCI register.
994 *
995 */
996typedef volatile struct {
997 /** Flags. */
998 uint16_t flags;
999 /** Physical Region Descriptor Table Length. */
1000 uint16_t prdtl;
1001 /** Physical Region Descriptor Byte Count. */
1002 uint32_t bytesprocessed;
1003 /** Command Table Descriptor Base Address. */
1004 uint32_t cmdtable;
1005 /** Command Table Descriptor Base Address Upper 32-bits. */
1006 uint32_t cmdtableu;
1007} ahci_cmdhdr_t;
1008
1009/** Clear Busy upon R_OK (C) flag. */
1010#define AHCI_CMDHDR_FLAGS_CLEAR_BUSY_UPON_OK 0x0400
1011
1012/** Write operation flag. */
1013#define AHCI_CMDHDR_FLAGS_WRITE 0x0040
1014
1015/** 2 DW length command flag. */
1016#define AHCI_CMDHDR_FLAGS_2DWCMD 0x0002
1017
1018/** 5 DW length command flag. */
1019#define AHCI_CMDHDR_FLAGS_5DWCMD 0x0005
1020
1021/** AHCI Command Physical Region Descriptor entry.
1022 *
1023 * This structure is not an AHCI register.
1024 *
1025 */
1026typedef volatile struct {
1027 /** Word aligned 32-bit data base address. */
1028 uint32_t data_address_low;
1029 /** Upper data base address, valid only for 64-bit HBA addressing. */
1030 uint32_t data_address_upper;
1031 /** Reserved. */
1032 uint32_t reserved1;
1033 /** Data byte count */
1034 unsigned int dbc : 22;
1035 /** Reserved */
1036 unsigned int reserved2 : 9;
1037 /** Set Interrupt on each operation completion */
1038 unsigned int ioc : 1;
1039} ahci_cmd_prdt_t;
1040
1041#endif
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