source: mainline/uspace/drv/block/ahci/ahci_hw.h@ ae7d03c

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since ae7d03c was ae7d03c, checked in by Jiri Svoboda <jiri@…>, 7 years ago

Selected ccheck-proposed comment fixes.
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[9904eb90]1/*
2 * Copyright (c) 2012 Petr Jerman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Header for AHCI driver (AHCI 1.3 specification).
31 */
32
33#ifndef __AHCI_HW_H__
34#define __AHCI_HW_H__
35
[8d2dd7f2]36#include <stdint.h>
[9904eb90]37
[ae3ff9f5]38/*----------------------------------------------------------------------------*/
39/*-- AHCI standard constants -------------------------------------------------*/
40/*----------------------------------------------------------------------------*/
41
42/** AHCI standard 1.3 - maximum ports. */
43#define AHCI_MAX_PORTS 32
44
[9904eb90]45/*----------------------------------------------------------------------------*/
46/*-- AHCI PCI Registers ------------------------------------------------------*/
47/*----------------------------------------------------------------------------*/
48
49/** AHCI PCI register Identifiers offset. */
50#define AHCI_PCI_ID 0x00
51/** AHCI PCI register Command offset. */
52#define AHCI_PCI_CMD 0x04
53/** AHCI PCI register Device Status offset. */
54#define AHCI_PCI_STS 0x06
55/** AHCI PCI register Revision ID offset. */
56#define AHCI_PCI_RID 0x08
57/** AHCI PCI register Class Codes offset. */
58#define AHCI_PCI_CC 0x09
59/** AHCI PCI register Cache Line Size offset. */
60#define AHCI_PCI_CLS 0x0C
61/** AHCI PCI register Master Latency Timer offset. */
62#define AHCI_PCI_MLT 0x0D
63/** AHCI PCI register Header Type offset. */
64#define AHCI_PCI_HTYPE 0x0E
65/** AHCI PCI register Built In Self Test (Optional) offset. */
66#define AHCI_PCI_BIST 0x0F
67/** AHCI PCI register Other Base Address Registres (Optional). */
68#define AHCI_PCI_BAR0 0x10
69/** AHCI PCI register Other Base Address Registres (Optional). */
70#define AHCI_PCI_BAR1 0x14
71/** AHCI PCI register Other Base Address Registres (Optional). */
72#define AHCI_PCI_BAR2 0x18
73/** AHCI PCI register Other Base Address Registres (Optional). */
74#define AHCI_PCI_BAR3 0x1C
75/** AHCI PCI register Other Base Address Registres (Optional). */
76#define AHCI_PCI_BAR4 0x20
77/** AHCI PCI register AHCI Base Address offset. */
78#define AHCI_PCI_ABAR 0x24
79/** AHCI PCI register Subsystem Identifiers offset. */
80#define AHCI_PCI_SS 0x2C
81/** AHCI PCI register Expansion ROM Base Address (Optional) offset. */
82#define AHCI_PCI_EROM 0x30
83/** AHCI PCI register Capabilities Pointer offset. */
84#define AHCI_PCI_CAP 0x34
85/** AHCI PCI register Interrupt Information offset. */
86#define AHCI_PCI_INTR 0x3C
87/** AHCI PCI register Min Grant (Optional) offset. */
88#define AHCI_PCI_MGNT 0x3E
89/** AHCI PCI register Max Latency (Optional) offset. */
90#define AHCI_PCI_MLAT 0x3F
91
92/** AHCI PCI register Identifiers. */
93typedef struct {
94 /** Indicates the company vendor assigned by the PCI SIG. */
95 uint16_t vendorid;
96 /** Indicates what device number assigned by the vendor */
97 uint16_t deviceid;
[730dce77]98} ahci_pcireg_id_t;
[9904eb90]99
100/** AHCI PCI register Command. */
101typedef union {
102 struct {
103 /** I/O Space Enable. */
104 unsigned int iose : 1;
105 /** Memory Space Enable. */
106 unsigned int mse : 1;
107 /** Bus Master Enable. */
108 unsigned int bme : 1;
109 /** Special Cycle Enable. */
110 unsigned int sce : 1;
111 /** Memory Write and Invalidate Enable. */
112 unsigned int mwie : 1;
113 /** VGA Palette Snooping Enable. */
114 unsigned int vga : 1;
115 /** Parity Error Response Enable. */
116 unsigned int pee : 1;
117 /** Wait Cycle Enable. */
118 unsigned int wcc : 1;
119 /** SERR# Enable. */
120 unsigned int see : 1;
121 /** Fast Back-to-Back Enable. */
122 unsigned int fbe : 1;
123 /** Interrupt Disable - disables the HBA from generating interrupts.
124 * This bit does not have any effect on MSI operation.
125 */
126 unsigned int id : 1;
127 /** Reserved. */
128 unsigned int reserved : 5;
[730dce77]129 };
[9904eb90]130 uint16_t u16;
[730dce77]131} ahci_pcireg_cmd_t;
[9904eb90]132
133/** AHCI PCI register Command - Interrupt Disable bit. */
134#define AHCI_PCIREG_CMD_ID 0x0400
135
136/** AHCI PCI register Command - Bus Master Enable bit. */
137#define AHCI_PCIREG_CMD_BME 0x0004
138
139/** AHCI PCI register Device status. */
140typedef union {
141 struct {
142 /** Reserved. */
143 unsigned int reserved1 : 3;
144 /** Indicate the interrupt status of the device (1 = asserted). */
145 unsigned int is : 1;
146 /** Indicates presence of capatibility list. */
147 unsigned int cl : 1;
148 /** 66 Mhz capable. */
149 unsigned int c66 : 1;
150 /** Reserved. */
151 unsigned int reserved2 : 1;
152 /** Fast back to back capable. */
153 unsigned int fbc : 1;
154 /** Master data parity error detected. */
155 unsigned int dpd : 1;
156 /** Device select timing. */
157 unsigned int devt : 2;
158 /** Signaled target abort. */
159 unsigned int sta : 1;
160 /** Received target abort. */
161 unsigned int rta : 1;
162 /** Received master abort. */
163 unsigned int rma : 1;
164 /** Signaled system error. */
165 unsigned int sse : 1;
166 /** Detected parity error. */
167 unsigned int dpe : 1;
[730dce77]168 };
[9904eb90]169 uint16_t u16;
[730dce77]170} ahci_pcireg_sts_t;
[9904eb90]171
172/** AHCI PCI register Revision ID. */
173typedef struct {
174 /** Indicates stepping of the HBA hardware. */
175 uint8_t u8;
[730dce77]176} ahci_pcireg_rid_t;
[9904eb90]177
178/** AHCI PCI register Class Codes. */
179typedef struct {
180 /** Programing interface, when set to 01h and the scc is set to 06h,
181 * indicates that this an AHCI HBA major revision 1.
182 */
183 uint8_t pi;
184 /** When set to 06h, indicates that is a SATA device. */
185 uint8_t scc;
186 /** Value 01 indicates that is a mass storage device. */
187 uint8_t bcc;
[730dce77]188} ahci_pcireg_cc_t_t;
[9904eb90]189
190/** AHCI PCI register Cache Line Size. */
191typedef struct {
[730dce77]192 /** Cache line size for use with the memory write and invalidate command. */
[9904eb90]193 uint8_t u8;
[730dce77]194} ahci_pcireg_cls_t;
[9904eb90]195
196/** AHCI PCI register Master Latency Timer. */
197typedef struct {
198 /** Master latency timer,indicates the number of clocks the HBA is allowed
199 * to acts as master on PCI.
200 */
201 uint8_t u8;
[730dce77]202} ahci_pcireg_mlt_t;
[9904eb90]203
204/** AHCI PCI register Header Type. */
205typedef union {
206 struct {
[ae3ff9f5]207 /** Header layout. */
[9904eb90]208 unsigned int hl : 7;
[ae3ff9f5]209 /** Multi function device flag. */
[9904eb90]210 unsigned int mfd : 1;
[730dce77]211 };
[9904eb90]212 uint8_t u8;
[730dce77]213} ahci_pciregs_htype_t;
[9904eb90]214
215/** AHCI PCI register Built in self test. */
216typedef union {
217 struct {
[ae7d03c]218 /** Indicates the completion status of BIST
219 * non-zero value indicates a failure.
220 */
221 unsigned int cc : 4;
222 /** Reserved. */
223 unsigned int reserved : 2;
224 /** Software sets this bit to 1 to invoke BIST,
225 * the HBA clears this bit to 0 when BIST is complete.
226 */
227 unsigned int sb : 1;
228 /** BIST capable. */
229 unsigned int bc : 1;
[730dce77]230 };
[9904eb90]231 uint8_t u8;
[730dce77]232} ahci_pciregs_bist_t;
[9904eb90]233
234/** AHCI PCI register AHCI Base Address <BAR 5>. */
235typedef union {
236 struct {
237 /** Indicates a request for register memory space. */
238 unsigned int rte : 1;
239 /** Indicates the this range can be mapped anywhere in 32-bit address
240 * space.
241 */
242 unsigned int tp : 2;
243 /** Indicate that this range is not prefetchable. */
244 unsigned int pf : 1;
245 /** Reserved. */
246 unsigned int reserved : 9;
247 /** Base address of registry memory space. */
248 unsigned int ba : 19;
[730dce77]249 };
[9904eb90]250 uint32_t u32;
[730dce77]251} ahci_pciregs_abar_t;
[9904eb90]252
253/** AHCI PCI register Subsystem Identifiers. */
[ae7d03c]254typedef struct {
[9904eb90]255 /** Sub system vendor identifier. */
256 uint8_t ssvid;
257 /** Sub system identifier. */
258 uint8_t ssid;
[730dce77]259} ahci_pcireg_ss_t;
[9904eb90]260
261/** AHCI PCI registers Expansion ROM Base Address. */
[ae7d03c]262typedef struct {
[9904eb90]263 /** Indicates the base address of the HBA expansion ROM. */
264 uint32_t u32;
[730dce77]265} ahci_pcireg_erom_t;
[9904eb90]266
267/** AHCI PCI register Capabilities Pointer. */
[ae7d03c]268typedef struct {
[9904eb90]269 /** Indicates the first capability pointer offset. */
270 uint8_t u8;
[730dce77]271} ahci_pcireg_cap_t;
[9904eb90]272
273/** AHCI PCI register Interrupt Information. */
[ae7d03c]274typedef struct {
[9904eb90]275 /* Software written value to indicate which interrupt vector
276 * the interrupt is connected to.
277 */
278 uint8_t iline;
279 /** This indicates the interrupt pin the HBA uses. */
280 uint8_t ipin;
[730dce77]281} ahci_pcireg_intr;
[9904eb90]282
283/** AHCI PCI register Min Grant (Optional). */
[ae7d03c]284typedef struct {
[ae3ff9f5]285 /** Indicates the minimum grant time that the device
286 * wishes grant asserted.
[9904eb90]287 */
288 uint8_t u8;
[730dce77]289} ahci_pcireg_mgnt_t;
[9904eb90]290
291/** AHCI PCI register Max Latency (Optional). */
[ae7d03c]292typedef struct {
[9904eb90]293 /** Indicates the maximum latency that the device can withstand. */
294 uint8_t u8;
[730dce77]295} ahci_pcireg_mlat_t;
[9904eb90]296
297/*----------------------------------------------------------------------------*/
298/*-- AHCI Memory Registers ---------------------------------------------------*/
299/*----------------------------------------------------------------------------*/
300
[ae3ff9f5]301/** Number of pages for ahci memory registers. */
302#define AHCI_MEMREGS_PAGES_COUNT 8
303
[9904eb90]304/** AHCI Memory register Generic Host Control - HBA Capabilities. */
305typedef union {
306 struct {
307 /** Number of Ports. */
308 unsigned int np : 5;
309 /** Supports External SATA. */
310 unsigned int sxs : 1;
311 /** Enclosure Management Supported. */
312 unsigned int ems : 1;
313 /** Command Completion Coalescing Supported. */
314 unsigned int cccs : 1;
315 /** Number of Command Slots. */
316 unsigned int ncs : 5;
317 /** Partial State Capable. */
318 unsigned int psc : 1;
319 /** Slumber State Capable. */
320 unsigned int ssc : 1;
321 /** PIO Multiple DRQ Block. */
322 unsigned int pmd : 1;
323 /** FIS-based Switching Supported. */
324 unsigned int fbss : 1;
325 /** Supports Port Multiplier. */
326 unsigned int spm : 1;
327 /** Supports AHCI mode only. */
328 unsigned int sam : 1;
329 /** Reserved. */
330 unsigned int reserved : 1;
331 /** Interface Speed Support. */
332 unsigned int iss : 4;
333 /** Supports Command List Override. */
334 unsigned int sclo : 1;
335 /** Supports Activity LED. */
336 unsigned int sal : 1;
337 /** Supports Aggressive Link Power Management. */
338 unsigned int salp : 1;
339 /** Supports Staggered Spin-up. */
340 unsigned int sss : 1;
341 /** Supports Mechanical Presence Switch. */
342 unsigned int smps : 1;
343 /** Supports SNotification Register. */
344 unsigned int ssntf : 1;
345 /** Supports Native Command Queuing. */
346 unsigned int sncq : 1;
347 /** Supports 64-bit Addressing. */
348 unsigned int s64a : 1;
[730dce77]349 };
[9904eb90]350 uint32_t u32;
[730dce77]351} ahci_ghc_cap_t;
[9904eb90]352
353/** AHCI Memory register Generic Host Control Global Host Control. */
354typedef union {
355 struct {
356 /** HBA Reset. */
357 unsigned int hr : 1;
358 /** Interrupt Enable. */
359 unsigned int ie : 1;
360 /** MSI Revert to Single Message. */
361 unsigned int mrsm : 1;
362 /** Reserved. */
363 unsigned int reserved : 28;
364 /** AHCI Enable. */
365 unsigned int ae : 1;
[730dce77]366 };
[9904eb90]367 uint32_t u32;
[730dce77]368} ahci_ghc_ghc_t;
[9904eb90]369
370/** AHCI Enable mask bit. */
371#define AHCI_GHC_GHC_AE 0x80000000
372
373/** AHCI Interrupt Enable mask bit. */
374#define AHCI_GHC_GHC_IE 0x00000002
375
376/** AHCI Memory register Interrupt pending register. */
[eb3683a]377typedef uint32_t ahci_ghc_is_t;
[9904eb90]378
[ae3ff9f5]379/** AHCI GHC register offset. */
[eb3683a]380#define AHCI_GHC_IS_REGISTER_OFFSET 2
381
382/** AHCI ports registers offset. */
383#define AHCI_PORTS_REGISTERS_OFFSET 64
384
385/** AHCI port registers size. */
386#define AHCI_PORT_REGISTERS_SIZE 32
387
388/** AHCI port IS register offset. */
389#define AHCI_PORT_IS_REGISTER_OFFSET 4
[ae3ff9f5]390
[9904eb90]391/** AHCI Memory register Ports implemented. */
392typedef struct {
393 /** If a bit is set to 1, the corresponding port
394 * is available for software use.
395 */
396 uint32_t u32;
[730dce77]397} ahci_ghc_pi_t;
[9904eb90]398
399/** AHCI Memory register AHCI version. */
400typedef struct {
401 /** Indicates the minor version */
402 uint16_t mnr;
403 /** Indicates the major version */
404 uint16_t mjr;
[730dce77]405} ahci_ghc_vs_t;
[9904eb90]406
407/** AHCI Memory register Command completion coalesce control. */
408typedef union {
409 struct {
410 /** Enable CCC features. */
411 unsigned int en : 1;
412 /** Reserved. */
413 unsigned int reserved : 2;
414 /** Interrupt number for CCC. */
415 unsigned int intr : 5;
416 /** Number of command completions that are necessary to cause
417 * a CCC interrupt.
418 */
419 uint8_t cc;
420 /** Timeout value in ms. */
421 uint16_t tv;
[730dce77]422 };
[9904eb90]423 uint32_t u32;
[730dce77]424} ahci_ghc_ccc_ctl_t;
[9904eb90]425
426/** AHCI Memory register Command completion coalescing ports. */
[ae7d03c]427typedef struct {
[9904eb90]428 /** If a bit is set to 1, the corresponding port is
429 * part of the command completion coalescing feature.
430 */
431 uint32_t u32;
[730dce77]432} ahci_ghc_ccc_ports_t;
[9904eb90]433
434/** AHCI Memory register Enclosure management location. */
[ae7d03c]435typedef struct {
[9904eb90]436 /** Size of the transmit message buffer area in dwords. */
437 uint16_t sz;
[ae3ff9f5]438 /*
439 * Offset of the transmit message buffer area in dwords
[9904eb90]440 * from the beginning of ABAR
441 */
442 uint16_t ofst;
[730dce77]443} ahci_ghc_em_loc;
[9904eb90]444
445/** AHCI Memory register Enclosure management control. */
446typedef union {
447 struct {
448 /** Message received. */
449 unsigned int mr : 1;
450 /** Reserved. */
451 unsigned int reserved : 7;
452 /** Transmit message. */
453 unsigned int tm : 1;
454 /** Reset. */
455 unsigned int rst : 1;
456 /** Reserved. */
457 unsigned int reserved2 : 6;
458 /** LED message types. */
459 unsigned int led : 1;
460 /** Support SAFT-TE message type. */
461 unsigned int safte : 1;
462 /** Support SES-2 message type. */
463 unsigned int ses2 : 1;
464 /** Support SGPIO register. */
465 unsigned int sgpio : 1;
466 /** Reserved. */
467 unsigned int reserved3 : 4;
468 /** Single message buffer. */
469 unsigned int smb : 1;
470 /** Support transmitting only. */
471 unsigned int xmt : 1;
472 /** Activity LED hardware driven. */
473 unsigned int alhd : 1;
[ae3ff9f5]474 /** Port multiplier support. */
[9904eb90]475 unsigned int pm : 1;
476 /** Reserved. */
477 unsigned int reserved4 : 4;
[730dce77]478 };
[9904eb90]479 uint32_t u32;
[730dce77]480} ahci_ghc_em_ctl_t;
[9904eb90]481
482/** AHCI Memory register HBA capatibilities extended. */
483typedef union {
484 struct {
485 /** HBA support BIOS/OS handoff mechanism,
486 * implemented BOHC register.
487 */
488 unsigned int boh : 1;
489 /** Support for NVMHCI register. */
490 unsigned int nvmp : 1;
491 /** Automatic partial to slumber transition support. */
492 unsigned int apst : 1;
493 /** Reserved. */
494 unsigned int reserved : 29;
[730dce77]495 };
[9904eb90]496 uint32_t u32;
[730dce77]497} ahci_ghc_cap2_t;
[9904eb90]498
499/** AHCI Memory register BIOS/OS Handoff control and status. */
500typedef union {
501 struct {
502 /** BIOS Owned semaphore. */
503 unsigned int bos : 1;
504 /** OS Owned semaphore. */
505 unsigned int oos : 1;
506 /** SMI on OS ownership change enable. */
507 unsigned int sooe : 1;
508 /** OS ownership change. */
509 unsigned int ooc : 1;
510 /** BIOS Busy. */
511 unsigned int bb : 1;
512 /** Reserved. */
513 unsigned int reserved : 27;
[730dce77]514 };
[9904eb90]515 uint32_t u32;
[730dce77]516} ahci_ghc_bohc_t;
[9904eb90]517
518/** AHCI Memory register Generic Host Control. */
[ae7d03c]519typedef struct {
[ae3ff9f5]520 /** Host Capabilities */
[9904eb90]521 uint32_t cap;
[ae3ff9f5]522 /** Global Host Control */
[9904eb90]523 uint32_t ghc;
[ae3ff9f5]524 /** Interrupt Status */
[eb3683a]525 ahci_ghc_is_t is;
[ae3ff9f5]526 /** Ports Implemented */
[9904eb90]527 uint32_t pi;
[ae3ff9f5]528 /** Version */
[9904eb90]529 uint32_t vs;
[ae3ff9f5]530 /** Command Completion Coalescing Control */
[9904eb90]531 uint32_t ccc_ctl;
[ae3ff9f5]532 /** Command Completion Coalescing Ports */
[9904eb90]533 uint32_t ccc_ports;
[ae3ff9f5]534 /** Enclosure Management Location */
[9904eb90]535 uint32_t em_loc;
[ae3ff9f5]536 /** Enclosure Management Control */
[9904eb90]537 uint32_t em_ctl;
[ae3ff9f5]538 /** Host Capabilities Extended */
[9904eb90]539 uint32_t cap2;
[ae3ff9f5]540 /** BIOS/OS Handoff Control and Status */
[9904eb90]541 uint32_t bohc;
[730dce77]542} ahci_ghc_t;
[9904eb90]543
544/** AHCI Memory register Port x Command List Base Address. */
545typedef union {
546 struct {
547 /** Reserved. */
548 unsigned int reserved : 10;
549 /** Command List Base Address (CLB) - Indicates the 32-bit base physical
550 * address for the command list for this port. This base is used when
551 * fetching commands to execute. The structure pointed to by this
552 * address range is 1K-bytes in length. This address must be 1K-byte
553 * aligned as indicated by bits 09:00 being read only.
554 */
555 unsigned int clb : 22;
[730dce77]556 };
[9904eb90]557 uint32_t u32;
[730dce77]558} ahci_port_clb_t;
[9904eb90]559
560/** AHCI Memory register Port x Command List Base Address Upper 32-Bits. */
561typedef struct {
562 /** Command List Base Address Upper (CLBU): Indicates the upper 32-bits
563 * for the command list base physical address for this port. This base
564 * is used when fetching commands to execute. This register shall
565 * be read only for HBAs that do not support 64-bit addressing.
566 */
567 uint32_t u32;
[730dce77]568} ahci_port_clbu_t;
[9904eb90]569
570/** AHCI Memory register Port x FIS Base Address. */
571typedef union {
572 struct {
573 /** Reserved. */
[730dce77]574 unsigned int reserved : 8;
[9904eb90]575 /** FIS Base Address (FB) - Indicates the 32-bit base physical address
576 * for received FISes. The structure pointed to by this address range
577 * is 256 bytes in length. This address must be 256-byte aligned as
578 * indicated by bits 07:00 being read only. When FIS-based switching
579 * is in use, this structure is 4KB in length and the address shall be
580 * 4KB aligned.
581 */
582 unsigned int fb : 24;
[730dce77]583 };
[9904eb90]584 uint32_t u32;
[730dce77]585} ahci_port_fb_t;
[9904eb90]586
587/** AHCI Memory register Port x FIS Base Address Upper 32-Bits. */
588typedef struct {
589 /** FIS Base Address Upper (FBU) - Indicates the upper 32-bits
590 * for the received FIS base physical address for this port. This register
591 * shall be read only for HBAs that do not support 64-bit addressing.
592 */
593 uint32_t u32;
[730dce77]594} ahci_port_fbu_t;
[9904eb90]595
596/** AHCI Memory register Port x Interrupt Status. */
[eb3683a]597typedef uint32_t ahci_port_is_t;
[9904eb90]598
599#define AHCI_PORT_IS_DHRS (1 << 0)
600#define AHCI_PORT_IS_PSS (1 << 1)
601#define AHCI_PORT_IS_DSS (1 << 2)
602#define AHCI_PORT_IS_SDBS (1 << 3)
603#define AHCI_PORT_IS_UFS (1 << 4)
604#define AHCI_PORT_IS_DPS (1 << 5)
605#define AHCI_PORT_IS_PCS (1 << 6)
606#define AHCI_PORT_IS_DMPS (1 << 7)
607
608#define AHCI_PORT_IS_PRCS (1 << 22)
609#define AHCI_PORT_IS_IPMS (1 << 23)
610#define AHCI_PORT_IS_OFS (1 << 24)
611#define AHCI_PORT_IS_INFS (1 << 26)
612#define AHCI_PORT_IS_IFS (1 << 27)
613#define AHCI_PORT_IS_HDBS (1 << 28)
614#define AHCI_PORT_IS_HBFS (1 << 29)
615#define AHCI_PORT_IS_TFES (1 << 30)
616#define AHCI_PORT_IS_CPDS (1 << 31)
617
618#define AHCI_PORT_END_OF_OPERATION \
619 (AHCI_PORT_IS_DHRS | \
620 AHCI_PORT_IS_SDBS )
621
622#define AHCI_PORT_IS_ERROR \
623 (AHCI_PORT_IS_UFS | \
624 AHCI_PORT_IS_PCS | \
625 AHCI_PORT_IS_DMPS | \
626 AHCI_PORT_IS_PRCS | \
627 AHCI_PORT_IS_IPMS | \
628 AHCI_PORT_IS_OFS | \
629 AHCI_PORT_IS_INFS | \
630 AHCI_PORT_IS_IFS | \
631 AHCI_PORT_IS_HDBS | \
632 AHCI_PORT_IS_HBFS | \
633 AHCI_PORT_IS_TFES | \
634 AHCI_PORT_IS_CPDS)
635
636#define AHCI_PORT_IS_PERMANENT_ERROR \
637 (AHCI_PORT_IS_PCS | \
638 AHCI_PORT_IS_DMPS | \
639 AHCI_PORT_IS_PRCS | \
640 AHCI_PORT_IS_IPMS | \
641 AHCI_PORT_IS_CPDS )
642
643/** Evaluate end of operation status from port interrupt status.
644 *
645 * @param port_is Value of port interrupt status.
646 *
647 * @return Indicate end of operation status.
648 *
649 */
650static inline int ahci_port_is_end_of_operation(ahci_port_is_t port_is)
651{
[eb3683a]652 return port_is & AHCI_PORT_END_OF_OPERATION;
[9904eb90]653}
654
655/** Evaluate error status from port interrupt status.
656 *
657 * @param port_is Value of port interrupt status.
658 *
659 * @return Indicate error status.
660 *
661 */
662static inline int ahci_port_is_error(ahci_port_is_t port_is)
663{
[eb3683a]664 return port_is & AHCI_PORT_IS_ERROR;
[9904eb90]665}
666
667/** Evaluate permanent error status from port interrupt status.
668 *
669 * @param port_is Value of port interrupt status.
670 *
671 * @return Indicate permanent error status.
672 *
673 */
674static inline int ahci_port_is_permanent_error(ahci_port_is_t port_is)
675{
[eb3683a]676 return port_is & AHCI_PORT_IS_PERMANENT_ERROR;
[9904eb90]677}
678
679/** Evaluate task file error status from port interrupt status.
680 *
681 * @param port_is Value of port interrupt status.
682 *
683 * @return Indicate error status.
684 *
685 */
686static inline int ahci_port_is_tfes(ahci_port_is_t port_is)
687{
[eb3683a]688 return port_is & AHCI_PORT_IS_TFES;
[9904eb90]689}
690
691/** AHCI Memory register Port x Interrupt Enable. */
692typedef union {
693 struct {
694 /** Device to Host Register FIS Interrupt Enable. */
695 unsigned int dhre : 1;
696 /** PIO Setup FIS Interrupt Enable. */
697 unsigned int pse : 1;
698 /** DMA Setup FIS Interrupt Enable. */
699 unsigned int dse : 1;
700 /** Set Device Bits Interrupt Eenable. */
701 unsigned int sdbe : 1;
702 /** Unknown FIS Interrupt Enable. */
703 unsigned int ufe : 1;
704 /** Descriptor Processed Interrupt Enable. */
705 unsigned int dpe : 1;
706 /** Port Change Interrupt Enable. */
707 unsigned int pce : 1;
708 /** Device Mechanical Presence Enable. */
709 unsigned int dmpe : 1;
710 /** Reserved. */
711 unsigned int reserved1 : 14;
712 /** PhyRdy Change Interrupt Enable. */
713 unsigned int prce : 1;
714 /** Incorrect Port Multiplier Enable. */
715 unsigned int ipme : 1;
716 /** Overflow Status Enable. */
717 unsigned int ofe : 1;
718 /** Reserved. */
719 unsigned int reserved2 : 1;
720 /** Interface Non-fatal Error Enable. */
721 unsigned int infe : 1;
722 /** Interface Fatal Error Enable. */
723 unsigned int ife : 1;
724 /** Host Bus Data Error Enable. */
725 unsigned int hbde : 1;
726 /** Host Bus Fatal Error Enable. */
727 unsigned int hbfe : 1;
728 /** Task File Error Enable. */
729 unsigned int tfee : 1;
730 /** Cold Port Detect Enable. */
731 unsigned int cpde : 1;
[730dce77]732 };
[9904eb90]733 uint32_t u32;
[730dce77]734} ahci_port_ie_t;
[9904eb90]735
736/** AHCI Memory register Port x Command and Status. */
737typedef union {
738 struct {
739 /** Start - when set, the HBA may process the command list. */
740 unsigned int st : 1;
741 /** Spin-Up Device. */
742 unsigned int sud : 1;
743 /** Power On Device. */
744 unsigned int pod : 1;
745 /** Command List Override. */
746 unsigned int clo : 1;
747 /** FIS Receive Enable. */
748 unsigned int fre : 1;
749 /** Reserved. */
750 unsigned int reserved : 3;
751 /** Current Command Slot. */
752 unsigned int ccs : 5;
753 /** Mechanical Presence Switch State. */
754 unsigned int mpss : 1;
755 /** FIS Receive Running. */
756 unsigned int fr : 1;
757 /** Command List Running. */
758 unsigned int cr : 1;
759 /** Cold Presence State. */
760 unsigned int cps : 1;
761 /** Port Multiplier Attached. */
762 unsigned int pma : 1;
763 /** Hot Plug Capable Port. */
764 unsigned int hpcp : 1;
765 /** Mechanical Presence Switch Attached to Port. */
766 unsigned int mpsp : 1;
767 /** Cold Presence Detection. */
768 unsigned int cpd : 1;
769 /** External SATA Port. */
770 unsigned int esp : 1;
771 /** FIS-based Switching Capable Port. */
772 unsigned int fbscp : 1;
773 /** Automatic Partial to Slumber Transitions Enabled. */
774 unsigned int apste : 1;
775 /** Device is ATAPI. */
776 unsigned int atapi : 1;
777 /** Drive LED on ATAPI Enable. */
778 unsigned int dlae : 1;
779 /** Aggressive Link Power Management Enable. */
780 unsigned int alpe : 1;
781 /** Aggressive Slumber / Partial. */
782 unsigned int asp : 1;
783 /** Interface Communication Control.
784 * Values:
785 * 7h - fh Reserved,
[ae3ff9f5]786 * 6h Slumber - This shall cause the HBA to request a transition
787 * of the interface to the Slumber state,
[9904eb90]788 * 3h - 5h Reserved,
[ae3ff9f5]789 * 2h Partial - This shall cause the HBA to request a transition
790 * of the interface to the Partial state,
[9904eb90]791 * 1h Active,
792 * 0h No-Op / Idle.
793 */
794 unsigned int icc : 4;
[730dce77]795 };
[9904eb90]796 uint32_t u32;
[730dce77]797} ahci_port_cmd_t;
[9904eb90]798
799/** AHCI Memory register Port x Task File Data. */
800typedef union {
801 struct {
802 /** Status (STS): Contains the latest copy of the task file
803 * status register.
804 */
805 uint8_t sts;
806 /** Error (ERR) - Contains the latest copy of the task file
807 * error register.
808 */
809 uint8_t err;
810 /** Reserved. */
811 uint16_t reserved;
[730dce77]812 };
[9904eb90]813 uint32_t u32;
[730dce77]814} ahci_port_tfd_t;
[9904eb90]815
816/** AHCI Memory register Port x Signature. */
817typedef union {
818 struct {
819 /** Sector Count Register */
820 uint8_t sector_count;
821 /** LBA Low Register */
822 uint8_t lba_lr;
823 /** LBA Mid Register */
824 uint8_t lba_mr;
[ae3ff9f5]825 /** LBA High Register */
[9904eb90]826 uint8_t lba_hr;
[730dce77]827 };
[9904eb90]828 uint32_t u32;
[730dce77]829} ahci_port_sig_t;
[9904eb90]830
831/** AHCI Memory register Port x Serial ATA Status (SCR0: SStatus). */
832typedef union {
833 struct {
834 /** Device Detection */
835 unsigned int det : 4;
836 /** Current Interface Speed */
837 unsigned int spd : 4;
838 /** Interface Power Management */
839 unsigned int ipm : 4;
840 /** Reserved. */
841 unsigned int reserved : 20;
[730dce77]842 };
[9904eb90]843 uint32_t u32;
[730dce77]844} ahci_port_ssts_t;
[9904eb90]845
[ae3ff9f5]846/** Device detection active status. */
847#define AHCI_PORT_SSTS_DET_ACTIVE 3
848
[9904eb90]849/** AHCI Memory register Port x Serial ATA Control (SCR2: SControl). */
850typedef union {
851 struct {
852 /** Device Detection Initialization */
853 unsigned int det : 4;
854 /** Speed Allowed */
855 unsigned int spd : 4;
856 /** Interface Power Management Transitions Allowed */
857 unsigned int ipm : 4;
858 /** Reserved. */
859 unsigned int reserved : 20;
[730dce77]860 };
[9904eb90]861 uint32_t u32;
[730dce77]862} ahci_port_sctl_t;
[9904eb90]863
864/** AHCI Memory register Port x Port x Serial ATA Error (SCR1: SError). */
865typedef struct {
866 /** Error (ERR) - The ERR field contains error information for use
867 * by host software in determining the appropriate response to the
868 * error condition.
869 */
870 uint16_t err;
871 /** Diagnostics (DIAG) - Contains diagnostic error information for use
872 * by diagnostic software in validating correct operation or isolating
873 * failure modes.
874 */
875 uint16_t diag;
[730dce77]876} ahci_port_serr_t;
[9904eb90]877
878/** AHCI Memory register Port x Serial ATA Active (SCR3: SActive). */
879typedef struct {
880 /** Device Status - Each bit corresponds to the TAG and
881 * command slot of a native queued command, where bit 0 corresponds
882 * to TAG 0 and command slot 0.
883 */
884 uint32_t u32;
[730dce77]885} ahci_port_sact_t;
[9904eb90]886
887/** AHCI Memory register Port x Command Issue. */
888typedef struct {
889 /** Commands Issued - Each bit corresponds to a command slot,
890 * where bit 0 corresponds to command slot 0.
891 */
892 uint32_t u32;
[730dce77]893} ahci_port_ci_t;
[9904eb90]894
895/** AHCI Memory register Port x Serial ATA Notification
896 * (SCR4: SNotification).
897 */
898typedef struct {
899 /** PM Notify (PMN): This field indicates whether a particular device with
900 * the corresponding PM Port number issued a Set Device Bits FIS
901 * to the host with the Notification bit set.
902 */
903 uint16_t pmn;
904 /** Reserved. */
905 uint16_t reserved;
[730dce77]906} ahci_port_sntf_t;
[9904eb90]907
908/** AHCI Memory register Port x FIS-based Switching Control.
909 * This register is used to control and obtain status
910 * for Port Multiplier FIS-based switching.
911 */
912typedef union {
913 struct {
914 /** Enable */
915 unsigned int en : 1;
916 /** Device Error Clear */
917 unsigned int dec : 1;
918 /** Single Device Error */
919 unsigned int sde : 1;
920 /** Reserved. */
921 unsigned int reserved1 : 5;
922 /** Device To Issue */
923 unsigned int dev : 1;
924 /** Active Device Optimization */
925 unsigned int ado : 1;
926 /** Device With Error */
927 unsigned int dwe : 1;
928 /** Reserved. */
929 unsigned int reserved2 : 1;
[730dce77]930 };
[9904eb90]931 uint32_t u32;
[730dce77]932} ahci_port_fbs_t;
[9904eb90]933
934/** AHCI Memory register Port. */
[ae7d03c]935typedef volatile struct {
[9904eb90]936 /** Port x Command List Base Address. */
937 uint32_t pxclb;
938 /** Port x Command List Base Address Upper 32-Bits. */
939 uint32_t pxclbu;
940 /** Port x FIS Base Address. */
941 uint32_t pxfb;
942 /** Port x FIS Base Address Upper 32-Bits. */
943 uint32_t pxfbu;
944 /** Port x Interrupt Status. */
[eb3683a]945 ahci_port_is_t pxis;
[9904eb90]946 /** Port x Interrupt Enable. */
947 uint32_t pxie;
948 /** Port x Command and Status. */
949 uint32_t pxcmd;
950 /** Reserved. */
951 uint32_t reserved1;
952 /** Port x Task File Data. */
953 uint32_t pxtfd;
954 /** Port x Signature. */
955 uint32_t pxsig;
956 /** Port x Serial ATA Status (SCR0: SStatus). */
957 uint32_t pxssts;
958 /** Port x Serial ATA Control (SCR2: SControl). */
959 uint32_t pxsctl;
960 /** Port x Serial ATA Error (SCR1: SError). */
961 uint32_t pxserr;
962 /** Port x Serial ATA Active (SCR3: SActive). */
963 uint32_t pxsact;
964 /** Port x Command Issue. */
965 uint32_t pxci;
966 /** Port x Serial ATA Notification (SCR4: SNotification). */
967 uint32_t pxsntf;
968 /** Port x FIS-based Switching Control. */
969 uint32_t pxfbs;
970 /** Reserved. */
971 uint32_t reserved2[11];
972 /** Port x Vendor Specific. */
973 uint32_t pxvs[4];
[730dce77]974} ahci_port_t;
[9904eb90]975
976/** AHCI Memory Registers. */
977typedef volatile struct {
978 /** Generic Host Control. */
979 ahci_ghc_t ghc;
980 /** Reserved. */
[eb3683a]981 uint32_t reserved[13];
[9904eb90]982 /** Reserved for NVMHCI. */
[ae3ff9f5]983 uint32_t reservedfornvmhci[16];
[9904eb90]984 /** Vendor Specific registers. */
[ae3ff9f5]985 uint32_t vendorspecificsregs[24];
[9904eb90]986 /** Ports. */
[eb3683a]987 ahci_port_t ports[AHCI_MAX_PORTS];
[730dce77]988} ahci_memregs_t;
[9904eb90]989
[ae3ff9f5]990/** AHCI Command header entry.
991 *
992 * This structure is not an AHCI register.
993 *
994 */
[9904eb90]995typedef volatile struct {
996 /** Flags. */
997 uint16_t flags;
998 /** Physical Region Descriptor Table Length. */
999 uint16_t prdtl;
1000 /** Physical Region Descriptor Byte Count. */
1001 uint32_t bytesprocessed;
[ae7d03c]1002 /** Command Table Descriptor Base Address. */
[9904eb90]1003 uint32_t cmdtable;
1004 /** Command Table Descriptor Base Address Upper 32-bits. */
1005 uint32_t cmdtableu;
[730dce77]1006} ahci_cmdhdr_t;
[9904eb90]1007
[ae3ff9f5]1008/** Clear Busy upon R_OK (C) flag. */
1009#define AHCI_CMDHDR_FLAGS_CLEAR_BUSY_UPON_OK 0x0400
1010
1011/** Write operation flag. */
1012#define AHCI_CMDHDR_FLAGS_WRITE 0x0040
1013
1014/** 2 DW length command flag. */
1015#define AHCI_CMDHDR_FLAGS_2DWCMD 0x0002
1016
1017/** 5 DW length command flag. */
1018#define AHCI_CMDHDR_FLAGS_5DWCMD 0x0005
1019
1020/** AHCI Command Physical Region Descriptor entry.
1021 *
1022 * This structure is not an AHCI register.
1023 *
1024 */
[9904eb90]1025typedef volatile struct {
1026 /** Word aligned 32-bit data base address. */
1027 uint32_t data_address_low;
1028 /** Upper data base address, valid only for 64-bit HBA addressing. */
1029 uint32_t data_address_upper;
1030 /** Reserved. */
1031 uint32_t reserved1;
1032 /** Data byte count */
1033 unsigned int dbc : 22;
1034 /** Reserved */
1035 unsigned int reserved2 : 9;
[ae3ff9f5]1036 /** Set Interrupt on each operation completion */
[9904eb90]1037 unsigned int ioc : 1;
[730dce77]1038} ahci_cmd_prdt_t;
[9904eb90]1039
1040#endif
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