source: mainline/uspace/drv/block/ahci/ahci_hw.h@ 7dddd7b

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 7dddd7b was 8d2dd7f2, checked in by Jakub Jermar <jakub@…>, 8 years ago

Reduce the number of files that include <sys/types.h>
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[9904eb90]1/*
2 * Copyright (c) 2012 Petr Jerman
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Header for AHCI driver (AHCI 1.3 specification).
31 */
32
33#ifndef __AHCI_HW_H__
34#define __AHCI_HW_H__
35
[8d2dd7f2]36#include <stdint.h>
[9904eb90]37
[ae3ff9f5]38/*----------------------------------------------------------------------------*/
39/*-- AHCI standard constants -------------------------------------------------*/
40/*----------------------------------------------------------------------------*/
41
42/** AHCI standard 1.3 - maximum ports. */
43#define AHCI_MAX_PORTS 32
44
[9904eb90]45/*----------------------------------------------------------------------------*/
46/*-- AHCI PCI Registers ------------------------------------------------------*/
47/*----------------------------------------------------------------------------*/
48
49/** AHCI PCI register Identifiers offset. */
50#define AHCI_PCI_ID 0x00
51/** AHCI PCI register Command offset. */
52#define AHCI_PCI_CMD 0x04
53/** AHCI PCI register Device Status offset. */
54#define AHCI_PCI_STS 0x06
55/** AHCI PCI register Revision ID offset. */
56#define AHCI_PCI_RID 0x08
57/** AHCI PCI register Class Codes offset. */
58#define AHCI_PCI_CC 0x09
59/** AHCI PCI register Cache Line Size offset. */
60#define AHCI_PCI_CLS 0x0C
61/** AHCI PCI register Master Latency Timer offset. */
62#define AHCI_PCI_MLT 0x0D
63/** AHCI PCI register Header Type offset. */
64#define AHCI_PCI_HTYPE 0x0E
65/** AHCI PCI register Built In Self Test (Optional) offset. */
66#define AHCI_PCI_BIST 0x0F
67/** AHCI PCI register Other Base Address Registres (Optional). */
68#define AHCI_PCI_BAR0 0x10
69/** AHCI PCI register Other Base Address Registres (Optional). */
70#define AHCI_PCI_BAR1 0x14
71/** AHCI PCI register Other Base Address Registres (Optional). */
72#define AHCI_PCI_BAR2 0x18
73/** AHCI PCI register Other Base Address Registres (Optional). */
74#define AHCI_PCI_BAR3 0x1C
75/** AHCI PCI register Other Base Address Registres (Optional). */
76#define AHCI_PCI_BAR4 0x20
77/** AHCI PCI register AHCI Base Address offset. */
78#define AHCI_PCI_ABAR 0x24
79/** AHCI PCI register Subsystem Identifiers offset. */
80#define AHCI_PCI_SS 0x2C
81/** AHCI PCI register Expansion ROM Base Address (Optional) offset. */
82#define AHCI_PCI_EROM 0x30
83/** AHCI PCI register Capabilities Pointer offset. */
84#define AHCI_PCI_CAP 0x34
85/** AHCI PCI register Interrupt Information offset. */
86#define AHCI_PCI_INTR 0x3C
87/** AHCI PCI register Min Grant (Optional) offset. */
88#define AHCI_PCI_MGNT 0x3E
89/** AHCI PCI register Max Latency (Optional) offset. */
90#define AHCI_PCI_MLAT 0x3F
91
92/** AHCI PCI register Identifiers. */
93typedef struct {
94 /** Indicates the company vendor assigned by the PCI SIG. */
95 uint16_t vendorid;
96 /** Indicates what device number assigned by the vendor */
97 uint16_t deviceid;
[730dce77]98} ahci_pcireg_id_t;
[9904eb90]99
100/** AHCI PCI register Command. */
101typedef union {
102 struct {
103 /** I/O Space Enable. */
104 unsigned int iose : 1;
105 /** Memory Space Enable. */
106 unsigned int mse : 1;
107 /** Bus Master Enable. */
108 unsigned int bme : 1;
109 /** Special Cycle Enable. */
110 unsigned int sce : 1;
111 /** Memory Write and Invalidate Enable. */
112 unsigned int mwie : 1;
113 /** VGA Palette Snooping Enable. */
114 unsigned int vga : 1;
115 /** Parity Error Response Enable. */
116 unsigned int pee : 1;
117 /** Wait Cycle Enable. */
118 unsigned int wcc : 1;
119 /** SERR# Enable. */
120 unsigned int see : 1;
121 /** Fast Back-to-Back Enable. */
122 unsigned int fbe : 1;
123 /** Interrupt Disable - disables the HBA from generating interrupts.
124 * This bit does not have any effect on MSI operation.
125 */
126 unsigned int id : 1;
127 /** Reserved. */
128 unsigned int reserved : 5;
[730dce77]129 };
[9904eb90]130 uint16_t u16;
[730dce77]131} ahci_pcireg_cmd_t;
[9904eb90]132
133/** AHCI PCI register Command - Interrupt Disable bit. */
134#define AHCI_PCIREG_CMD_ID 0x0400
135
136/** AHCI PCI register Command - Bus Master Enable bit. */
137#define AHCI_PCIREG_CMD_BME 0x0004
138
139/** AHCI PCI register Device status. */
140typedef union {
141 struct {
142 /** Reserved. */
143 unsigned int reserved1 : 3;
144 /** Indicate the interrupt status of the device (1 = asserted). */
145 unsigned int is : 1;
146 /** Indicates presence of capatibility list. */
147 unsigned int cl : 1;
148 /** 66 Mhz capable. */
149 unsigned int c66 : 1;
150 /** Reserved. */
151 unsigned int reserved2 : 1;
152 /** Fast back to back capable. */
153 unsigned int fbc : 1;
154 /** Master data parity error detected. */
155 unsigned int dpd : 1;
156 /** Device select timing. */
157 unsigned int devt : 2;
158 /** Signaled target abort. */
159 unsigned int sta : 1;
160 /** Received target abort. */
161 unsigned int rta : 1;
162 /** Received master abort. */
163 unsigned int rma : 1;
164 /** Signaled system error. */
165 unsigned int sse : 1;
166 /** Detected parity error. */
167 unsigned int dpe : 1;
[730dce77]168 };
[9904eb90]169 uint16_t u16;
[730dce77]170} ahci_pcireg_sts_t;
[9904eb90]171
172/** AHCI PCI register Revision ID. */
173typedef struct {
174 /** Indicates stepping of the HBA hardware. */
175 uint8_t u8;
[730dce77]176} ahci_pcireg_rid_t;
[9904eb90]177
178/** AHCI PCI register Class Codes. */
179typedef struct {
180 /** Programing interface, when set to 01h and the scc is set to 06h,
181 * indicates that this an AHCI HBA major revision 1.
182 */
183 uint8_t pi;
184 /** When set to 06h, indicates that is a SATA device. */
185 uint8_t scc;
186 /** Value 01 indicates that is a mass storage device. */
187 uint8_t bcc;
[730dce77]188} ahci_pcireg_cc_t_t;
[9904eb90]189
190/** AHCI PCI register Cache Line Size. */
191typedef struct {
[730dce77]192 /** Cache line size for use with the memory write and invalidate command. */
[9904eb90]193 uint8_t u8;
[730dce77]194} ahci_pcireg_cls_t;
[9904eb90]195
196/** AHCI PCI register Master Latency Timer. */
197typedef struct {
198 /** Master latency timer,indicates the number of clocks the HBA is allowed
199 * to acts as master on PCI.
200 */
201 uint8_t u8;
[730dce77]202} ahci_pcireg_mlt_t;
[9904eb90]203
204/** AHCI PCI register Header Type. */
205typedef union {
206 struct {
[ae3ff9f5]207 /** Header layout. */
[9904eb90]208 unsigned int hl : 7;
[ae3ff9f5]209 /** Multi function device flag. */
[9904eb90]210 unsigned int mfd : 1;
[730dce77]211 };
[9904eb90]212 uint8_t u8;
[730dce77]213} ahci_pciregs_htype_t;
[9904eb90]214
215/** AHCI PCI register Built in self test. */
216typedef union {
217 struct {
218 /** Indicates the completion status of BIST
219 * non-zero value indicates a failure.
220 */
221 unsigned int cc : 4;
222 /** Reserved. */
223 unsigned int reserved : 2;
224 /** Software sets this bit to 1 to invoke BIST,
225 * the HBA clears this bit to 0 when BIST is complete.
226 */
227 unsigned int sb : 1;
228 /** BIST capable. */
229 unsigned int bc : 1;
[730dce77]230 };
[9904eb90]231 uint8_t u8;
[730dce77]232} ahci_pciregs_bist_t;
[9904eb90]233
234/** AHCI PCI register AHCI Base Address <BAR 5>. */
235typedef union {
236 struct {
237 /** Indicates a request for register memory space. */
238 unsigned int rte : 1;
239 /** Indicates the this range can be mapped anywhere in 32-bit address
240 * space.
241 */
242 unsigned int tp : 2;
243 /** Indicate that this range is not prefetchable. */
244 unsigned int pf : 1;
245 /** Reserved. */
246 unsigned int reserved : 9;
247 /** Base address of registry memory space. */
248 unsigned int ba : 19;
[730dce77]249 };
[9904eb90]250 uint32_t u32;
[730dce77]251} ahci_pciregs_abar_t;
[9904eb90]252
253/** AHCI PCI register Subsystem Identifiers. */
254typedef struct
255{
256 /** Sub system vendor identifier. */
257 uint8_t ssvid;
258 /** Sub system identifier. */
259 uint8_t ssid;
[730dce77]260} ahci_pcireg_ss_t;
[9904eb90]261
262/** AHCI PCI registers Expansion ROM Base Address. */
263typedef struct
264{
265 /** Indicates the base address of the HBA expansion ROM. */
266 uint32_t u32;
[730dce77]267} ahci_pcireg_erom_t;
[9904eb90]268
269/** AHCI PCI register Capabilities Pointer. */
270typedef struct
271{
272 /** Indicates the first capability pointer offset. */
273 uint8_t u8;
[730dce77]274} ahci_pcireg_cap_t;
[9904eb90]275
276/** AHCI PCI register Interrupt Information. */
277typedef struct
278{
279 /* Software written value to indicate which interrupt vector
280 * the interrupt is connected to.
281 */
282 uint8_t iline;
283 /** This indicates the interrupt pin the HBA uses. */
284 uint8_t ipin;
[730dce77]285} ahci_pcireg_intr;
[9904eb90]286
287/** AHCI PCI register Min Grant (Optional). */
288typedef struct
289{
[ae3ff9f5]290 /** Indicates the minimum grant time that the device
291 * wishes grant asserted.
[9904eb90]292 */
293 uint8_t u8;
[730dce77]294} ahci_pcireg_mgnt_t;
[9904eb90]295
296/** AHCI PCI register Max Latency (Optional). */
297typedef struct
298{
299 /** Indicates the maximum latency that the device can withstand. */
300 uint8_t u8;
[730dce77]301} ahci_pcireg_mlat_t;
[9904eb90]302
303/*----------------------------------------------------------------------------*/
304/*-- AHCI Memory Registers ---------------------------------------------------*/
305/*----------------------------------------------------------------------------*/
306
[ae3ff9f5]307/** Number of pages for ahci memory registers. */
308#define AHCI_MEMREGS_PAGES_COUNT 8
309
[9904eb90]310/** AHCI Memory register Generic Host Control - HBA Capabilities. */
311typedef union {
312 struct {
313 /** Number of Ports. */
314 unsigned int np : 5;
315 /** Supports External SATA. */
316 unsigned int sxs : 1;
317 /** Enclosure Management Supported. */
318 unsigned int ems : 1;
319 /** Command Completion Coalescing Supported. */
320 unsigned int cccs : 1;
321 /** Number of Command Slots. */
322 unsigned int ncs : 5;
323 /** Partial State Capable. */
324 unsigned int psc : 1;
325 /** Slumber State Capable. */
326 unsigned int ssc : 1;
327 /** PIO Multiple DRQ Block. */
328 unsigned int pmd : 1;
329 /** FIS-based Switching Supported. */
330 unsigned int fbss : 1;
331 /** Supports Port Multiplier. */
332 unsigned int spm : 1;
333 /** Supports AHCI mode only. */
334 unsigned int sam : 1;
335 /** Reserved. */
336 unsigned int reserved : 1;
337 /** Interface Speed Support. */
338 unsigned int iss : 4;
339 /** Supports Command List Override. */
340 unsigned int sclo : 1;
341 /** Supports Activity LED. */
342 unsigned int sal : 1;
343 /** Supports Aggressive Link Power Management. */
344 unsigned int salp : 1;
345 /** Supports Staggered Spin-up. */
346 unsigned int sss : 1;
347 /** Supports Mechanical Presence Switch. */
348 unsigned int smps : 1;
349 /** Supports SNotification Register. */
350 unsigned int ssntf : 1;
351 /** Supports Native Command Queuing. */
352 unsigned int sncq : 1;
353 /** Supports 64-bit Addressing. */
354 unsigned int s64a : 1;
[730dce77]355 };
[9904eb90]356 uint32_t u32;
[730dce77]357} ahci_ghc_cap_t;
[9904eb90]358
359/** AHCI Memory register Generic Host Control Global Host Control. */
360typedef union {
361 struct {
362 /** HBA Reset. */
363 unsigned int hr : 1;
364 /** Interrupt Enable. */
365 unsigned int ie : 1;
366 /** MSI Revert to Single Message. */
367 unsigned int mrsm : 1;
368 /** Reserved. */
369 unsigned int reserved : 28;
370 /** AHCI Enable. */
371 unsigned int ae : 1;
[730dce77]372 };
[9904eb90]373 uint32_t u32;
[730dce77]374} ahci_ghc_ghc_t;
[9904eb90]375
376/** AHCI Enable mask bit. */
377#define AHCI_GHC_GHC_AE 0x80000000
378
379/** AHCI Interrupt Enable mask bit. */
380#define AHCI_GHC_GHC_IE 0x00000002
381
382/** AHCI Memory register Interrupt pending register. */
[eb3683a]383typedef uint32_t ahci_ghc_is_t;
[9904eb90]384
[ae3ff9f5]385/** AHCI GHC register offset. */
[eb3683a]386#define AHCI_GHC_IS_REGISTER_OFFSET 2
387
388/** AHCI ports registers offset. */
389#define AHCI_PORTS_REGISTERS_OFFSET 64
390
391/** AHCI port registers size. */
392#define AHCI_PORT_REGISTERS_SIZE 32
393
394/** AHCI port IS register offset. */
395#define AHCI_PORT_IS_REGISTER_OFFSET 4
[ae3ff9f5]396
[9904eb90]397/** AHCI Memory register Ports implemented. */
398typedef struct {
399 /** If a bit is set to 1, the corresponding port
400 * is available for software use.
401 */
402 uint32_t u32;
[730dce77]403} ahci_ghc_pi_t;
[9904eb90]404
405/** AHCI Memory register AHCI version. */
406typedef struct {
407 /** Indicates the minor version */
408 uint16_t mnr;
409 /** Indicates the major version */
410 uint16_t mjr;
[730dce77]411} ahci_ghc_vs_t;
[9904eb90]412
413/** AHCI Memory register Command completion coalesce control. */
414typedef union {
415 struct {
416 /** Enable CCC features. */
417 unsigned int en : 1;
418 /** Reserved. */
419 unsigned int reserved : 2;
420 /** Interrupt number for CCC. */
421 unsigned int intr : 5;
422 /** Number of command completions that are necessary to cause
423 * a CCC interrupt.
424 */
425 uint8_t cc;
426 /** Timeout value in ms. */
427 uint16_t tv;
[730dce77]428 };
[9904eb90]429 uint32_t u32;
[730dce77]430} ahci_ghc_ccc_ctl_t;
[9904eb90]431
432/** AHCI Memory register Command completion coalescing ports. */
433typedef struct
434{
435 /** If a bit is set to 1, the corresponding port is
436 * part of the command completion coalescing feature.
437 */
438 uint32_t u32;
[730dce77]439} ahci_ghc_ccc_ports_t;
[9904eb90]440
441/** AHCI Memory register Enclosure management location. */
442typedef struct
443{
444 /** Size of the transmit message buffer area in dwords. */
445 uint16_t sz;
[ae3ff9f5]446 /*
447 * Offset of the transmit message buffer area in dwords
[9904eb90]448 * from the beginning of ABAR
449 */
450 uint16_t ofst;
[730dce77]451} ahci_ghc_em_loc;
[9904eb90]452
453/** AHCI Memory register Enclosure management control. */
454typedef union {
455 struct {
456 /** Message received. */
457 unsigned int mr : 1;
458 /** Reserved. */
459 unsigned int reserved : 7;
460 /** Transmit message. */
461 unsigned int tm : 1;
462 /** Reset. */
463 unsigned int rst : 1;
464 /** Reserved. */
465 unsigned int reserved2 : 6;
466 /** LED message types. */
467 unsigned int led : 1;
468 /** Support SAFT-TE message type. */
469 unsigned int safte : 1;
470 /** Support SES-2 message type. */
471 unsigned int ses2 : 1;
472 /** Support SGPIO register. */
473 unsigned int sgpio : 1;
474 /** Reserved. */
475 unsigned int reserved3 : 4;
476 /** Single message buffer. */
477 unsigned int smb : 1;
478 /** Support transmitting only. */
479 unsigned int xmt : 1;
480 /** Activity LED hardware driven. */
481 unsigned int alhd : 1;
[ae3ff9f5]482 /** Port multiplier support. */
[9904eb90]483 unsigned int pm : 1;
484 /** Reserved. */
485 unsigned int reserved4 : 4;
[730dce77]486 };
[9904eb90]487 uint32_t u32;
[730dce77]488} ahci_ghc_em_ctl_t;
[9904eb90]489
490/** AHCI Memory register HBA capatibilities extended. */
491typedef union {
492 struct {
493 /** HBA support BIOS/OS handoff mechanism,
494 * implemented BOHC register.
495 */
496 unsigned int boh : 1;
497 /** Support for NVMHCI register. */
498 unsigned int nvmp : 1;
499 /** Automatic partial to slumber transition support. */
500 unsigned int apst : 1;
501 /** Reserved. */
502 unsigned int reserved : 29;
[730dce77]503 };
[9904eb90]504 uint32_t u32;
[730dce77]505} ahci_ghc_cap2_t;
[9904eb90]506
507/** AHCI Memory register BIOS/OS Handoff control and status. */
508typedef union {
509 struct {
510 /** BIOS Owned semaphore. */
511 unsigned int bos : 1;
512 /** OS Owned semaphore. */
513 unsigned int oos : 1;
514 /** SMI on OS ownership change enable. */
515 unsigned int sooe : 1;
516 /** OS ownership change. */
517 unsigned int ooc : 1;
518 /** BIOS Busy. */
519 unsigned int bb : 1;
520 /** Reserved. */
521 unsigned int reserved : 27;
[730dce77]522 };
[9904eb90]523 uint32_t u32;
[730dce77]524} ahci_ghc_bohc_t;
[9904eb90]525
526/** AHCI Memory register Generic Host Control. */
527typedef struct
528{
[ae3ff9f5]529 /** Host Capabilities */
[9904eb90]530 uint32_t cap;
[ae3ff9f5]531 /** Global Host Control */
[9904eb90]532 uint32_t ghc;
[ae3ff9f5]533 /** Interrupt Status */
[eb3683a]534 ahci_ghc_is_t is;
[ae3ff9f5]535 /** Ports Implemented */
[9904eb90]536 uint32_t pi;
[ae3ff9f5]537 /** Version */
[9904eb90]538 uint32_t vs;
[ae3ff9f5]539 /** Command Completion Coalescing Control */
[9904eb90]540 uint32_t ccc_ctl;
[ae3ff9f5]541 /** Command Completion Coalescing Ports */
[9904eb90]542 uint32_t ccc_ports;
[ae3ff9f5]543 /** Enclosure Management Location */
[9904eb90]544 uint32_t em_loc;
[ae3ff9f5]545 /** Enclosure Management Control */
[9904eb90]546 uint32_t em_ctl;
[ae3ff9f5]547 /** Host Capabilities Extended */
[9904eb90]548 uint32_t cap2;
[ae3ff9f5]549 /** BIOS/OS Handoff Control and Status */
[9904eb90]550 uint32_t bohc;
[730dce77]551} ahci_ghc_t;
[9904eb90]552
553/** AHCI Memory register Port x Command List Base Address. */
554typedef union {
555 struct {
556 /** Reserved. */
557 unsigned int reserved : 10;
558 /** Command List Base Address (CLB) - Indicates the 32-bit base physical
559 * address for the command list for this port. This base is used when
560 * fetching commands to execute. The structure pointed to by this
561 * address range is 1K-bytes in length. This address must be 1K-byte
562 * aligned as indicated by bits 09:00 being read only.
563 */
564 unsigned int clb : 22;
[730dce77]565 };
[9904eb90]566 uint32_t u32;
[730dce77]567} ahci_port_clb_t;
[9904eb90]568
569/** AHCI Memory register Port x Command List Base Address Upper 32-Bits. */
570typedef struct {
571 /** Command List Base Address Upper (CLBU): Indicates the upper 32-bits
572 * for the command list base physical address for this port. This base
573 * is used when fetching commands to execute. This register shall
574 * be read only for HBAs that do not support 64-bit addressing.
575 */
576 uint32_t u32;
[730dce77]577} ahci_port_clbu_t;
[9904eb90]578
579/** AHCI Memory register Port x FIS Base Address. */
580typedef union {
581 struct {
582 /** Reserved. */
[730dce77]583 unsigned int reserved : 8;
[9904eb90]584 /** FIS Base Address (FB) - Indicates the 32-bit base physical address
585 * for received FISes. The structure pointed to by this address range
586 * is 256 bytes in length. This address must be 256-byte aligned as
587 * indicated by bits 07:00 being read only. When FIS-based switching
588 * is in use, this structure is 4KB in length and the address shall be
589 * 4KB aligned.
590 */
591 unsigned int fb : 24;
[730dce77]592 };
[9904eb90]593 uint32_t u32;
[730dce77]594} ahci_port_fb_t;
[9904eb90]595
596/** AHCI Memory register Port x FIS Base Address Upper 32-Bits. */
597typedef struct {
598 /** FIS Base Address Upper (FBU) - Indicates the upper 32-bits
599 * for the received FIS base physical address for this port. This register
600 * shall be read only for HBAs that do not support 64-bit addressing.
601 */
602 uint32_t u32;
[730dce77]603} ahci_port_fbu_t;
[9904eb90]604
605/** AHCI Memory register Port x Interrupt Status. */
[eb3683a]606typedef uint32_t ahci_port_is_t;
[9904eb90]607
608#define AHCI_PORT_IS_DHRS (1 << 0)
609#define AHCI_PORT_IS_PSS (1 << 1)
610#define AHCI_PORT_IS_DSS (1 << 2)
611#define AHCI_PORT_IS_SDBS (1 << 3)
612#define AHCI_PORT_IS_UFS (1 << 4)
613#define AHCI_PORT_IS_DPS (1 << 5)
614#define AHCI_PORT_IS_PCS (1 << 6)
615#define AHCI_PORT_IS_DMPS (1 << 7)
616
617#define AHCI_PORT_IS_PRCS (1 << 22)
618#define AHCI_PORT_IS_IPMS (1 << 23)
619#define AHCI_PORT_IS_OFS (1 << 24)
620#define AHCI_PORT_IS_INFS (1 << 26)
621#define AHCI_PORT_IS_IFS (1 << 27)
622#define AHCI_PORT_IS_HDBS (1 << 28)
623#define AHCI_PORT_IS_HBFS (1 << 29)
624#define AHCI_PORT_IS_TFES (1 << 30)
625#define AHCI_PORT_IS_CPDS (1 << 31)
626
627#define AHCI_PORT_END_OF_OPERATION \
628 (AHCI_PORT_IS_DHRS | \
629 AHCI_PORT_IS_SDBS )
630
631#define AHCI_PORT_IS_ERROR \
632 (AHCI_PORT_IS_UFS | \
633 AHCI_PORT_IS_PCS | \
634 AHCI_PORT_IS_DMPS | \
635 AHCI_PORT_IS_PRCS | \
636 AHCI_PORT_IS_IPMS | \
637 AHCI_PORT_IS_OFS | \
638 AHCI_PORT_IS_INFS | \
639 AHCI_PORT_IS_IFS | \
640 AHCI_PORT_IS_HDBS | \
641 AHCI_PORT_IS_HBFS | \
642 AHCI_PORT_IS_TFES | \
643 AHCI_PORT_IS_CPDS)
644
645#define AHCI_PORT_IS_PERMANENT_ERROR \
646 (AHCI_PORT_IS_PCS | \
647 AHCI_PORT_IS_DMPS | \
648 AHCI_PORT_IS_PRCS | \
649 AHCI_PORT_IS_IPMS | \
650 AHCI_PORT_IS_CPDS )
651
652/** Evaluate end of operation status from port interrupt status.
653 *
654 * @param port_is Value of port interrupt status.
655 *
656 * @return Indicate end of operation status.
657 *
658 */
659static inline int ahci_port_is_end_of_operation(ahci_port_is_t port_is)
660{
[eb3683a]661 return port_is & AHCI_PORT_END_OF_OPERATION;
[9904eb90]662}
663
664/** Evaluate error status from port interrupt status.
665 *
666 * @param port_is Value of port interrupt status.
667 *
668 * @return Indicate error status.
669 *
670 */
671static inline int ahci_port_is_error(ahci_port_is_t port_is)
672{
[eb3683a]673 return port_is & AHCI_PORT_IS_ERROR;
[9904eb90]674}
675
676/** Evaluate permanent error status from port interrupt status.
677 *
678 * @param port_is Value of port interrupt status.
679 *
680 * @return Indicate permanent error status.
681 *
682 */
683static inline int ahci_port_is_permanent_error(ahci_port_is_t port_is)
684{
[eb3683a]685 return port_is & AHCI_PORT_IS_PERMANENT_ERROR;
[9904eb90]686}
687
688/** Evaluate task file error status from port interrupt status.
689 *
690 * @param port_is Value of port interrupt status.
691 *
692 * @return Indicate error status.
693 *
694 */
695static inline int ahci_port_is_tfes(ahci_port_is_t port_is)
696{
[eb3683a]697 return port_is & AHCI_PORT_IS_TFES;
[9904eb90]698}
699
700/** AHCI Memory register Port x Interrupt Enable. */
701typedef union {
702 struct {
703 /** Device to Host Register FIS Interrupt Enable. */
704 unsigned int dhre : 1;
705 /** PIO Setup FIS Interrupt Enable. */
706 unsigned int pse : 1;
707 /** DMA Setup FIS Interrupt Enable. */
708 unsigned int dse : 1;
709 /** Set Device Bits Interrupt Eenable. */
710 unsigned int sdbe : 1;
711 /** Unknown FIS Interrupt Enable. */
712 unsigned int ufe : 1;
713 /** Descriptor Processed Interrupt Enable. */
714 unsigned int dpe : 1;
715 /** Port Change Interrupt Enable. */
716 unsigned int pce : 1;
717 /** Device Mechanical Presence Enable. */
718 unsigned int dmpe : 1;
719 /** Reserved. */
720 unsigned int reserved1 : 14;
721 /** PhyRdy Change Interrupt Enable. */
722 unsigned int prce : 1;
723 /** Incorrect Port Multiplier Enable. */
724 unsigned int ipme : 1;
725 /** Overflow Status Enable. */
726 unsigned int ofe : 1;
727 /** Reserved. */
728 unsigned int reserved2 : 1;
729 /** Interface Non-fatal Error Enable. */
730 unsigned int infe : 1;
731 /** Interface Fatal Error Enable. */
732 unsigned int ife : 1;
733 /** Host Bus Data Error Enable. */
734 unsigned int hbde : 1;
735 /** Host Bus Fatal Error Enable. */
736 unsigned int hbfe : 1;
737 /** Task File Error Enable. */
738 unsigned int tfee : 1;
739 /** Cold Port Detect Enable. */
740 unsigned int cpde : 1;
[730dce77]741 };
[9904eb90]742 uint32_t u32;
[730dce77]743} ahci_port_ie_t;
[9904eb90]744
745/** AHCI Memory register Port x Command and Status. */
746typedef union {
747 struct {
748 /** Start - when set, the HBA may process the command list. */
749 unsigned int st : 1;
750 /** Spin-Up Device. */
751 unsigned int sud : 1;
752 /** Power On Device. */
753 unsigned int pod : 1;
754 /** Command List Override. */
755 unsigned int clo : 1;
756 /** FIS Receive Enable. */
757 unsigned int fre : 1;
758 /** Reserved. */
759 unsigned int reserved : 3;
760 /** Current Command Slot. */
761 unsigned int ccs : 5;
762 /** Mechanical Presence Switch State. */
763 unsigned int mpss : 1;
764 /** FIS Receive Running. */
765 unsigned int fr : 1;
766 /** Command List Running. */
767 unsigned int cr : 1;
768 /** Cold Presence State. */
769 unsigned int cps : 1;
770 /** Port Multiplier Attached. */
771 unsigned int pma : 1;
772 /** Hot Plug Capable Port. */
773 unsigned int hpcp : 1;
774 /** Mechanical Presence Switch Attached to Port. */
775 unsigned int mpsp : 1;
776 /** Cold Presence Detection. */
777 unsigned int cpd : 1;
778 /** External SATA Port. */
779 unsigned int esp : 1;
780 /** FIS-based Switching Capable Port. */
781 unsigned int fbscp : 1;
782 /** Automatic Partial to Slumber Transitions Enabled. */
783 unsigned int apste : 1;
784 /** Device is ATAPI. */
785 unsigned int atapi : 1;
786 /** Drive LED on ATAPI Enable. */
787 unsigned int dlae : 1;
788 /** Aggressive Link Power Management Enable. */
789 unsigned int alpe : 1;
790 /** Aggressive Slumber / Partial. */
791 unsigned int asp : 1;
792 /** Interface Communication Control.
793 * Values:
794 * 7h - fh Reserved,
[ae3ff9f5]795 * 6h Slumber - This shall cause the HBA to request a transition
796 * of the interface to the Slumber state,
[9904eb90]797 * 3h - 5h Reserved,
[ae3ff9f5]798 * 2h Partial - This shall cause the HBA to request a transition
799 * of the interface to the Partial state,
[9904eb90]800 * 1h Active,
801 * 0h No-Op / Idle.
802 */
803 unsigned int icc : 4;
[730dce77]804 };
[9904eb90]805 uint32_t u32;
[730dce77]806} ahci_port_cmd_t;
[9904eb90]807
808/** AHCI Memory register Port x Task File Data. */
809typedef union {
810 struct {
811 /** Status (STS): Contains the latest copy of the task file
812 * status register.
813 */
814 uint8_t sts;
815 /** Error (ERR) - Contains the latest copy of the task file
816 * error register.
817 */
818 uint8_t err;
819 /** Reserved. */
820 uint16_t reserved;
[730dce77]821 };
[9904eb90]822 uint32_t u32;
[730dce77]823} ahci_port_tfd_t;
[9904eb90]824
825/** AHCI Memory register Port x Signature. */
826typedef union {
827 struct {
828 /** Sector Count Register */
829 uint8_t sector_count;
830 /** LBA Low Register */
831 uint8_t lba_lr;
832 /** LBA Mid Register */
833 uint8_t lba_mr;
[ae3ff9f5]834 /** LBA High Register */
[9904eb90]835 uint8_t lba_hr;
[730dce77]836 };
[9904eb90]837 uint32_t u32;
[730dce77]838} ahci_port_sig_t;
[9904eb90]839
840/** AHCI Memory register Port x Serial ATA Status (SCR0: SStatus). */
841typedef union {
842 struct {
843 /** Device Detection */
844 unsigned int det : 4;
845 /** Current Interface Speed */
846 unsigned int spd : 4;
847 /** Interface Power Management */
848 unsigned int ipm : 4;
849 /** Reserved. */
850 unsigned int reserved : 20;
[730dce77]851 };
[9904eb90]852 uint32_t u32;
[730dce77]853} ahci_port_ssts_t;
[9904eb90]854
[ae3ff9f5]855/** Device detection active status. */
856#define AHCI_PORT_SSTS_DET_ACTIVE 3
857
[9904eb90]858/** AHCI Memory register Port x Serial ATA Control (SCR2: SControl). */
859typedef union {
860 struct {
861 /** Device Detection Initialization */
862 unsigned int det : 4;
863 /** Speed Allowed */
864 unsigned int spd : 4;
865 /** Interface Power Management Transitions Allowed */
866 unsigned int ipm : 4;
867 /** Reserved. */
868 unsigned int reserved : 20;
[730dce77]869 };
[9904eb90]870 uint32_t u32;
[730dce77]871} ahci_port_sctl_t;
[9904eb90]872
873/** AHCI Memory register Port x Port x Serial ATA Error (SCR1: SError). */
874typedef struct {
875 /** Error (ERR) - The ERR field contains error information for use
876 * by host software in determining the appropriate response to the
877 * error condition.
878 */
879 uint16_t err;
880 /** Diagnostics (DIAG) - Contains diagnostic error information for use
881 * by diagnostic software in validating correct operation or isolating
882 * failure modes.
883 */
884 uint16_t diag;
[730dce77]885} ahci_port_serr_t;
[9904eb90]886
887/** AHCI Memory register Port x Serial ATA Active (SCR3: SActive). */
888typedef struct {
889 /** Device Status - Each bit corresponds to the TAG and
890 * command slot of a native queued command, where bit 0 corresponds
891 * to TAG 0 and command slot 0.
892 */
893 uint32_t u32;
[730dce77]894} ahci_port_sact_t;
[9904eb90]895
896/** AHCI Memory register Port x Command Issue. */
897typedef struct {
898 /** Commands Issued - Each bit corresponds to a command slot,
899 * where bit 0 corresponds to command slot 0.
900 */
901 uint32_t u32;
[730dce77]902} ahci_port_ci_t;
[9904eb90]903
904/** AHCI Memory register Port x Serial ATA Notification
905 * (SCR4: SNotification).
906 */
907typedef struct {
908 /** PM Notify (PMN): This field indicates whether a particular device with
909 * the corresponding PM Port number issued a Set Device Bits FIS
910 * to the host with the Notification bit set.
911 */
912 uint16_t pmn;
913 /** Reserved. */
914 uint16_t reserved;
[730dce77]915} ahci_port_sntf_t;
[9904eb90]916
917/** AHCI Memory register Port x FIS-based Switching Control.
918 * This register is used to control and obtain status
919 * for Port Multiplier FIS-based switching.
920 */
921typedef union {
922 struct {
923 /** Enable */
924 unsigned int en : 1;
925 /** Device Error Clear */
926 unsigned int dec : 1;
927 /** Single Device Error */
928 unsigned int sde : 1;
929 /** Reserved. */
930 unsigned int reserved1 : 5;
931 /** Device To Issue */
932 unsigned int dev : 1;
933 /** Active Device Optimization */
934 unsigned int ado : 1;
935 /** Device With Error */
936 unsigned int dwe : 1;
937 /** Reserved. */
938 unsigned int reserved2 : 1;
[730dce77]939 };
[9904eb90]940 uint32_t u32;
[730dce77]941} ahci_port_fbs_t;
[9904eb90]942
943/** AHCI Memory register Port. */
944typedef volatile struct
945{
946 /** Port x Command List Base Address. */
947 uint32_t pxclb;
948 /** Port x Command List Base Address Upper 32-Bits. */
949 uint32_t pxclbu;
950 /** Port x FIS Base Address. */
951 uint32_t pxfb;
952 /** Port x FIS Base Address Upper 32-Bits. */
953 uint32_t pxfbu;
954 /** Port x Interrupt Status. */
[eb3683a]955 ahci_port_is_t pxis;
[9904eb90]956 /** Port x Interrupt Enable. */
957 uint32_t pxie;
958 /** Port x Command and Status. */
959 uint32_t pxcmd;
960 /** Reserved. */
961 uint32_t reserved1;
962 /** Port x Task File Data. */
963 uint32_t pxtfd;
964 /** Port x Signature. */
965 uint32_t pxsig;
966 /** Port x Serial ATA Status (SCR0: SStatus). */
967 uint32_t pxssts;
968 /** Port x Serial ATA Control (SCR2: SControl). */
969 uint32_t pxsctl;
970 /** Port x Serial ATA Error (SCR1: SError). */
971 uint32_t pxserr;
972 /** Port x Serial ATA Active (SCR3: SActive). */
973 uint32_t pxsact;
974 /** Port x Command Issue. */
975 uint32_t pxci;
976 /** Port x Serial ATA Notification (SCR4: SNotification). */
977 uint32_t pxsntf;
978 /** Port x FIS-based Switching Control. */
979 uint32_t pxfbs;
980 /** Reserved. */
981 uint32_t reserved2[11];
982 /** Port x Vendor Specific. */
983 uint32_t pxvs[4];
[730dce77]984} ahci_port_t;
[9904eb90]985
986/** AHCI Memory Registers. */
987typedef volatile struct {
988 /** Generic Host Control. */
989 ahci_ghc_t ghc;
990 /** Reserved. */
[eb3683a]991 uint32_t reserved[13];
[9904eb90]992 /** Reserved for NVMHCI. */
[ae3ff9f5]993 uint32_t reservedfornvmhci[16];
[9904eb90]994 /** Vendor Specific registers. */
[ae3ff9f5]995 uint32_t vendorspecificsregs[24];
[9904eb90]996 /** Ports. */
[eb3683a]997 ahci_port_t ports[AHCI_MAX_PORTS];
[730dce77]998} ahci_memregs_t;
[9904eb90]999
[ae3ff9f5]1000/** AHCI Command header entry.
1001 *
1002 * This structure is not an AHCI register.
1003 *
1004 */
[9904eb90]1005typedef volatile struct {
1006 /** Flags. */
1007 uint16_t flags;
1008 /** Physical Region Descriptor Table Length. */
1009 uint16_t prdtl;
1010 /** Physical Region Descriptor Byte Count. */
1011 uint32_t bytesprocessed;
1012 /** Command Table Descriptor Base Address. */
1013 uint32_t cmdtable;
1014 /** Command Table Descriptor Base Address Upper 32-bits. */
1015 uint32_t cmdtableu;
[730dce77]1016} ahci_cmdhdr_t;
[9904eb90]1017
[ae3ff9f5]1018/** Clear Busy upon R_OK (C) flag. */
1019#define AHCI_CMDHDR_FLAGS_CLEAR_BUSY_UPON_OK 0x0400
1020
1021/** Write operation flag. */
1022#define AHCI_CMDHDR_FLAGS_WRITE 0x0040
1023
1024/** 2 DW length command flag. */
1025#define AHCI_CMDHDR_FLAGS_2DWCMD 0x0002
1026
1027/** 5 DW length command flag. */
1028#define AHCI_CMDHDR_FLAGS_5DWCMD 0x0005
1029
1030/** AHCI Command Physical Region Descriptor entry.
1031 *
1032 * This structure is not an AHCI register.
1033 *
1034 */
[9904eb90]1035typedef volatile struct {
1036 /** Word aligned 32-bit data base address. */
1037 uint32_t data_address_low;
1038 /** Upper data base address, valid only for 64-bit HBA addressing. */
1039 uint32_t data_address_upper;
1040 /** Reserved. */
1041 uint32_t reserved1;
1042 /** Data byte count */
1043 unsigned int dbc : 22;
1044 /** Reserved */
1045 unsigned int reserved2 : 9;
[ae3ff9f5]1046 /** Set Interrupt on each operation completion */
[9904eb90]1047 unsigned int ioc : 1;
[730dce77]1048} ahci_cmd_prdt_t;
[9904eb90]1049
1050#endif
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