1 | /*
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2 | * Copyright (c) 2011 Jan Vesely
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | *
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9 | * - Redistributions of source code must retain the above copyright
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10 | * notice, this list of conditions and the following disclaimer.
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11 | * - Redistributions in binary form must reproduce the above copyright
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12 | * notice, this list of conditions and the following disclaimer in the
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13 | * documentation and/or other materials provided with the distribution.
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14 | * - The name of the author may not be used to endorse or promote products
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15 | * derived from this software without specific prior written permission.
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16 | *
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17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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27 | */
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28 | /** @addtogroup drvaudiosb16
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29 | * @{
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30 | */
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31 | /** @file
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32 | * @brief DMA memory management
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33 | */
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34 | #include <assert.h>
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35 | #include <errno.h>
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36 | #include <ddi.h>
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37 | #include <libarch/ddi.h>
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38 |
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39 | #include "dma_controller.h"
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40 |
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41 | #define DMA_CONTROLLER_FIRST_BASE ((void*)0x0)
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42 | typedef struct dma_controller_regs_first {
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43 | uint8_t channel_start0;
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44 | uint8_t channel_count0;
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45 | uint8_t channel_start1;
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46 | uint8_t channel_count1;
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47 | uint8_t channel_start2;
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48 | uint8_t channel_count2;
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49 | uint8_t channel_start3;
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50 | uint8_t channel_count3;
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51 |
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52 | uint8_t command_status;
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53 | #define DMA_STATUS_REQ(x) (1 << ((x % 4) + 4))
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54 | #define DMA_STATUS_COMPLETE(x) (1 << (x % 4))
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55 | /* http://wiki.osdev.org/DMA: The only bit that works is COND(bit 2) */
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56 | #define DMA_COMMAND_COND (1 << 2) /* Disables DMA controller */
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57 |
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58 | uint8_t request; /* Memory to memory transfers, NOT implemented on PCs*/
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59 | uint8_t single_mask;
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60 | #define DMA_SINGLE_MASK_CHAN_SEL_MASK (0x3)
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61 | #define DMA_SINGLE_MASK_CHAN_SEL_SHIFT (0)
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62 | #define DMA_SINGLE_MASK_CHAN_TO_REG(x) \
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63 | (((x % 4) & DMA_SINGLE_MASK_CHAN_SEL_MASK) << DMA_SINGLE_MASK_CHAN_SEL_SHIFT)
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64 | #define DMA_SINGLE_MASK_MASKED_FLAG (1 << 2)
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65 |
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66 | uint8_t mode;
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67 | #define DMA_MODE_CHAN_SELECT_MASK (0x3)
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68 | #define DMA_MODE_CHAN_SELECT_SHIFT (0)
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69 | #define DMA_MODE_CHAN_TRA_MASK (0x3)
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70 | #define DMA_MODE_CHAN_TRA_SHIFT (2)
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71 | #define DMA_MODE_CHAN_TRA_SELF_TEST (0)
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72 | #define DMA_MODE_CHAN_TRA_WRITE (1)
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73 | #define DMA_MODE_CHAN_TRA_READ (2)
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74 | #define DMA_MODE_CHAN_AUTO_FLAG (1 << 4)
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75 | #define DMA_MODE_CHAN_DOWN_FLAG (1 << 5)
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76 | #define DMA_MODE_CHAN_MOD_MASK (0x3)
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77 | #define DMA_MODE_CHAN_MOD_SHIFT (6)
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78 | #define DMA_MODE_CHAN_MOD_DEMAND (0)
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79 | #define DMA_MODE_CHAN_MOD_SINGLE (1)
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80 | #define DMA_MODE_CHAN_MOD_BLOCK (2)
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81 | #define DMA_MODE_CHAN_MOD_CASCADE (3)
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82 |
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83 | uint8_t flip_flop;
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84 | uint8_t master_reset; /* Intermediate is not implemented on PCs */
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85 | uint8_t mask_reset;
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86 | /* Master reset sets Flip-Flop low, clears status,sets all mask bits on */
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87 |
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88 | uint8_t multi_mask;
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89 | #define DMA_MULTI_MASK_CHAN(x) (1 << (x % 4))
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90 |
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91 | } dma_controller_regs_first_t;
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92 |
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93 | #define DMA_CONTROLLER_SECOND_BASE ((void*)0xc0)
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94 | /* See dma_controller_regs_first_t for register values */
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95 | typedef struct dma_controller_regs_second {
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96 | uint8_t channel_start4;
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97 | uint8_t reserved0;
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98 | uint8_t channel_count4;
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99 | uint8_t reserved1;
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100 | uint8_t channel_start5;
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101 | uint8_t reserved2;
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102 | uint8_t channel_count5;
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103 | uint8_t reserved3;
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104 | uint8_t channel_start6;
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105 | uint8_t reserved4;
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106 | uint8_t channel_count6;
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107 | uint8_t reserved5;
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108 | uint8_t channel_start7;
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109 | uint8_t reserved6;
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110 | uint8_t channel_count7;
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111 |
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112 | uint8_t command_status;
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113 | uint8_t reserved8;
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114 | uint8_t request;
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115 | uint8_t reserved9;
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116 | uint8_t single_mask;
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117 | uint8_t reserveda;
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118 | uint8_t mode;
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119 | uint8_t reservedb;
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120 | uint8_t flip_flop;
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121 | uint8_t reservedc;
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122 | uint8_t master_reset_intermediate;
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123 | uint8_t reservedd;
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124 | uint8_t multi_mask;
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125 | } dma_controller_regs_second_t;
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126 |
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127 | #define DMA_CONTROLLER_PAGE_BASE ((void*)0x81)
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128 | typedef struct dma_page_regs {
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129 | uint8_t channel2;
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130 | uint8_t channel3;
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131 | uint8_t channel1;
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132 | uint8_t reserved0;
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133 | uint8_t reserved1;
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134 | uint8_t reserved2;
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135 | uint8_t channel0;
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136 | uint8_t reserved3;
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137 | uint8_t channel6;
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138 | uint8_t channel7;
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139 | uint8_t channel5;
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140 | uint8_t reserved4;
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141 | uint8_t reserved5;
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142 | uint8_t reserved6;
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143 | uint8_t channel4;
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144 | } dma_page_regs_t;
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145 |
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146 | typedef struct dma_channel {
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147 | uint8_t *offset_reg_address;
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148 | uint8_t *size_reg_address;
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149 | uint8_t *page_reg_address;
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150 | } dma_channel_t;
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151 |
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152 | typedef struct dma_controller {
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153 | dma_channel_t channel[8];
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154 | dma_page_regs_t *page_table;
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155 | dma_controller_regs_first_t *first;
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156 | dma_controller_regs_second_t *second;
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157 | } dma_controller_t;
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158 |
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159 | dma_controller_t controller_8237 = {
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160 | .channel = {
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161 | { (uint8_t*)0x00, (uint8_t*)0x01, (uint8_t*)0x87 },
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162 | { (uint8_t*)0x02, (uint8_t*)0x03, (uint8_t*)0x83 },
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163 | { (uint8_t*)0x04, (uint8_t*)0x05, (uint8_t*)0x81 },
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164 | { (uint8_t*)0x06, (uint8_t*)0x07, (uint8_t*)0x82 },
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165 | { (uint8_t*)0xc0, (uint8_t*)0xc2, (uint8_t*)0x8f },
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166 | { (uint8_t*)0xc4, (uint8_t*)0xc6, (uint8_t*)0x8b },
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167 | { (uint8_t*)0xc8, (uint8_t*)0xca, (uint8_t*)0x89 },
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168 | { (uint8_t*)0xcc, (uint8_t*)0xce, (uint8_t*)0x8a } },
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169 | .page_table = NULL,
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170 | .first = NULL,
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171 | .second = NULL,
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172 | };
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173 |
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174 | static inline dma_controller_t *dma_controller_init()
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175 | {
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176 | int ret = pio_enable(DMA_CONTROLLER_PAGE_BASE, sizeof(dma_page_regs_t),
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177 | (void**)&controller_8237.page_table);
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178 | if (ret != EOK)
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179 | return NULL;
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180 |
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181 | ret = pio_enable(DMA_CONTROLLER_FIRST_BASE,
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182 | sizeof(dma_controller_regs_first_t),
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183 | (void**)&controller_8237.first);
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184 | if (ret != EOK)
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185 | return NULL;
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186 |
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187 | ret = pio_enable(DMA_CONTROLLER_SECOND_BASE,
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188 | sizeof(dma_controller_regs_second_t),
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189 | (void**)&controller_8237.second);
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190 | if (ret != EOK)
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191 | return NULL;
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192 | return &controller_8237;
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193 | }
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194 | /*----------------------------------------------------------------------------*/
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195 | static int dma_setup_channel_8bit(dma_controller_t *controller,
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196 | unsigned channel, uint32_t pa, uint16_t size)
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197 | {
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198 | if (channel == 0 || channel > 3)
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199 | return ENOTSUP;
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200 | assert(controller);
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201 | /* Mask DMA request */
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202 | uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel)
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203 | | DMA_SINGLE_MASK_MASKED_FLAG;
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204 | pio_write_8(&controller->first->single_mask, value);
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205 |
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206 | /* Set address -- reset flip-flop*/
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207 | pio_write_8(&controller->first->flip_flop, 1);
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208 |
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209 | /* Low byte */
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210 | value = pa & 0xff;
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211 | pio_write_8(controller->channel[channel].offset_reg_address, value);
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212 |
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213 | /* High byte */
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214 | value = (pa >> 8) & 0xff;
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215 | pio_write_8(controller->channel[channel].offset_reg_address, value);
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216 |
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217 | /* Page address - third byte */
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218 | value = (pa >> 16) & 0xff;
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219 | pio_write_8(controller->channel[channel].offset_reg_address, value);
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220 |
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221 | /* Set size -- reset flip-flop */
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222 | pio_write_8(&controller->first->flip_flop, 1);
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223 |
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224 | /* Low byte */
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225 | value = size & 0xff;
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226 | pio_write_8(controller->channel[channel].offset_reg_address, value);
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227 |
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228 | /* High byte */
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229 | value = (size >> 8) & 0xff;
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230 | pio_write_8(controller->channel[channel].offset_reg_address, value);
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231 |
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232 | /* Unmask DMA request */
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233 | value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
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234 | pio_write_8(&controller->first->single_mask, value);
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235 |
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236 | return EOK;
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237 | }
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238 | /*----------------------------------------------------------------------------*/
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239 | static int dma_setup_channel_16bit(dma_controller_t *controller,
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240 | unsigned channel, uintptr_t pa, size_t size)
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241 | {
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242 | if (channel == 4 || channel > 7)
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243 | return ENOTSUP;
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244 | assert(controller);
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245 | /* Mask DMA request */
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246 | uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel)
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247 | | DMA_SINGLE_MASK_MASKED_FLAG;
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248 | pio_write_8(&controller->second->single_mask, value);
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249 |
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250 | /* Set address -- reset flip-flop*/
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251 | pio_write_8(&controller->second->flip_flop, 1);
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252 |
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253 | /* Low byte */
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254 | value = pa & 0xff;
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255 | pio_write_8(controller->channel[channel].offset_reg_address, value);
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256 |
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257 | /* High byte */
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258 | value = (pa >> 8) & 0xff;
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259 | pio_write_8(controller->channel[channel].offset_reg_address, value);
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260 |
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261 | /* Page address - third byte */
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262 | value = (pa >> 16) & 0xff;
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263 | pio_write_8(controller->channel[channel].offset_reg_address, value);
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264 |
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265 | /* Set size -- reset flip-flop */
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266 | pio_write_8(&controller->second->flip_flop, 1);
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267 |
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268 | /* Low byte */
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269 | value = size & 0xff;
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270 | pio_write_8(controller->channel[channel].offset_reg_address, value);
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271 |
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272 | /* High byte */
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273 | value = (size >> 8) & 0xff;
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274 | pio_write_8(controller->channel[channel].offset_reg_address, value);
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275 |
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276 | /* Unmask DMA request */
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277 | value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
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278 | pio_write_8(&controller->second->single_mask, value);
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279 |
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280 | return EOK;
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281 | }
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282 | /*----------------------------------------------------------------------------*/
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283 | int dma_setup_channel(unsigned channel, uintptr_t pa, size_t size)
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284 | {
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285 | static dma_controller_t *controller = NULL;
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286 | if (!controller)
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287 | controller = dma_controller_init();
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288 | if (!controller)
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289 | return EIO;
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290 | if (channel <= 4)
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291 | return dma_setup_channel_8bit(controller, channel, pa, size);
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292 | else
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293 | return dma_setup_channel_16bit(controller, channel, pa, size);
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294 | }
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295 | /**
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296 | * @}
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297 | */
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