source: mainline/uspace/drv/audio/sb16/dma_controller.c@ d2134da

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d2134da was d2134da, checked in by Jan Vesely <jano.vesely@…>, 14 years ago

sb16: Implement DMA channel setup.

Without mode selection for now.

  • Property mode set to 100644
File size: 9.0 KB
Line 
1/*
2 * Copyright (c) 2011 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup drvaudiosb16
29 * @{
30 */
31/** @file
32 * @brief DMA memory management
33 */
34#include <assert.h>
35#include <errno.h>
36#include <ddi.h>
37#include <libarch/ddi.h>
38
39#include "dma_controller.h"
40
41#define DMA_CONTROLLER_FIRST_BASE ((void*)0x0)
42typedef struct dma_controller_regs_first {
43 uint8_t channel_start0;
44 uint8_t channel_count0;
45 uint8_t channel_start1;
46 uint8_t channel_count1;
47 uint8_t channel_start2;
48 uint8_t channel_count2;
49 uint8_t channel_start3;
50 uint8_t channel_count3;
51
52 uint8_t command_status;
53#define DMA_STATUS_REQ(x) (1 << ((x % 4) + 4))
54#define DMA_STATUS_COMPLETE(x) (1 << (x % 4))
55/* http://wiki.osdev.org/DMA: The only bit that works is COND(bit 2) */
56#define DMA_COMMAND_COND (1 << 2) /* Disables DMA controller */
57
58 uint8_t request; /* Memory to memory transfers, NOT implemented on PCs*/
59 uint8_t single_mask;
60#define DMA_SINGLE_MASK_CHAN_SEL_MASK (0x3)
61#define DMA_SINGLE_MASK_CHAN_SEL_SHIFT (0)
62#define DMA_SINGLE_MASK_CHAN_TO_REG(x) \
63 (((x % 4) & DMA_SINGLE_MASK_CHAN_SEL_MASK) << DMA_SINGLE_MASK_CHAN_SEL_SHIFT)
64#define DMA_SINGLE_MASK_MASKED_FLAG (1 << 2)
65
66 uint8_t mode;
67#define DMA_MODE_CHAN_SELECT_MASK (0x3)
68#define DMA_MODE_CHAN_SELECT_SHIFT (0)
69#define DMA_MODE_CHAN_TRA_MASK (0x3)
70#define DMA_MODE_CHAN_TRA_SHIFT (2)
71#define DMA_MODE_CHAN_TRA_SELF_TEST (0)
72#define DMA_MODE_CHAN_TRA_WRITE (1)
73#define DMA_MODE_CHAN_TRA_READ (2)
74#define DMA_MODE_CHAN_AUTO_FLAG (1 << 4)
75#define DMA_MODE_CHAN_DOWN_FLAG (1 << 5)
76#define DMA_MODE_CHAN_MOD_MASK (0x3)
77#define DMA_MODE_CHAN_MOD_SHIFT (6)
78#define DMA_MODE_CHAN_MOD_DEMAND (0)
79#define DMA_MODE_CHAN_MOD_SINGLE (1)
80#define DMA_MODE_CHAN_MOD_BLOCK (2)
81#define DMA_MODE_CHAN_MOD_CASCADE (3)
82
83 uint8_t flip_flop;
84 uint8_t master_reset; /* Intermediate is not implemented on PCs */
85 uint8_t mask_reset;
86/* Master reset sets Flip-Flop low, clears status,sets all mask bits on */
87
88 uint8_t multi_mask;
89#define DMA_MULTI_MASK_CHAN(x) (1 << (x % 4))
90
91} dma_controller_regs_first_t;
92
93#define DMA_CONTROLLER_SECOND_BASE ((void*)0xc0)
94/* See dma_controller_regs_first_t for register values */
95typedef struct dma_controller_regs_second {
96 uint8_t channel_start4;
97 uint8_t reserved0;
98 uint8_t channel_count4;
99 uint8_t reserved1;
100 uint8_t channel_start5;
101 uint8_t reserved2;
102 uint8_t channel_count5;
103 uint8_t reserved3;
104 uint8_t channel_start6;
105 uint8_t reserved4;
106 uint8_t channel_count6;
107 uint8_t reserved5;
108 uint8_t channel_start7;
109 uint8_t reserved6;
110 uint8_t channel_count7;
111
112 uint8_t command_status;
113 uint8_t reserved8;
114 uint8_t request;
115 uint8_t reserved9;
116 uint8_t single_mask;
117 uint8_t reserveda;
118 uint8_t mode;
119 uint8_t reservedb;
120 uint8_t flip_flop;
121 uint8_t reservedc;
122 uint8_t master_reset_intermediate;
123 uint8_t reservedd;
124 uint8_t multi_mask;
125} dma_controller_regs_second_t;
126
127#define DMA_CONTROLLER_PAGE_BASE ((void*)0x81)
128typedef struct dma_page_regs {
129 uint8_t channel2;
130 uint8_t channel3;
131 uint8_t channel1;
132 uint8_t reserved0;
133 uint8_t reserved1;
134 uint8_t reserved2;
135 uint8_t channel0;
136 uint8_t reserved3;
137 uint8_t channel6;
138 uint8_t channel7;
139 uint8_t channel5;
140 uint8_t reserved4;
141 uint8_t reserved5;
142 uint8_t reserved6;
143 uint8_t channel4;
144} dma_page_regs_t;
145
146typedef struct dma_channel {
147 uint8_t *offset_reg_address;
148 uint8_t *size_reg_address;
149 uint8_t *page_reg_address;
150} dma_channel_t;
151
152typedef struct dma_controller {
153 dma_channel_t channel[8];
154 dma_page_regs_t *page_table;
155 dma_controller_regs_first_t *first;
156 dma_controller_regs_second_t *second;
157} dma_controller_t;
158
159dma_controller_t controller_8237 = {
160 .channel = {
161 { (uint8_t*)0x00, (uint8_t*)0x01, (uint8_t*)0x87 },
162 { (uint8_t*)0x02, (uint8_t*)0x03, (uint8_t*)0x83 },
163 { (uint8_t*)0x04, (uint8_t*)0x05, (uint8_t*)0x81 },
164 { (uint8_t*)0x06, (uint8_t*)0x07, (uint8_t*)0x82 },
165 { (uint8_t*)0xc0, (uint8_t*)0xc2, (uint8_t*)0x8f },
166 { (uint8_t*)0xc4, (uint8_t*)0xc6, (uint8_t*)0x8b },
167 { (uint8_t*)0xc8, (uint8_t*)0xca, (uint8_t*)0x89 },
168 { (uint8_t*)0xcc, (uint8_t*)0xce, (uint8_t*)0x8a } },
169 .page_table = NULL,
170 .first = NULL,
171 .second = NULL,
172};
173
174static inline dma_controller_t *dma_controller_init()
175{
176 int ret = pio_enable(DMA_CONTROLLER_PAGE_BASE, sizeof(dma_page_regs_t),
177 (void**)&controller_8237.page_table);
178 if (ret != EOK)
179 return NULL;
180
181 ret = pio_enable(DMA_CONTROLLER_FIRST_BASE,
182 sizeof(dma_controller_regs_first_t),
183 (void**)&controller_8237.first);
184 if (ret != EOK)
185 return NULL;
186
187 ret = pio_enable(DMA_CONTROLLER_SECOND_BASE,
188 sizeof(dma_controller_regs_second_t),
189 (void**)&controller_8237.second);
190 if (ret != EOK)
191 return NULL;
192 return &controller_8237;
193}
194/*----------------------------------------------------------------------------*/
195static int dma_setup_channel_8bit(dma_controller_t *controller,
196 unsigned channel, uint32_t pa, uint16_t size)
197{
198 if (channel == 0 || channel > 3)
199 return ENOTSUP;
200 assert(controller);
201 /* Mask DMA request */
202 uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel)
203 | DMA_SINGLE_MASK_MASKED_FLAG;
204 pio_write_8(&controller->first->single_mask, value);
205
206 /* Set address -- reset flip-flop*/
207 pio_write_8(&controller->first->flip_flop, 1);
208
209 /* Low byte */
210 value = pa & 0xff;
211 pio_write_8(controller->channel[channel].offset_reg_address, value);
212
213 /* High byte */
214 value = (pa >> 8) & 0xff;
215 pio_write_8(controller->channel[channel].offset_reg_address, value);
216
217 /* Page address - third byte */
218 value = (pa >> 16) & 0xff;
219 pio_write_8(controller->channel[channel].offset_reg_address, value);
220
221 /* Set size -- reset flip-flop */
222 pio_write_8(&controller->first->flip_flop, 1);
223
224 /* Low byte */
225 value = size & 0xff;
226 pio_write_8(controller->channel[channel].offset_reg_address, value);
227
228 /* High byte */
229 value = (size >> 8) & 0xff;
230 pio_write_8(controller->channel[channel].offset_reg_address, value);
231
232 /* Unmask DMA request */
233 value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
234 pio_write_8(&controller->first->single_mask, value);
235
236 return EOK;
237}
238/*----------------------------------------------------------------------------*/
239static int dma_setup_channel_16bit(dma_controller_t *controller,
240 unsigned channel, uintptr_t pa, size_t size)
241{
242 if (channel == 4 || channel > 7)
243 return ENOTSUP;
244 assert(controller);
245 /* Mask DMA request */
246 uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel)
247 | DMA_SINGLE_MASK_MASKED_FLAG;
248 pio_write_8(&controller->second->single_mask, value);
249
250 /* Set address -- reset flip-flop*/
251 pio_write_8(&controller->second->flip_flop, 1);
252
253 /* Low byte */
254 value = pa & 0xff;
255 pio_write_8(controller->channel[channel].offset_reg_address, value);
256
257 /* High byte */
258 value = (pa >> 8) & 0xff;
259 pio_write_8(controller->channel[channel].offset_reg_address, value);
260
261 /* Page address - third byte */
262 value = (pa >> 16) & 0xff;
263 pio_write_8(controller->channel[channel].offset_reg_address, value);
264
265 /* Set size -- reset flip-flop */
266 pio_write_8(&controller->second->flip_flop, 1);
267
268 /* Low byte */
269 value = size & 0xff;
270 pio_write_8(controller->channel[channel].offset_reg_address, value);
271
272 /* High byte */
273 value = (size >> 8) & 0xff;
274 pio_write_8(controller->channel[channel].offset_reg_address, value);
275
276 /* Unmask DMA request */
277 value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
278 pio_write_8(&controller->second->single_mask, value);
279
280 return EOK;
281}
282/*----------------------------------------------------------------------------*/
283int dma_setup_channel(unsigned channel, uintptr_t pa, size_t size)
284{
285 static dma_controller_t *controller = NULL;
286 if (!controller)
287 controller = dma_controller_init();
288 if (!controller)
289 return EIO;
290 if (channel <= 4)
291 return dma_setup_channel_8bit(controller, channel, pa, size);
292 else
293 return dma_setup_channel_16bit(controller, channel, pa, size);
294}
295/**
296 * @}
297 */
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