| 1 | /*
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| 2 | * Copyright (c) 2011 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 | /** @addtogroup drvaudiosb16
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| 29 | * @{
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| 30 | */
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| 31 | /** @file
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| 32 | * @brief DMA memory management
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| 33 | */
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| 34 | #include <assert.h>
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| 35 | #include <errno.h>
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| 36 | #include <ddi.h>
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| 37 | #include <libarch/ddi.h>
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| 38 |
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| 39 | #include "ddf_log.h"
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| 40 | #include "dma_controller.h"
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| 41 |
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| 42 | #define DMA_CONTROLLER_FIRST_BASE ((void*)0x0)
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| 43 | typedef struct dma_controller_regs_first {
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| 44 | uint8_t channel_start0;
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| 45 | uint8_t channel_count0;
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| 46 | uint8_t channel_start1;
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| 47 | uint8_t channel_count1;
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| 48 | uint8_t channel_start2;
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| 49 | uint8_t channel_count2;
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| 50 | uint8_t channel_start3;
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| 51 | uint8_t channel_count3;
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| 52 |
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| 53 | uint8_t command_status;
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| 54 | #define DMA_STATUS_REQ(x) (1 << ((x % 4) + 4))
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| 55 | #define DMA_STATUS_COMPLETE(x) (1 << (x % 4))
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| 56 | /* http://wiki.osdev.org/DMA: The only bit that works is COND(bit 2) */
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| 57 | #define DMA_COMMAND_COND (1 << 2) /* Disables DMA controller */
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| 58 |
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| 59 | uint8_t request; /* Memory to memory transfers, NOT implemented on PCs*/
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| 60 | uint8_t single_mask;
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| 61 | #define DMA_SINGLE_MASK_CHAN_SEL_MASK (0x3)
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| 62 | #define DMA_SINGLE_MASK_CHAN_SEL_SHIFT (0)
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| 63 | #define DMA_SINGLE_MASK_CHAN_TO_REG(x) \
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| 64 | (((x % 4) & DMA_SINGLE_MASK_CHAN_SEL_MASK) << DMA_SINGLE_MASK_CHAN_SEL_SHIFT)
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| 65 | #define DMA_SINGLE_MASK_MASKED_FLAG (1 << 2)
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| 66 |
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| 67 | uint8_t mode;
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| 68 | #define DMA_MODE_CHAN_SELECT_MASK (0x3)
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| 69 | #define DMA_MODE_CHAN_SELECT_SHIFT (0)
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| 70 | #define DMA_MODE_CHAN_TO_REG(x) \
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| 71 | (((x % 4) & DMA_MODE_CHAN_SELECT_MASK) << DMA_MODE_CHAN_SELECT_SHIFT)
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| 72 | #define DMA_MODE_CHAN_TRA_MASK (0x3)
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| 73 | #define DMA_MODE_CHAN_TRA_SHIFT (2)
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| 74 | #define DMA_MODE_CHAN_TRA_SELF_TEST (0)
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| 75 | #define DMA_MODE_CHAN_TRA_WRITE (0x1)
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| 76 | #define DMA_MODE_CHAN_TRA_READ (0x2)
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| 77 | #define DMA_MODE_CHAN_AUTO_FLAG (1 << 4)
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| 78 | #define DMA_MODE_CHAN_DOWN_FLAG (1 << 5)
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| 79 | #define DMA_MODE_CHAN_MODE_MASK (0x3)
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| 80 | #define DMA_MODE_CHAN_MODE_SHIFT (6)
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| 81 | #define DMA_MODE_CHAN_MODE_DEMAND (0)
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| 82 | #define DMA_MODE_CHAN_MODE_SINGLE (1)
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| 83 | #define DMA_MODE_CHAN_MODE_BLOCK (2)
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| 84 | #define DMA_MODE_CHAN_MODE_CASCADE (3)
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| 85 |
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| 86 | uint8_t flip_flop;
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| 87 | uint8_t master_reset; /* Intermediate is not implemented on PCs */
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| 88 | uint8_t mask_reset;
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| 89 | /* Master reset sets Flip-Flop low, clears status,sets all mask bits on */
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| 90 |
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| 91 | uint8_t multi_mask;
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| 92 | #define DMA_MULTI_MASK_CHAN(x) (1 << (x % 4))
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| 93 |
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| 94 | } dma_controller_regs_first_t;
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| 95 |
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| 96 | #define DMA_CONTROLLER_SECOND_BASE ((void*)0xc0)
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| 97 | /* See dma_controller_regs_first_t for register values */
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| 98 | typedef struct dma_controller_regs_second {
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| 99 | uint8_t channel_start4;
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| 100 | uint8_t reserved0;
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| 101 | uint8_t channel_count4;
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| 102 | uint8_t reserved1;
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| 103 | uint8_t channel_start5;
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| 104 | uint8_t reserved2;
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| 105 | uint8_t channel_count5;
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| 106 | uint8_t reserved3;
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| 107 | uint8_t channel_start6;
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| 108 | uint8_t reserved4;
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| 109 | uint8_t channel_count6;
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| 110 | uint8_t reserved5;
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| 111 | uint8_t channel_start7;
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| 112 | uint8_t reserved6;
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| 113 | uint8_t channel_count7;
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| 114 |
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| 115 | uint8_t command_status;
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| 116 | uint8_t reserved8;
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| 117 | uint8_t request;
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| 118 | uint8_t reserved9;
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| 119 | uint8_t single_mask;
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| 120 | uint8_t reserveda;
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| 121 | uint8_t mode;
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| 122 | uint8_t reservedb;
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| 123 | uint8_t flip_flop;
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| 124 | uint8_t reservedc;
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| 125 | uint8_t master_reset_intermediate;
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| 126 | uint8_t reservedd;
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| 127 | uint8_t multi_mask;
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| 128 | } dma_controller_regs_second_t;
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| 129 |
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| 130 | #define DMA_CONTROLLER_PAGE_BASE ((void*)0x81)
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| 131 | typedef struct dma_page_regs {
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| 132 | uint8_t channel2;
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| 133 | uint8_t channel3;
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| 134 | uint8_t channel1;
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| 135 | uint8_t reserved0;
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| 136 | uint8_t reserved1;
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| 137 | uint8_t reserved2;
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| 138 | uint8_t channel0;
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| 139 | uint8_t reserved3;
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| 140 | uint8_t channel6;
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| 141 | uint8_t channel7;
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| 142 | uint8_t channel5;
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| 143 | uint8_t reserved4;
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| 144 | uint8_t reserved5;
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| 145 | uint8_t reserved6;
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| 146 | uint8_t channel4;
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| 147 | } dma_page_regs_t;
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| 148 |
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| 149 | typedef struct dma_channel {
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| 150 | uint8_t *offset_reg_address;
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| 151 | uint8_t *size_reg_address;
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| 152 | uint8_t *page_reg_address;
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| 153 | uint8_t *single_mask_address;
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| 154 | uint8_t *mode_address;
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| 155 | uint8_t *flip_flop_address;
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| 156 | } dma_channel_t;
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| 157 |
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| 158 | typedef struct dma_controller {
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| 159 | dma_channel_t channels[8];
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| 160 | dma_page_regs_t *page_table;
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| 161 | dma_controller_regs_first_t *first;
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| 162 | dma_controller_regs_second_t *second;
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| 163 | bool initialized;
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| 164 | } dma_controller_t;
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| 165 |
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| 166 |
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| 167 | /* http://zet.aluzina.org/index.php/8237_DMA_controller#DMA_Channel_Registers */
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| 168 | static dma_controller_t controller_8237 = {
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| 169 | .channels = {
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| 170 | /* The first chip */
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| 171 | { (uint8_t*)0x00, (uint8_t*)0x01, (uint8_t*)0x87,
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| 172 | (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
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| 173 | { (uint8_t*)0x02, (uint8_t*)0x03, (uint8_t*)0x83,
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| 174 | (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
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| 175 | { (uint8_t*)0x04, (uint8_t*)0x05, (uint8_t*)0x81,
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| 176 | (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
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| 177 | { (uint8_t*)0x06, (uint8_t*)0x07, (uint8_t*)0x82,
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| 178 | (uint8_t*)0x0a, (uint8_t*)0x0b, (uint8_t*)0x0c, },
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| 179 |
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| 180 | /* The second chip */
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| 181 | { (uint8_t*)0xc0, (uint8_t*)0xc2, (uint8_t*)0x8f,
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| 182 | (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, },
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| 183 | { (uint8_t*)0xc4, (uint8_t*)0xc6, (uint8_t*)0x8b,
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| 184 | (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, },
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| 185 | { (uint8_t*)0xc8, (uint8_t*)0xca, (uint8_t*)0x89,
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| 186 | (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, },
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| 187 | { (uint8_t*)0xcc, (uint8_t*)0xce, (uint8_t*)0x8a,
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| 188 | (uint8_t*)0xd4, (uint8_t*)0xd6, (uint8_t*)0xd8, }, },
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| 189 |
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| 190 | .page_table = NULL,
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| 191 | .first = NULL,
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| 192 | .second = NULL,
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| 193 | .initialized = false,
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| 194 | };
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| 195 |
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| 196 | static inline int dma_controller_init(dma_controller_t *controller)
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| 197 | {
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| 198 | assert(controller);
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| 199 | int ret = pio_enable(DMA_CONTROLLER_PAGE_BASE, sizeof(dma_page_regs_t),
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| 200 | (void**)&controller->page_table);
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| 201 | if (ret != EOK)
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| 202 | return EIO;
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| 203 |
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| 204 | ret = pio_enable(DMA_CONTROLLER_FIRST_BASE,
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| 205 | sizeof(dma_controller_regs_first_t),
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| 206 | (void**)&controller->first);
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| 207 | if (ret != EOK)
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| 208 | return EIO;
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| 209 |
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| 210 | ret = pio_enable(DMA_CONTROLLER_SECOND_BASE,
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| 211 | sizeof(dma_controller_regs_second_t),
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| 212 | (void**)&controller->second);
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| 213 | if (ret != EOK)
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| 214 | return EIO;
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| 215 | controller->initialized = true;
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| 216 | return EOK;
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| 217 | }
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| 218 | /*----------------------------------------------------------------------------*/
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| 219 | int dma_setup_channel(unsigned channel, uintptr_t pa, size_t size)
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| 220 | {
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| 221 | if (channel == 0 || channel == 4)
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| 222 | return ENOTSUP;
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| 223 | if (channel > 7)
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| 224 | return ENOENT;
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| 225 |
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| 226 | if (!controller_8237.initialized)
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| 227 | dma_controller_init(&controller_8237);
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| 228 |
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| 229 | if (!controller_8237.initialized)
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| 230 | return EIO;
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| 231 |
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| 232 | /* 16 bit transfers are a bit special */
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| 233 | ddf_log_debug("Unspoiled address and size: %p(%zu).\n", pa, size);
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| 234 | if (channel > 4) {
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| 235 | /* Size is the count of 16bit words */
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| 236 | assert(size % 2 == 0);
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| 237 | size /= 2;
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| 238 | /* Address is fun: lower 16bits need to be shifted by 1 */
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| 239 | pa = ((pa & 0xffff) >> 1) | (pa & 0xff0000);
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| 240 | }
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| 241 |
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| 242 | const dma_channel_t dma_channel = controller_8237.channels[channel];
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| 243 |
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| 244 | ddf_log_debug("Setting channel %u, to address %p(%zu).\n",
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| 245 | channel, pa, size);
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| 246 | /* Mask DMA request */
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| 247 | uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel)
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| 248 | | DMA_SINGLE_MASK_MASKED_FLAG;
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| 249 | pio_write_8(dma_channel.single_mask_address, value);
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| 250 |
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| 251 | /* Set address -- reset flip-flop*/
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| 252 | pio_write_8(dma_channel.flip_flop_address, 1);
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| 253 |
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| 254 | /* Low byte */
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| 255 | value = pa & 0xff;
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| 256 | ddf_log_verbose("Writing address low byte: %hhx.\n", value);
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| 257 | pio_write_8(dma_channel.offset_reg_address, value);
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| 258 |
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| 259 | /* High byte */
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| 260 | value = (pa >> 8) & 0xff;
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| 261 | ddf_log_verbose("Writing address high byte: %hhx.\n", value);
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| 262 | pio_write_8(dma_channel.offset_reg_address, value);
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| 263 |
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| 264 | /* Page address - third byte */
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| 265 | value = (pa >> 16) & 0xff;
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| 266 | ddf_log_verbose("Writing address page byte: %hhx.\n", value);
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| 267 | pio_write_8(dma_channel.offset_reg_address, value);
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| 268 |
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| 269 | /* Set size -- reset flip-flop */
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| 270 | pio_write_8(dma_channel.flip_flop_address, 1);
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| 271 |
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| 272 | /* Low byte */
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| 273 | value = (size - 1) & 0xff;
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| 274 | ddf_log_verbose("Writing size low byte: %hhx.\n", value);
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| 275 | pio_write_8(dma_channel.offset_reg_address, value);
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| 276 |
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| 277 | /* High byte */
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| 278 | value = ((size - 1) >> 8) & 0xff;
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| 279 | ddf_log_verbose("Writing size high byte: %hhx.\n", value);
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| 280 | pio_write_8(dma_channel.offset_reg_address, value);
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| 281 |
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| 282 | /* Unmask DMA request */
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| 283 | value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
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| 284 | pio_write_8(dma_channel.single_mask_address, value);
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| 285 |
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| 286 | return EOK;
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| 287 | }
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| 288 | /*----------------------------------------------------------------------------*/
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| 289 | int dma_prepare_channel(
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| 290 | unsigned channel, bool write, bool auto_mode, transfer_mode_t mode)
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| 291 | {
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| 292 | if (channel == 0 || channel == 4)
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| 293 | return ENOTSUP;
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| 294 | if (channel > 7)
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| 295 | return ENOENT;
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| 296 |
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| 297 | if (!controller_8237.initialized)
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| 298 | return EIO;
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| 299 |
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| 300 | dma_channel_t dma_channel = controller_8237.channels[channel];
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| 301 |
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| 302 | /* Mask DMA request */
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| 303 | uint8_t value = DMA_SINGLE_MASK_CHAN_TO_REG(channel)
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| 304 | | DMA_SINGLE_MASK_MASKED_FLAG;
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| 305 | pio_write_8(dma_channel.single_mask_address, value);
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| 306 |
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| 307 | /* Set DMA mode */
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| 308 | value = DMA_MODE_CHAN_TO_REG(channel)
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| 309 | | ((write ? DMA_MODE_CHAN_TRA_WRITE : DMA_MODE_CHAN_TRA_READ)
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| 310 | << DMA_MODE_CHAN_TRA_SHIFT)
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| 311 | | (auto_mode ? DMA_MODE_CHAN_AUTO_FLAG : 0)
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| 312 | | (mode << DMA_MODE_CHAN_MODE_SHIFT);
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| 313 | ddf_log_verbose("Setting mode: %hhx.\n", value);
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| 314 | pio_write_8(dma_channel.mode_address, value);
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| 315 |
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| 316 | /* Unmask DMA request */
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| 317 | value = DMA_SINGLE_MASK_CHAN_TO_REG(channel);
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| 318 | pio_write_8(dma_channel.single_mask_address, value);
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| 319 |
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| 320 | return EOK;
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| 321 | }
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| 322 | /**
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| 323 | * @}
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| 324 | */
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