source: mainline/uspace/drv/audio/hdaudio/hdactl.c@ 903eff5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 903eff5 was 903eff5, checked in by Jiri Svoboda <jiri@…>, 11 years ago

First sound.
  • Property mode set to 100644
File size: 14.5 KB
Line 
1/*
2 * Copyright (c) 2014 Jiri Svoboda
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup hdaudio
30 * @{
31 */
32/** @file High Definition Audio controller
33 */
34
35#include <as.h>
36#include <async.h>
37#include <bitops.h>
38#include <ddf/log.h>
39#include <ddi.h>
40#include <errno.h>
41#include <fibril_synch.h>
42#include <macros.h>
43#include <stdint.h>
44
45#include "codec.h"
46#include "hdactl.h"
47#include "regif.h"
48#include "spec/regs.h"
49
50enum {
51 ctrl_init_wait_max = 10,
52 codec_enum_wait_us = 512,
53 corb_wait_max = 10,
54 rirb_wait_max = 100
55};
56
57/** Select an appropriate CORB/RIRB size.
58 *
59 * We always use the largest available size. In @a sizecap each of bits
60 * 0, 1, 2 determine whether one of the supported size (0 == 2 enries,
61 * 1 == 16 entries, 2 == 256 entries) is supported. @a *selsz is set to
62 * one of 0, 1, 2 on success.
63 *
64 * @param sizecap CORB/RIRB Size Capability
65 * @param selsz Place to store CORB/RIRB Size
66 * @return EOK on success, EINVAL if sizecap has no valid bits set
67 *
68 */
69static int hda_rb_size_select(uint8_t sizecap, uint8_t *selsz)
70{
71 int i;
72
73 for (i = 2; i >= 0; --i) {
74 if ((sizecap & BIT_V(uint8_t, i)) != 0) {
75 *selsz = i;
76 return EOK;
77 }
78 }
79
80 return EINVAL;
81}
82
83static size_t hda_rb_entries(uint8_t selsz)
84{
85 switch (selsz) {
86 case 0:
87 return 2;
88 case 1:
89 return 16;
90 case 2:
91 return 256;
92 default:
93 assert(false);
94 return 0;
95 }
96}
97
98/** Initialize the CORB */
99static int hda_corb_init(hda_t *hda)
100{
101 uint8_t ctl;
102 uint8_t corbsz;
103 uint8_t sizecap;
104 uint8_t selsz;
105 int rc;
106
107 ddf_msg(LVL_NOTE, "hda_corb_init()");
108
109 /* Stop CORB if not stopped */
110 ctl = hda_reg8_read(&hda->regs->corbctl);
111 if ((ctl & BIT_V(uint8_t, corbctl_run)) != 0) {
112 ddf_msg(LVL_NOTE, "CORB is enabled, disabling first.");
113 hda_reg8_write(&hda->regs->corbctl, ctl & ~BIT_V(uint8_t,
114 corbctl_run));
115 }
116
117 /* Determine CORB size and allocate CORB buffer */
118 corbsz = hda_reg8_read(&hda->regs->corbsize);
119 sizecap = BIT_RANGE_EXTRACT(uint8_t, corbsize_cap_h,
120 corbsize_cap_l, corbsz);
121 rc = hda_rb_size_select(sizecap, &selsz);
122 if (rc != EOK) {
123 ddf_msg(LVL_ERROR, "Invalid CORB Size Capability");
124 goto error;
125 }
126 corbsz = corbsz & ~BIT_RANGE(uint8_t, corbsize_size_h, corbsize_size_l);
127 corbsz = corbsz | selsz;
128
129 ddf_msg(LVL_NOTE, "Setting CORB Size register to 0x%x", corbsz);
130 hda_reg8_write(&hda->regs->corbsize, corbsz);
131 hda->ctl->corb_entries = hda_rb_entries(selsz);
132
133
134 /*
135 * CORB must be aligned to 128 bytes. If 64OK is not set,
136 * it must be within the 32-bit address space.
137 */
138 hda->ctl->corb_virt = AS_AREA_ANY;
139 rc = dmamem_map_anonymous(hda->ctl->corb_entries * sizeof(uint32_t),
140 hda->ctl->ok64bit ? 0 : DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
141 &hda->ctl->corb_phys, &hda->ctl->corb_virt);
142
143 ddf_msg(LVL_NOTE, "Set CORB base registers");
144
145 /* Update CORB base registers */
146 hda_reg32_write(&hda->regs->corblbase, LOWER32(hda->ctl->corb_phys));
147 hda_reg32_write(&hda->regs->corbubase, UPPER32(hda->ctl->corb_phys));
148
149 ddf_msg(LVL_NOTE, "Reset CORB Read/Write pointers");
150
151 /* Reset CORB Read Pointer */
152 hda_reg16_write(&hda->regs->corbrp, BIT_V(uint16_t, corbrp_rst));
153
154 /* Reset CORB Write Poitner */
155 hda_reg16_write(&hda->regs->corbwp, 0);
156
157 /* Start CORB */
158 ctl = hda_reg8_read(&hda->regs->corbctl);
159 ddf_msg(LVL_NOTE, "CORBctl (0x%x) = 0x%x",
160 (unsigned)((void *)&hda->regs->corbctl - (void *)hda->regs), ctl | BIT_V(uint8_t, corbctl_run));
161 hda_reg8_write(&hda->regs->corbctl, ctl | BIT_V(uint8_t, corbctl_run));
162
163 ddf_msg(LVL_NOTE, "CORB initialized");
164 return EOK;
165error:
166 return EIO;
167}
168
169/** Initialize the RIRB */
170static int hda_rirb_init(hda_t *hda)
171{
172 uint8_t ctl;
173 uint8_t rirbsz;
174 uint8_t sizecap;
175 uint8_t selsz;
176 int rc;
177
178 ddf_msg(LVL_NOTE, "hda_rirb_init()");
179
180 /* Stop RIRB if not stopped */
181 ctl = hda_reg8_read(&hda->regs->rirbctl);
182 if ((ctl & BIT_V(uint8_t, rirbctl_run)) != 0) {
183 ddf_msg(LVL_NOTE, "RIRB is enabled, disabling first.");
184 hda_reg8_write(&hda->regs->corbctl, ctl & ~BIT_V(uint8_t,
185 rirbctl_run));
186 }
187
188 /* Determine RIRB size and allocate RIRB buffer */
189 rirbsz = hda_reg8_read(&hda->regs->rirbsize);
190 sizecap = BIT_RANGE_EXTRACT(uint8_t, rirbsize_cap_h,
191 rirbsize_cap_l, rirbsz);
192 rc = hda_rb_size_select(sizecap, &selsz);
193 if (rc != EOK) {
194 ddf_msg(LVL_ERROR, "Invalid RIRB Size Capability");
195 goto error;
196 }
197 rirbsz = rirbsz & ~BIT_RANGE(uint8_t, rirbsize_size_h, rirbsize_size_l);
198 rirbsz = rirbsz | selsz;
199
200 ddf_msg(LVL_NOTE, "Setting RIRB Size register to 0x%x", rirbsz);
201 hda_reg8_write(&hda->regs->rirbsize, rirbsz);
202 hda->ctl->rirb_entries = hda_rb_entries(selsz);
203
204 /*
205 * RIRB must be aligned to 128 bytes. If 64OK is not set,
206 * it must be within the 32-bit address space.
207 */
208 hda->ctl->rirb_virt = AS_AREA_ANY;
209 rc = dmamem_map_anonymous(hda->ctl->rirb_entries * sizeof(uint64_t),
210 hda->ctl->ok64bit ? 0 : DMAMEM_4GiB, AS_AREA_READ | AS_AREA_WRITE, 0,
211 &hda->ctl->rirb_phys, &hda->ctl->rirb_virt);
212
213 ddf_msg(LVL_NOTE, "Set RIRB base registers");
214
215 /* Update RIRB base registers */
216 hda_reg32_write(&hda->regs->rirblbase, LOWER32(hda->ctl->rirb_phys));
217 hda_reg32_write(&hda->regs->rirbubase, UPPER32(hda->ctl->rirb_phys));
218
219 ddf_msg(LVL_NOTE, "Reset RIRB Write pointer");
220
221 /* Reset RIRB Write Pointer */
222 hda_reg16_write(&hda->regs->rirbwp, BIT_V(uint16_t, rirbwp_rst));
223
224 /* Set RINTCNT - Qemu won't read from CORB if this is zero */
225 hda_reg16_write(&hda->regs->rintcnt, hda->ctl->rirb_entries / 2);
226
227 hda->ctl->rirb_rp = 0;
228
229 /* Start RIRB and enable RIRB interrupt */
230 ctl = hda_reg8_read(&hda->regs->rirbctl);
231 ddf_msg(LVL_NOTE, "RIRBctl (0x%x) = 0x%x",
232 (unsigned)((void *)&hda->regs->rirbctl - (void *)hda->regs), ctl | BIT_V(uint8_t, rirbctl_run));
233 hda_reg8_write(&hda->regs->rirbctl, ctl | BIT_V(uint8_t, rirbctl_run) |
234 BIT_V(uint8_t, rirbctl_int));
235
236 ddf_msg(LVL_NOTE, "RIRB initialized");
237 return EOK;
238error:
239 return EIO;
240}
241
242static size_t hda_get_corbrp(hda_t *hda)
243{
244 uint16_t corbrp;
245
246 corbrp = hda_reg16_read(&hda->regs->corbrp);
247 return BIT_RANGE_EXTRACT(uint16_t, corbrp_rp_h, corbrp_rp_l, corbrp);
248}
249
250static size_t hda_get_corbwp(hda_t *hda)
251{
252 uint16_t corbwp;
253
254 corbwp = hda_reg16_read(&hda->regs->corbwp);
255 return BIT_RANGE_EXTRACT(uint16_t, corbwp_wp_h, corbwp_wp_l, corbwp);
256}
257
258static void hda_set_corbwp(hda_t *hda, size_t wp)
259{
260 ddf_msg(LVL_DEBUG2, "Set CORBWP = %d", wp);
261 hda_reg16_write(&hda->regs->corbwp, wp);
262}
263
264static size_t hda_get_rirbwp(hda_t *hda)
265{
266 uint16_t rirbwp;
267
268 rirbwp = hda_reg16_read(&hda->regs->rirbwp);
269 return BIT_RANGE_EXTRACT(uint16_t, rirbwp_wp_h, rirbwp_wp_l, rirbwp);
270}
271
272/** Determine number of free entries in CORB */
273static size_t hda_corb_avail(hda_t *hda)
274{
275 int rp, wp;
276 int avail;
277
278 rp = hda_get_corbrp(hda);
279 wp = hda_get_corbwp(hda);
280
281 avail = rp - wp - 1;
282 while (avail < 0)
283 avail += hda->ctl->corb_entries;
284
285 return avail;
286}
287
288/** Write to CORB */
289static int hda_corb_write(hda_t *hda, uint32_t *data, size_t count)
290{
291 size_t avail;
292 size_t wp;
293 size_t idx;
294 size_t now;
295 size_t i;
296 uint32_t *corb;
297 int wcnt;
298
299 avail = hda_corb_avail(hda);
300 wp = hda_get_corbwp(hda);
301 corb = (uint32_t *)hda->ctl->corb_virt;
302
303 idx = 0;
304 while (idx < count) {
305 now = min(avail, count - idx);
306
307 for (i = 0; i < now; i++) {
308 wp = (wp + 1) % hda->ctl->corb_entries;
309 corb[wp] = data[idx++];
310 }
311
312 hda_set_corbwp(hda, wp);
313
314 if (idx < count) {
315 /* We filled up CORB but still data remaining */
316 wcnt = corb_wait_max;
317 while (hda_corb_avail(hda) < 1 && wcnt > 0) {
318 async_usleep(100);
319 --wcnt;
320 }
321
322 /* If CORB is still full return timeout error */
323 if (hda_corb_avail(hda) < 1)
324 return ETIMEOUT;
325 }
326 }
327
328 return EOK;
329}
330
331static int hda_rirb_read(hda_t *hda, hda_rirb_entry_t *data)
332{
333 size_t wp;
334 hda_rirb_entry_t resp;
335 hda_rirb_entry_t *rirb;
336
337 rirb = (hda_rirb_entry_t *)hda->ctl->rirb_virt;
338
339 wp = hda_get_rirbwp(hda);
340 ddf_msg(LVL_DEBUG2, "hda_rirb_read: wp=%d", wp);
341 if (hda->ctl->rirb_rp == wp)
342 return ENOENT;
343
344 ++hda->ctl->rirb_rp;
345 resp = rirb[hda->ctl->rirb_rp];
346
347 ddf_msg(LVL_DEBUG2, "RESPONSE resp=0x%x respex=0x%x",
348 resp.resp, resp.respex);
349 *data = resp;
350 return EOK;
351}
352
353static int hda_solrb_read(hda_t *hda, hda_rirb_entry_t *data, size_t count)
354{
355 hda_rirb_entry_t resp;
356 int wcnt;
357
358 wcnt = 10*1000;
359
360 fibril_mutex_lock(&hda->ctl->solrb_lock);
361
362 while (count > 0) {
363 while (count > 0 && hda->ctl->solrb_rp != hda->ctl->solrb_wp) {
364 ++hda->ctl->solrb_rp;
365 resp = hda->ctl->solrb[hda->ctl->solrb_rp];
366
367 ddf_msg(LVL_DEBUG2, "solrb RESPONSE resp=0x%x respex=0x%x",
368 resp.resp, resp.respex);
369 if ((resp.respex & BIT_V(uint32_t, respex_unsol)) == 0) {
370 /* Solicited response */
371 *data++ = resp;
372 --count;
373 }
374 }
375
376 if (count > 0) {
377 while (wcnt > 0 && hda->ctl->solrb_wp == hda->ctl->solrb_rp) {
378 fibril_mutex_unlock(&hda->ctl->solrb_lock);
379 async_usleep(100);
380 fibril_mutex_lock(&hda->ctl->solrb_lock);
381 --wcnt;
382 }
383
384 if (hda->ctl->solrb_wp == hda->ctl->solrb_rp) {
385 ddf_msg(LVL_NOTE, "hda_solrb_read() time out");
386 fibril_mutex_unlock(&hda->ctl->solrb_lock);
387 return ETIMEOUT;
388 }
389 }
390 }
391
392 fibril_mutex_unlock(&hda->ctl->solrb_lock);
393 return EOK;
394}
395
396hda_ctl_t *hda_ctl_init(hda_t *hda)
397{
398 hda_ctl_t *ctl;
399 uint32_t gctl;
400 uint32_t intctl;
401 int cnt;
402 int rc;
403
404 ctl = calloc(1, sizeof(hda_ctl_t));
405 if (ctl == NULL)
406 return NULL;
407
408 fibril_mutex_initialize(&ctl->solrb_lock);
409 fibril_condvar_initialize(&ctl->solrb_cv);
410
411 hda->ctl = ctl;
412 ctl->hda = hda;
413
414 uint8_t vmaj = hda_reg8_read(&hda->regs->vmaj);
415 uint8_t vmin = hda_reg8_read(&hda->regs->vmin);
416 ddf_msg(LVL_NOTE, "HDA version %d.%d", vmaj, vmin);
417
418 if (vmaj != 1 || vmin != 0) {
419 ddf_msg(LVL_ERROR, "Unsupported HDA version (%d.%d).",
420 vmaj, vmin);
421 goto error;
422 }
423
424 ddf_msg(LVL_NOTE, "reg 0x%zx STATESTS = 0x%x",
425 (void *)&hda->regs->statests - (void *)hda->regs,
426 hda_reg16_read(&hda->regs->statests));
427 /**
428 * Clear STATESTS bits so they don't generate an interrupt later
429 * when we enable interrupts.
430 */
431 hda_reg16_write(&hda->regs->statests, 0x7f);
432
433 ddf_msg(LVL_NOTE, "after clearing reg 0x%zx STATESTS = 0x%x",
434 (void *)&hda->regs->statests - (void *)hda->regs,
435 hda_reg16_read(&hda->regs->statests));
436
437 gctl = hda_reg32_read(&hda->regs->gctl);
438 if ((gctl & BIT_V(uint32_t, gctl_crst)) != 0) {
439 ddf_msg(LVL_NOTE, "Controller not in reset. Resetting.");
440 hda_reg32_write(&hda->regs->gctl, gctl & ~BIT_V(uint32_t, gctl_crst));
441 }
442
443 ddf_msg(LVL_NOTE, "Taking controller out of reset.");
444 hda_reg32_write(&hda->regs->gctl, gctl | BIT_V(uint32_t, gctl_crst));
445
446 /* Wait for CRST to read as 1 */
447 cnt = ctrl_init_wait_max;
448 while (cnt > 0) {
449 gctl = hda_reg32_read(&hda->regs->gctl);
450 if ((gctl & BIT_V(uint32_t, gctl_crst)) != 0) {
451 ddf_msg(LVL_NOTE, "gctl=0x%x", gctl);
452 break;
453 }
454
455 ddf_msg(LVL_NOTE, "Waiting for controller to initialize.");
456 async_usleep(100*1000);
457 --cnt;
458 }
459
460 if (cnt == 0) {
461 ddf_msg(LVL_ERROR, "Timed out waiting for controller to come up.");
462 goto error;
463 }
464
465 ddf_msg(LVL_NOTE, "Controller is out of reset.");
466
467 ddf_msg(LVL_NOTE, "Read GCAP");
468 uint16_t gcap = hda_reg16_read(&hda->regs->gcap);
469 ctl->ok64bit = (gcap & BIT_V(uint16_t, gcap_64ok)) != 0;
470 ctl->oss = BIT_RANGE_EXTRACT(uint16_t, gcap_oss_h, gcap_oss_l, gcap);
471 ctl->iss = BIT_RANGE_EXTRACT(uint16_t, gcap_iss_h, gcap_iss_l, gcap);
472 ctl->bss = BIT_RANGE_EXTRACT(uint16_t, gcap_bss_h, gcap_bss_l, gcap);
473 ddf_msg(LVL_NOTE, "GCAP: 0x%x (64OK=%d)", gcap, ctl->ok64bit);
474
475 /* Give codecs enough time to enumerate themselves */
476 async_usleep(codec_enum_wait_us);
477
478 ddf_msg(LVL_NOTE, "STATESTS = 0x%x",
479 hda_reg16_read(&hda->regs->statests));
480
481 /* Enable interrupts */
482 intctl = hda_reg32_read(&hda->regs->intctl);
483 ddf_msg(LVL_NOTE, "intctl (0x%x) := 0x%x",
484 (unsigned)((void *)&hda->regs->intctl - (void *)hda->regs),
485 intctl | BIT_V(uint32_t, intctl_gie) | BIT_V(uint32_t, intctl_cie));
486 hda_reg32_write(&hda->regs->intctl, intctl |
487 BIT_V(uint32_t, intctl_gie) | BIT_V(uint32_t, intctl_cie) |
488 0x3fffffff);
489
490 rc = hda_corb_init(hda);
491 if (rc != EOK)
492 goto error;
493
494 rc = hda_rirb_init(hda);
495 if (rc != EOK)
496 goto error;
497
498 ddf_msg(LVL_NOTE, "call hda_codec_init()");
499 hda->ctl->codec = hda_codec_init(hda, 0);
500 if (hda->ctl->codec == NULL) {
501 ddf_msg(LVL_NOTE, "hda_codec_init() failed");
502 goto error;
503 }
504
505 async_usleep(5*1000*1000);
506 ddf_msg(LVL_NOTE, "intsts=0x%x", hda_reg32_read(&hda->regs->intsts));
507 ddf_msg(LVL_NOTE, "sdesc[%d].sts=0x%x",
508 hda->ctl->iss, hda_reg8_read(&hda->regs->sdesc[hda->ctl->iss].sts));
509
510 return ctl;
511error:
512 free(ctl);
513 hda->ctl = NULL;
514 return NULL;
515}
516
517int hda_cmd(hda_t *hda, uint32_t verb, uint32_t *resp)
518{
519 int rc;
520 hda_rirb_entry_t rentry;
521
522 rc = hda_corb_write(hda, &verb, 1);
523 if (rc != EOK)
524 return rc;
525
526 if (resp != NULL) {
527 rc = hda_solrb_read(hda, &rentry, 1);
528 if (rc != EOK)
529 return rc;
530
531 /* XXX Verify that response came from the correct codec */
532 *resp = rentry.resp;
533 }
534
535 return EOK;
536}
537
538void hda_ctl_fini(hda_ctl_t *ctl)
539{
540 ddf_msg(LVL_NOTE, "hda_ctl_fini()");
541 free(ctl);
542}
543
544void hda_ctl_interrupt(hda_ctl_t *ctl)
545{
546 hda_rirb_entry_t resp;
547 int rc;
548
549 while (true) {
550 rc = hda_rirb_read(ctl->hda, &resp);
551 if (rc != EOK) {
552// ddf_msg(LVL_NOTE, "nothing in rirb");
553 break;
554 }
555
556 ddf_msg(LVL_NOTE, "writing to solrb");
557 fibril_mutex_lock(&ctl->solrb_lock);
558 ctl->solrb_wp = (ctl->solrb_wp + 1) % softrb_entries;
559 ctl->solrb[ctl->solrb_wp] = resp;
560 fibril_mutex_unlock(&ctl->solrb_lock);
561 fibril_condvar_broadcast(&ctl->solrb_cv);
562 }
563}
564
565/** @}
566 */
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