source: mainline/uspace/app/pcc/arch/vax/order.c@ 711e7fe5

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 711e7fe5 was 711e7fe5, checked in by Prutkov Alex <prutkov.alex@…>, 14 years ago

Added printf module
  • Property mode set to 100755
File size: 12.7 KB
Line 
1/* $Id: order.c,v 1.4 2007/11/26 00:10:03 gmcgarry Exp $ */
2/*
3 * Copyright(C) Caldera International Inc. 2001-2002. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * Redistributions of source code and documentation must retain the above
10 * copyright notice, this list of conditions and the following disclaimer.
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditionsand the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed or owned by Caldera
17 * International, Inc.
18 * Neither the name of Caldera International, Inc. nor the names of other
19 * contributors may be used to endorse or promote products derived from
20 * this software without specific prior written permission.
21 *
22 * USE OF THE SOFTWARE PROVIDED FOR UNDER THIS LICENSE BY CALDERA
23 * INTERNATIONAL, INC. AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL CALDERA INTERNATIONAL, INC. BE LIABLE
27 * FOR ANY DIRECT, INDIRECT INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OFLIABILITY, WHETHER IN CONTRACT,
31 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
32 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
34 */
35
36# include "pass2.h"
37
38int canaddr(NODE *);
39
40int maxargs = { -1 };
41
42#if 0
43stoasg( p, o ) register NODE *p; {
44 /* should the assignment op p be stored,
45 given that it lies as the right operand of o
46 (or the left, if o==UNARY MUL) */
47/*
48 if( p->op == INCR || p->op == DECR ) return;
49 if( o==UNARY MUL && p->left->op == REG && !isbreg(p->left->rval) ) SETSTO(p,INAREG);
50 */
51 }
52#endif
53
54int
55deltest( p ) register NODE *p; {
56 /* should we delay the INCR or DECR operation p */
57 p = p->n_left;
58 return( p->n_op == REG || p->n_op == NAME || p->n_op == OREG );
59 }
60
61#if 0
62autoincr( p ) NODE *p; {
63 register NODE *q = p->left, *r;
64
65 if( q->op == INCR && (r=q->left)->op == REG &&
66 ISPTR(q->type) && p->type == DECREF(q->type) &&
67 tlen(p) == q->right->lval ) return(1);
68
69 return(0);
70 }
71
72mkadrs(p) register NODE *p; {
73 register o;
74
75 o = p->op;
76
77 if( asgop(o) ){
78 if( p->left->su >= p->right->su ){
79 if( p->left->op == UNARY MUL ){
80 SETSTO( p->left->left, INTEMP );
81 }
82 else if( p->left->op == FLD && p->left->left->op == UNARY MUL ){
83 SETSTO( p->left->left->left, INTEMP );
84 }
85 else { /* should be only structure assignment */
86 SETSTO( p->left, INTEMP );
87 }
88 }
89 else SETSTO( p->right, INTEMP );
90 }
91 else {
92 if( p->left->su > p->right->su ){
93 SETSTO( p->left, INTEMP );
94 }
95 else {
96 SETSTO( p->right, INTEMP );
97 }
98 }
99 }
100#endif
101
102int
103notoff(TWORD t, int r, CONSZ off, char *cp)
104{
105 /* is it legal to make an OREG or NAME entry which has an
106 * offset of off, (from a register of r), if the
107 * resulting thing had type t */
108
109/* if( r == R0 ) return( 1 ); / * NO */
110 return(0); /* YES */
111 }
112
113# define max(x,y) ((x)<(y)?(y):(x))
114
115#if 0
116sucomp( p ) register NODE *p; {
117
118 /* set the su field in the node to the sethi-ullman
119 number, or local equivalent */
120
121 register o, ty, sul, sur, r;
122
123 o = p->op;
124 ty = optype( o );
125 p->su = szty( p->type ); /* 2 for float or double, else 1 */;
126
127 if( ty == LTYPE ){
128 if( o == OREG ){
129 r = p->rval;
130 /* oreg cost is (worst case) 1 + number of temp registers used */
131 if( R2TEST(r) ){
132 if( R2UPK1(r)!=100 && istreg(R2UPK1(r)) ) ++p->su;
133 if( istreg(R2UPK2(r)) ) ++p->su;
134 }
135 else {
136 if( istreg( r ) ) ++p->su;
137 }
138 }
139 if( p->su == szty(p->type) &&
140 (p->op!=REG || !istreg(p->rval)) &&
141 (p->type==INT || p->type==UNSIGNED || p->type==DOUBLE) )
142 p->su = 0;
143 return;
144 }
145
146 else if( ty == UTYPE ){
147 switch( o ) {
148 case UNARY CALL:
149 case UNARY STCALL:
150 p->su = fregs; /* all regs needed */
151 return;
152
153 default:
154 p->su = p->left->su + (szty( p->type ) > 1 ? 2 : 0) ;
155 return;
156 }
157 }
158
159
160 /* If rhs needs n, lhs needs m, regular su computation */
161
162 sul = p->left->su;
163 sur = p->right->su;
164
165 if( o == ASSIGN ){
166 /* computed by doing right, then left (if not in mem), then doing it */
167 p->su = max(sur,sul+1);
168 return;
169 }
170
171 if( o == CALL || o == STCALL ){
172 /* in effect, takes all free registers */
173 p->su = fregs;
174 return;
175 }
176
177 if( o == STASG ){
178 /* right, then left */
179 p->su = max( max( 1+sul, sur), fregs );
180 return;
181 }
182
183 if( asgop(o) ){
184 /* computed by doing right, doing left address, doing left, op, and store */
185 p->su = max(sur,sul+2);
186/*
187 if( o==ASG MUL || o==ASG DIV || o==ASG MOD) p->su = max(p->su,fregs);
188 */
189 return;
190 }
191
192 switch( o ){
193 case ANDAND:
194 case OROR:
195 case QUEST:
196 case COLON:
197 case COMOP:
198 p->su = max( max(sul,sur), 1);
199 return;
200
201 case PLUS:
202 case OR:
203 case ER:
204 /* commutative ops; put harder on left */
205 if( p->right->su > p->left->su && !istnode(p->left) ){
206 register NODE *temp;
207 temp = p->left;
208 p->left = p->right;
209 p->right = temp;
210 }
211 break;
212 }
213
214 /* binary op, computed by left, then right, then do op */
215 p->su = max(sul,szty(p->right->type)+sur);
216/*
217 if( o==MUL||o==DIV||o==MOD) p->su = max(p->su,fregs);
218 */
219
220 }
221
222int radebug = 0;
223
224rallo( p, down ) NODE *p; {
225 /* do register allocation */
226 register o, type, down1, down2, ty;
227
228 if( radebug ) printf( "rallo( %o, %d )\n", p, down );
229
230 down2 = NOPREF;
231 p->rall = down;
232 down1 = ( down &= ~MUSTDO );
233
234 ty = optype( o = p->op );
235 type = p->type;
236
237
238 if( type == DOUBLE || type == FLOAT ){
239 if( o == FORCE ) down1 = R0|MUSTDO;
240 }
241 else switch( o ) {
242 case ASSIGN:
243 down1 = NOPREF;
244 down2 = down;
245 break;
246
247/*
248 case MUL:
249 case DIV:
250 case MOD:
251 down1 = R3|MUSTDO;
252 down2 = R5|MUSTDO;
253 break;
254
255 case ASG MUL:
256 case ASG DIV:
257 case ASG MOD:
258 p->left->rall = down1 = R3|MUSTDO;
259 if( p->left->op == UNARY MUL ){
260 rallo( p->left->left, R4|MUSTDO );
261 }
262 else if( p->left->op == FLD && p->left->left->op == UNARY MUL ){
263 rallo( p->left->left->left, R4|MUSTDO );
264 }
265 else rallo( p->left, R3|MUSTDO );
266 rallo( p->right, R5|MUSTDO );
267 return;
268 */
269
270 case CALL:
271 case STASG:
272 case EQ:
273 case NE:
274 case GT:
275 case GE:
276 case LT:
277 case LE:
278 case NOT:
279 case ANDAND:
280 case OROR:
281 down1 = NOPREF;
282 break;
283
284 case FORCE:
285 down1 = R0|MUSTDO;
286 break;
287
288 }
289
290 if( ty != LTYPE ) rallo( p->left, down1 );
291 if( ty == BITYPE ) rallo( p->right, down2 );
292
293 }
294#endif
295
296void
297offstar( p, s ) register NODE *p; {
298comperr("offstar");
299#if 0
300 if( p->n_op == PLUS ) {
301 if( p->n_left->n_su == fregs ) {
302 order( p->n_left, INAREG );
303 return;
304 } else if( p->n_right->n_su == fregs ) {
305 order( p->n_right, INAREG );
306 return;
307 }
308 if( p->n_left->n_op==LS &&
309 (p->n_left->n_left->n_op!=REG || tlen(p->n_left->n_left)!=sizeof(int) ) ) {
310 order( p->n_left->n_left, INAREG );
311 return;
312 }
313 if( p->n_right->n_op==LS &&
314 (p->n_right->n_left->n_op!=REG || tlen(p->n_right->n_left)!=sizeof(int) ) ) {
315 order( p->n_right->n_left, INAREG );
316 return;
317 }
318 if( p->n_type == (PTR|CHAR) || p->n_type == (PTR|UCHAR) ) {
319 if( p->n_left->n_op!=REG || tlen(p->n_left)!=sizeof(int) ) {
320 order( p->n_left, INAREG );
321 return;
322 }
323 else if( p->n_right->n_op!=REG || tlen(p->n_right)!=sizeof(int) ) {
324 order(p->n_right, INAREG);
325 return;
326 }
327 }
328 }
329 if( p->n_op == PLUS || p->n_op == MINUS ){
330 if( p->n_right->n_op == ICON ){
331 p = p->n_left;
332 order( p , INAREG);
333 return;
334 }
335 }
336
337 if( p->n_op == UMUL && !canaddr(p) ) {
338 offstar( p->n_left, 0 );
339 return;
340 }
341
342 order( p, INAREG );
343#endif
344 }
345
346int
347setbin( p ) register NODE *p; {
348
349#if 0
350 register int ro, rt;
351
352 rt = p->n_right->n_type;
353 ro = p->n_right->n_op;
354
355 if( canaddr( p->n_left ) && !canaddr( p->n_right ) ) { /* address rhs */
356 if( ro == UMUL ) {
357 offstar( p->n_right->n_left, 0 );
358 return(1);
359 } else {
360 order( p->n_right, INAREG|SOREG );
361 return(1);
362 }
363 }
364 if( !istnode( p->n_left) ) { /* try putting LHS into a reg */
365/* order( p->n_left, logop(p->n_op)?(INAREG|INBREG|INTAREG|INTBREG|SOREG):(INTAREG|INTBREG|SOREG) );*/
366 order( p->n_left, INAREG|INTAREG|INBREG|INTBREG|SOREG );
367 return(1);
368 }
369 else if( ro == UNARY MUL && rt != CHAR && rt != UCHAR ){
370 offstar( p->n_right->n_left );
371 return(1);
372 }
373 else if( rt == CHAR || rt == UCHAR || rt == SHORT || rt == USHORT || (ro != REG &&
374 ro != NAME && ro != OREG && ro != ICON ) ){
375 order( p->n_right, INAREG|INBREG );
376 return(1);
377 }
378/*
379 else if( logop(p->n_op) && rt==USHORT ){ / * must get rhs into register */
380/*
381 order( p->n_right, INAREG );
382 return( 1 );
383 }
384 */
385#endif
386 return(0);
387 }
388
389#if 0
390int
391setstr( p ) register NODE *p; { /* structure assignment */
392 if( p->right->op != REG ){
393 order( p->right, INTAREG );
394 return(1);
395 }
396 p = p->left;
397 if( p->op != NAME && p->op != OREG ){
398 if( p->op != UNARY MUL ) cerror( "bad setstr" );
399 order( p->left, INTAREG );
400 return( 1 );
401 }
402 return( 0 );
403 }
404#endif
405
406int
407setasg( p, s ) register NODE *p; {
408
409#if 0
410 /* setup for assignment operator */
411
412 if( !canaddr(p->n_right) ) {
413 if( p->n_right->n_op == UNARY MUL )
414 offstar(p->n_right->n_left);
415 else
416 order( p->n_right, INAREG|INBREG|SOREG );
417 return(1);
418 }
419 if( p->n_left->n_op == UMUL ) {
420 offstar( p->n_left->n_left );
421 return(1);
422 }
423 if( p->left->op == FLD && p->left->left->op == UNARY MUL ){
424 offstar( p->left->left->left );
425 return(1);
426 }
427/* FLD patch */
428 if( p->left->op == FLD && !(p->right->type==INT || p->right->type==UNSIGNED)) {
429 order( p->right, INAREG);
430 return(1);
431 }
432/* end of FLD patch */
433#endif
434 return(0);
435 }
436
437/* setup for unary operator */
438int
439setuni(NODE *p, int cookie)
440{
441 return 0;
442}
443
444
445#if 0
446int
447setasop( p ) register NODE *p; {
448 /* setup for =ops */
449 register rt, ro;
450
451 rt = p->right->type;
452 ro = p->right->op;
453
454 if( ro == UNARY MUL && rt != CHAR ){
455 offstar( p->right->left );
456 return(1);
457 }
458 if( ( rt == CHAR || rt == SHORT || rt == UCHAR || rt == USHORT ||
459 ( ro != REG && ro != ICON && ro != NAME && ro != OREG ) ) ){
460 order( p->right, INAREG|INBREG );
461 return(1);
462 }
463/*
464 if( (p->op == ASG LS || p->op == ASG RS) && ro != ICON && ro != REG ){
465 order( p->right, INAREG );
466 return(1);
467 }
468 */
469
470
471 p = p->left;
472 if( p->op == FLD ) p = p->left;
473
474 switch( p->op ){
475
476 case REG:
477 case ICON:
478 case NAME:
479 case OREG:
480 return(0);
481
482 case UNARY MUL:
483 if( p->left->op==OREG )
484 return(0);
485 else
486 offstar( p->left );
487 return(1);
488
489 }
490 cerror( "illegal setasop" );
491 }
492#endif
493
494void
495deflab(int l)
496{
497 printf(LABFMT ":\n", l);
498}
499
500#if 0
501genargs( p, ptemp ) register NODE *p, *ptemp; {
502 register NODE *pasg;
503 register align;
504 register size;
505 register TWORD type;
506
507 /* generate code for the arguments */
508
509 /* first, do the arguments on the right */
510 while( p->op == CM ){
511 genargs( p->right, ptemp );
512 p->op = FREE;
513 p = p->left;
514 }
515
516 if( p->op == STARG ){ /* structure valued argument */
517
518 size = p->stsize;
519 align = p->stalign;
520
521 /* ptemp->lval = (ptemp->lval/align)*align; / * SETOFF for negative numbers */
522 ptemp->lval = 0; /* all moves to (sp) */
523
524 p->op = STASG;
525 p->right = p->left;
526 p->left = tcopy( ptemp );
527
528 /* the following line is done only with the knowledge
529 that it will be undone by the STASG node, with the
530 offset (lval) field retained */
531
532 if( p->right->op == OREG ) p->right->op = REG; /* only for temporaries */
533
534 order( p, FORARG );
535 ptemp->lval += size;
536 return;
537 }
538
539 /* ordinary case */
540
541 order( p, FORARG );
542 }
543
544argsize( p ) register NODE *p; {
545 register t;
546 t = 0;
547 if( p->op == CM ){
548 t = argsize( p->left );
549 p = p->right;
550 }
551 if( p->type == DOUBLE || p->type == FLOAT ){
552 SETOFF( t, 4 );
553 return( t+8 );
554 }
555 else if( p->op == STARG ){
556 SETOFF( t, 4 ); /* alignment */
557 return( t + ((p->stsize+3)/4)*4 ); /* size */
558 }
559 else {
560 SETOFF( t, 4 );
561 return( t+4 );
562 }
563 }
564#endif
565
566/*
567 * Special handling of some instruction register allocation.
568 */
569struct rspecial *
570nspecial(struct optab *q)
571{
572 comperr("nspecial");
573 return NULL;
574}
575
576/*
577 * Set evaluation order of a binary node if it differs from default.
578 */
579int
580setorder(NODE *p)
581{
582 return 0; /* nothing differs on vax */
583}
584
585/*
586 * Do the actual conversion of offstar-found OREGs into real OREGs.
587 */
588void
589myormake(NODE *q)
590{
591}
592/*
593 * Set registers "live" at function calls (like arguments in registers).
594 * This is for liveness analysis of registers.
595 */
596int *
597livecall(NODE *p)
598{
599 static int r[1] = { -1 }; /* Terminate with -1 */
600
601 return &r[0];
602}
603
604/*
605 * Signal whether the instruction is acceptable for this target.
606 */
607int
608acceptable(struct optab *op)
609{
610 return 1;
611}
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