source: mainline/libc/arch/mips32/include/atomic.h@ 432c648

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 432c648 was 29a9f62, checked in by Ondrej Palkovsky <ondrap@…>, 19 years ago

Added symbolic links 'libarch','libadt','libipc' into libc/include,
so that it can be easily used from anywhere.
Renamed thread_main to thread_main.
Allowed MIPS to compile with -O0.
Added non-preemptible threads support (not yet secured by futexes).
Added simple way to hold Thread Local Storage. Support for compiler
will be added later.
This update breaks IA64 uspace.

There is some forgotten spinlock_lock() in futexes, amd64 gets locked
in the secod uspace thread probably with preemption disabled.

  • Property mode set to 100644
File size: 2.4 KB
Line 
1/*
2 * Copyright (C) 2005 Ondrej Palkovsky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __mips32_ATOMIC_H__
30#define __mips32_ATOMIC_H__
31
32#define atomic_inc(x) ((void) atomic_add(x, 1))
33#define atomic_dec(x) ((void) atomic_add(x, -1))
34
35#define atomic_postinc(x) (atomic_add(x, 1) - 1)
36#define atomic_postdec(x) (atomic_add(x, -1) + 1)
37
38#define atomic_preinc(x) atomic_add(x, 1)
39#define atomic_predec(x) atomic_add(x, -1)
40
41/* Atomic addition of immediate value.
42 *
43 * @param val Memory location to which will be the immediate value added.
44 * @param i Signed immediate that will be added to *val.
45 *
46 * @return Value after addition.
47 */
48static inline long atomic_add(atomic_t *val, int i)
49{
50 long tmp, v;
51
52 __asm__ volatile (
53 "1:\n"
54 " ll %0, %1\n"
55 " addiu %0, %0, %3\n" /* same as addi, but never traps on overflow */
56 " move %2, %0\n"
57 " sc %0, %1\n"
58 " beq %0, %4, 1b\n" /* if the atomic operation failed, try again */
59 /* nop */ /* nop is inserted automatically by compiler */
60 : "=r" (tmp), "=m" (val->count), "=r" (v)
61 : "i" (i), "i" (0)
62 );
63
64 return v;
65}
66
67#endif
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