source: mainline/kernel/test/fpu/mips2.c@ dff0a94

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since dff0a94 was f272cb8, checked in by Martin Decky <martin@…>, 19 years ago

integrate more tests

  • Property mode set to 100644
File size: 3.5 KB
Line 
1/*
2 * Copyright (C) 2005 Ondrej Palkovsky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <print.h>
30#include <debug.h>
31#include <panic.h>
32
33#include <test.h>
34#include <atomic.h>
35#include <proc/thread.h>
36#include <time/delay.h>
37
38#include <arch.h>
39
40#ifdef mips32
41
42#define THREADS 50
43#define DELAY 10000L
44#define ATTEMPTS 5
45
46static atomic_t threads_ok;
47static waitq_t can_start;
48
49static void testit1(void *data)
50{
51 int i;
52 int arg __attribute__((aligned(16))) = (int)((unative_t) data);
53 int after_arg __attribute__((aligned(16)));
54
55 thread_detach(THREAD);
56
57 waitq_sleep(&can_start);
58
59 for (i = 0; i<ATTEMPTS; i++) {
60 __asm__ volatile (
61 "mtc1 %0,$1"
62 :"=r"(arg)
63 );
64
65 delay(DELAY);
66 __asm__ volatile (
67 "mfc1 %0, $1"
68 :"=r"(after_arg)
69 );
70
71 if(arg != after_arg)
72 panic("General reg tid%d: arg(%d) != %d\n",
73 THREAD->tid, arg, after_arg);
74 }
75
76 atomic_inc(&threads_ok);
77}
78
79static void testit2(void *data)
80{
81 int i;
82 int arg __attribute__((aligned(16))) = (int)((unative_t) data);
83 int after_arg __attribute__((aligned(16)));
84
85 thread_detach(THREAD);
86
87 waitq_sleep(&can_start);
88
89 for (i = 0; i<ATTEMPTS; i++) {
90 __asm__ volatile (
91 "mtc1 %0,$1"
92 :"=r"(arg)
93 );
94
95 scheduler();
96 __asm__ volatile (
97 "mfc1 %0,$1"
98 :"=r"(after_arg)
99 );
100
101 if(arg != after_arg)
102 panic("General reg tid%d: arg(%d) != %d\n",
103 THREAD->tid, arg, after_arg);
104 }
105
106 atomic_inc(&threads_ok);
107}
108
109
110void test_mips2(void)
111{
112 thread_t *t;
113 int i;
114
115 waitq_initialize(&can_start);
116
117 printf("MIPS test #1\n");
118 printf("Creating %d threads... ", THREADS);
119
120 for (i=0; i<THREADS/2; i++) {
121 if (!(t = thread_create(testit1, (void *)((unative_t)i*2), TASK, 0, "testit1")))
122 panic("could not create thread\n");
123 thread_ready(t);
124 if (!(t = thread_create(testit2, (void *)((unative_t)i*2+1), TASK, 0, "testit2")))
125 panic("could not create thread\n");
126 thread_ready(t);
127 }
128
129 printf("ok\n");
130
131 thread_sleep(1);
132 waitq_wakeup(&can_start, WAKEUP_ALL);
133
134 while (atomic_get(&threads_ok) != THREADS)
135 ;
136
137 printf("Test passed.\n");
138}
139
140#else
141
142void test_mips2(void)
143{
144 printf("This test is availaible only on MIPS32 platform.\n");
145}
146
147#endif
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