source: mainline/kernel/kernel.config@ d4b5542

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since d4b5542 was 44d0758, checked in by Jakub Jermar <jakub@…>, 19 years ago

Add option to compile the sparc64 kernel without the TTE_CV bit support.
The bit is not used by default now.
Enabling it may theoretically lead to physical memory inconsistencies until code that
mitigates the problem is written.

  • Property mode set to 100644
File size: 3.7 KB
RevLine 
[34722ee]1## General configuration directives
2
[9371c30]3# Architecture
[36e7b6c3]4@ "amd64" AMD64/Intel EM64T
[fd8af4b]5@ "ia32" Intel IA-32
[57ce359]6@ "ia32xen" Intel IA-32 on Xen hypervisor
[36e7b6c3]7@ "ia64" Intel IA-64
[9371c30]8@ "mips32" MIPS 32-bit
9@ "ppc32" PowerPC 32-bit
[602c9101]10@ "ppc64" PowerPC 64-bit
[41f7564]11@ "sparc64" Sun UltraSPARC 64-bit
[9371c30]12! ARCH (choice)
13
14# Compiler
15@ "cross" Cross-compiler
16@ "native" Native
[41f7564]17! COMPILER (choice)
[9371c30]18
19# CPU type
20@ "pentium4" Pentium 4
21@ "pentium3" Pentium 3
22@ "athlon-xp" Athlon XP
23@ "athlon-mp" Athlon MP
24@ "prescott" Prescott
[57ce359]25! [ARCH=ia32|ARCH=ia32xen] MACHINE (choice)
[41f7564]26
27# CPU type
28@ "opteron" Opteron
29! [ARCH=amd64] MACHINE (choice)
[9371c30]30
[41f7564]31# Machine type
[9371c30]32@ "msim" MSIM Simulator
33@ "simics" Virtutech Simics simulator
34@ "lgxemul" GXEmul Little Endian
35@ "bgxemul" GXEmul Big Endian
36@ "indy" SGI Indy
[41f7564]37! [ARCH=mips32] MACHINE (choice)
[9371c30]38
[bbf5657]39# Framebuffer support
[aecf79f]40! [(ARCH=mips32&MACHINE=lgxemul)|(ARCH=mips32&MACHINE=bgxemul)|(ARCH=ia32)|(ARCH=amd64)] CONFIG_FB (y/n)
[22cf454d]41
42# Framebuffer width
43@ "640"
44@ "800"
45@ "1024"
[b0f8c84]46@ "1152"
[22cf454d]47@ "1280"
[b0f8c84]48@ "1400"
49@ "1440"
[22cf454d]50@ "1600"
51@ "2048"
[aecf79f]52! [(ARCH=ia32|ARCH=amd64)&CONFIG_FB=y] CONFIG_VESA_WIDTH (choice)
[22cf454d]53
54# Framebuffer height
55@ "480"
56@ "600"
57@ "768"
[b0f8c84]58@ "852"
59@ "900"
60@ "960"
[22cf454d]61@ "1024"
[b0f8c84]62@ "1050"
[22cf454d]63@ "1200"
64@ "1536"
[aecf79f]65! [(ARCH=ia32|ARCH=amd64)&CONFIG_FB=y] CONFIG_VESA_HEIGHT (choice)
[22cf454d]66
67# Framebuffer depth
68@ "8"
69@ "16"
70@ "24"
[aecf79f]71! [(ARCH=ia32|ARCH=amd64)&CONFIG_FB=y] CONFIG_VESA_BPP (choice)
[22cf454d]72
[944b15c]73# Support for SMP
[57ce359]74! [ARCH=ia32|ARCH=amd64|ARCH=ia32xen|ARCH=sparc64] CONFIG_SMP (y/n)
[944b15c]75
76# Improved support for hyperthreading
[57ce359]77! [(ARCH=ia32|ARCH=amd64|ARCH=ia32xen)&CONFIG_SMP=y] CONFIG_HT (y/n)
[944b15c]78
[04225a7]79# Simics BIOS AP boot fix
[a0c12f5]80! [(ARCH=ia32|ARCH=amd64)&CONFIG_SMP=y] CONFIG_SIMICS_FIX (y/n)
[04225a7]81
[944b15c]82# Lazy FPU context switching
[57ce359]83! [(ARCH=mips32&MACHINE!=msim&MACHINE!=simics)|ARCH=amd64|ARCH=ia32|ARCH=ia64|ARCH=sparc64|ARCH=ia32xen] CONFIG_FPU_LAZY (y/n)
[944b15c]84
[91d5ad6]85# Power off on halt
[898d9f8]86! [ARCH=ppc32] CONFIG_POWEROFF (n/y)
[91d5ad6]87
[eb353b3]88# Use VHPT
89! [ARCH=ia64] CONFIG_VHPT (n/y)
90
91# Use TSB
92! [ARCH=sparc64] CONFIG_TSB (y/n)
93
94# Support for Z8530 serial port
95! [ARCH=sparc64] CONFIG_Z8530 (y/n)
96
97# Support for NS16550 serial port
98! [ARCH=sparc64] CONFIG_NS16550 (y/n)
99
100# Virtually indexed cache support
[44d0758]101! [ARCH=sparc64] CONFIG_VIRT_IDX_CACHE (n/y)
[eb353b3]102
103
[34722ee]104## Debugging configuration directives
105
106# General debuging and assert checking
107! CONFIG_DEBUG (y/n)
108
109# Deadlock detection support for spinlocks
[b4cad8b2]110! [CONFIG_DEBUG=y&CONFIG_SMP=y] CONFIG_DEBUG_SPINLOCK (y/n)
[34722ee]111
[4e49572]112# Watchpoint on rewriting AS with zero
[57ce359]113! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=ia32|ARCH=ia32xen)] CONFIG_DEBUG_AS_WATCHPOINT (y/n)
[4e49572]114
[8d25b44]115# Save all interrupt registers
[57ce359]116! [CONFIG_DEBUG=y&(ARCH=amd64|ARCH=mips32|ARCH=ia32|ARCH=ia32xen)] CONFIG_DEBUG_ALLREGS (y/n)
[8d25b44]117
[28ecadb]118
[34722ee]119## Run-time configuration directives
120
121# Kernel test type
122@ "" No test
[9a2d6e1]123@ "atomic/atomic1" Test of atomic operations.
[018d957e]124@ "btree/btree1" B-tree test.
[34722ee]125@ "synch/rwlock1" Read write test 1
126@ "synch/rwlock2" Read write test 2
127@ "synch/rwlock3" Read write test 3
128@ "synch/rwlock4" Read write test 4
129@ "synch/rwlock5" Read write test 5
130@ "synch/semaphore1" Semaphore test 1
131@ "synch/semaphore2" Sempahore test 2
[57ce359]132@ [ARCH=ia32|ARCH=amd64|ARCH=ia64|ARCH=ia32xen] "fpu/fpu1" Intel FPU test 1
133@ [ARCH=ia32|ARCH=amd64|ARCH=ia32xen] "fpu/sse1" Intel SSE test 1
[41f7564]134@ [ARCH=mips32&MACHINE!=msim&MACHINE!=simics] "fpu/mips1" MIPS FPU test 1
[34722ee]135@ "print/print1" Printf test 1
[3887b105]136@ "thread/thread1" Thread test 1
[d43d2f7]137@ "mm/mapping1" Mapping test 1
[f275cb3]138@ "mm/falloc1" Frame Allocation test 1
[078a0a1]139@ "mm/falloc2" Frame Allocation test 2
[41f7564]140@ "mm/slab1" SLAB test1 - No CPU cache
[4a5b2b0e]141@ "mm/slab2" SLAB test2 - SMP CPU cache
[4a2b52f]142@ "fault/fault1" Write to NULL (maybe page fault)
[2666daa]143@ "sysinfo" Sysinfo fill and dump test
[bdab828]144@ [ARCH=ia64] "mm/purge1" Itanium TLB purge test
[41f7564]145@ [ARCH=mips32] "debug/mips1" MIPS breakpoint-debug test
[34722ee]146! CONFIG_TEST (choice)
[3783d7d]147
148# Benchmark test
149! [CONFIG_TEST!=] CONFIG_BENCH (y/n)
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