[f761f1eb] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2001-2004 Jakub Jermar
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[f761f1eb] | 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[cc73a8a1] | 29 | /** @addtogroup genericmm
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[b45c443] | 30 | * @{
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| 31 | */
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| 32 |
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[9179d0a] | 33 | /**
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[b45c443] | 34 | * @file
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[da1bafb] | 35 | * @brief Generic TLB shootdown algorithm.
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[2bb8648] | 36 | *
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| 37 | * The algorithm implemented here is based on the CMU TLB shootdown
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| 38 | * algorithm and is further simplified (e.g. all CPUs receive all TLB
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| 39 | * shootdown messages).
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[9179d0a] | 40 | */
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| 41 |
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[f761f1eb] | 42 | #include <mm/tlb.h>
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[d1e414c] | 43 | #include <mm/asid.h>
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[ce031f0] | 44 | #include <arch/mm/tlb.h>
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[4ffa9e0] | 45 | #include <smp/ipi.h>
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[169587a] | 46 | #include <synch/spinlock.h>
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[23684b7] | 47 | #include <atomic.h>
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[4ffa9e0] | 48 | #include <arch/interrupt.h>
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[169587a] | 49 | #include <config.h>
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[434f700] | 50 | #include <arch.h>
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[02055415] | 51 | #include <panic.h>
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[d1e414c] | 52 | #include <debug.h>
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[b3f8fb7] | 53 | #include <cpu.h>
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[f761f1eb] | 54 |
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[169587a] | 55 | void tlb_init(void)
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| 56 | {
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[b00fdde] | 57 | tlb_arch_init();
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[169587a] | 58 | }
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| 59 |
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[5f85c91] | 60 | #ifdef CONFIG_SMP
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[d1e414c] | 61 |
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[da1bafb] | 62 | /**
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| 63 | * This lock is used for synchronisation between sender and
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| 64 | * recipients of TLB shootdown message. It must be acquired
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| 65 | * before CPU structure lock.
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| 66 | *
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| 67 | */
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| 68 | IRQ_SPINLOCK_STATIC_INITIALIZE(tlblock);
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| 69 |
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[d1e414c] | 70 | /** Send TLB shootdown message.
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| 71 | *
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| 72 | * This function attempts to deliver TLB shootdown message
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| 73 | * to all other processors.
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| 74 | *
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[05e3cb8] | 75 | * @param type Type describing scope of shootdown.
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| 76 | * @param asid Address space, if required by type.
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| 77 | * @param page Virtual page address, if required by type.
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| 78 | * @param count Number of pages, if required by type.
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[da1bafb] | 79 | *
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[402eda5] | 80 | * @return The interrupt priority level as it existed prior to this call.
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[05e3cb8] | 81 | *
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[d1e414c] | 82 | */
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[402eda5] | 83 | ipl_t tlb_shootdown_start(tlb_invalidate_type_t type, asid_t asid,
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[98000fb] | 84 | uintptr_t page, size_t count)
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[169587a] | 85 | {
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[05e3cb8] | 86 | ipl_t ipl = interrupts_disable();
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[da1bafb] | 87 | CPU->tlb_active = false;
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[402eda5] | 88 | irq_spinlock_lock(&tlblock, false);
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[4512d7e] | 89 |
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[da1bafb] | 90 | size_t i;
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[d1e414c] | 91 | for (i = 0; i < config.cpu_count; i++) {
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| 92 | if (i == CPU->id)
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| 93 | continue;
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[da1bafb] | 94 |
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[05e3cb8] | 95 | cpu_t *cpu = &cpus[i];
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[49eb681] | 96 |
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[da1bafb] | 97 | irq_spinlock_lock(&cpu->lock, false);
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[d1e414c] | 98 | if (cpu->tlb_messages_count == TLB_MESSAGE_QUEUE_LEN) {
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| 99 | /*
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| 100 | * The message queue is full.
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| 101 | * Erase the queue and store one TLB_INVL_ALL message.
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| 102 | */
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| 103 | cpu->tlb_messages_count = 1;
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| 104 | cpu->tlb_messages[0].type = TLB_INVL_ALL;
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| 105 | cpu->tlb_messages[0].asid = ASID_INVALID;
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| 106 | cpu->tlb_messages[0].page = 0;
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| 107 | cpu->tlb_messages[0].count = 0;
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| 108 | } else {
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| 109 | /*
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| 110 | * Enqueue the message.
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| 111 | */
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[98000fb] | 112 | size_t idx = cpu->tlb_messages_count++;
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[4638401] | 113 | cpu->tlb_messages[idx].type = type;
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| 114 | cpu->tlb_messages[idx].asid = asid;
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| 115 | cpu->tlb_messages[idx].page = page;
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| 116 | cpu->tlb_messages[idx].count = count;
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[d1e414c] | 117 | }
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[da1bafb] | 118 | irq_spinlock_unlock(&cpu->lock, false);
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[d1e414c] | 119 | }
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[36b01bb2] | 120 |
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[b109ebb] | 121 | tlb_shootdown_ipi_send();
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[da1bafb] | 122 |
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| 123 | busy_wait:
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[49eb681] | 124 | for (i = 0; i < config.cpu_count; i++) {
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[434f700] | 125 | if (cpus[i].tlb_active)
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| 126 | goto busy_wait;
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[49eb681] | 127 | }
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[05e3cb8] | 128 |
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[402eda5] | 129 | return ipl;
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[169587a] | 130 | }
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| 131 |
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[da1bafb] | 132 | /** Finish TLB shootdown sequence.
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| 133 | *
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[05e3cb8] | 134 | * @param ipl Previous interrupt priority level.
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| 135 | *
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[da1bafb] | 136 | */
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[402eda5] | 137 | void tlb_shootdown_finalize(ipl_t ipl)
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[169587a] | 138 | {
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[402eda5] | 139 | irq_spinlock_unlock(&tlblock, false);
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[da1bafb] | 140 | CPU->tlb_active = true;
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[402eda5] | 141 | interrupts_restore(ipl);
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[169587a] | 142 | }
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| 143 |
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[4ffa9e0] | 144 | void tlb_shootdown_ipi_send(void)
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| 145 | {
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| 146 | ipi_broadcast(VECTOR_TLB_SHOOTDOWN_IPI);
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| 147 | }
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| 148 |
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[da1bafb] | 149 | /** Receive TLB shootdown message.
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| 150 | *
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| 151 | */
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[b109ebb] | 152 | void tlb_shootdown_ipi_recv(void)
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[f761f1eb] | 153 | {
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[97b64c9] | 154 | ASSERT(CPU);
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| 155 |
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[da1bafb] | 156 | CPU->tlb_active = false;
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| 157 | irq_spinlock_lock(&tlblock, false);
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| 158 | irq_spinlock_unlock(&tlblock, false);
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[d1e414c] | 159 |
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[da1bafb] | 160 | irq_spinlock_lock(&CPU->lock, false);
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[d1e414c] | 161 | ASSERT(CPU->tlb_messages_count <= TLB_MESSAGE_QUEUE_LEN);
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[da1bafb] | 162 |
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| 163 | size_t i;
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[9432f08] | 164 | for (i = 0; i < CPU->tlb_messages_count; i++) {
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[da1bafb] | 165 | tlb_invalidate_type_t type = CPU->tlb_messages[i].type;
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| 166 | asid_t asid = CPU->tlb_messages[i].asid;
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| 167 | uintptr_t page = CPU->tlb_messages[i].page;
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| 168 | size_t count = CPU->tlb_messages[i].count;
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| 169 |
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[d1e414c] | 170 | switch (type) {
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[00b38a3] | 171 | case TLB_INVL_ALL:
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[d1e414c] | 172 | tlb_invalidate_all();
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| 173 | break;
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[00b38a3] | 174 | case TLB_INVL_ASID:
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[d1e414c] | 175 | tlb_invalidate_asid(asid);
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| 176 | break;
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[00b38a3] | 177 | case TLB_INVL_PAGES:
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[da1bafb] | 178 | ASSERT(count);
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[d1e414c] | 179 | tlb_invalidate_pages(asid, page, count);
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| 180 | break;
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[00b38a3] | 181 | default:
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[f651e80] | 182 | panic("Unknown type (%d).", type);
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[d1e414c] | 183 | break;
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| 184 | }
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[da1bafb] | 185 |
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[d1e414c] | 186 | if (type == TLB_INVL_ALL)
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| 187 | break;
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| 188 | }
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| 189 |
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[9432f08] | 190 | CPU->tlb_messages_count = 0;
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[da1bafb] | 191 | irq_spinlock_unlock(&CPU->lock, false);
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| 192 | CPU->tlb_active = true;
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[f761f1eb] | 193 | }
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[d1e414c] | 194 |
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[5f85c91] | 195 | #endif /* CONFIG_SMP */
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[b45c443] | 196 |
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[cc73a8a1] | 197 | /** @}
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[b45c443] | 198 | */
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