[162f919] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2006 Ondrej Palkovsky
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| 3 | * Copyright (c) 2006 Jakub Jermar
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[162f919] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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[cc73a8a1] | 30 | /** @addtogroup genericipc
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[b45c443] | 31 | * @{
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| 32 | */
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[da1bafb] | 33 |
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[cc73a8a1] | 34 | /**
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| 35 | * @file
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| 36 | * @brief IRQ notification framework.
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[bdc5c516] | 37 | *
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[8820544] | 38 | * This framework allows applications to subscribe to receive a notification
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[a5d0143] | 39 | * when an interrupt is detected. The application may provide a simple
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| 40 | * 'top-half' handler as part of its registration, which can perform simple
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| 41 | * operations (read/write port/memory, add information to notification IPC
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| 42 | * message).
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[bdc5c516] | 43 | *
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| 44 | * The structure of a notification message is as follows:
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[8820544] | 45 | * - IMETHOD: interface and method as set by the SYS_IPC_IRQ_SUBSCRIBE syscall
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[56c167c] | 46 | * - ARG1: payload modified by a 'top-half' handler (scratch[1])
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| 47 | * - ARG2: payload modified by a 'top-half' handler (scratch[2])
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| 48 | * - ARG3: payload modified by a 'top-half' handler (scratch[3])
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| 49 | * - ARG4: payload modified by a 'top-half' handler (scratch[4])
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| 50 | * - ARG5: payload modified by a 'top-half' handler (scratch[5])
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[43752b6] | 51 | * - in_phone_hash: interrupt counter (may be needed to assure correct order
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[228e490] | 52 | * in multithreaded drivers)
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[bdc5c516] | 53 | */
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| 54 |
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[162f919] | 55 | #include <arch.h>
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[63e27ef] | 56 | #include <assert.h>
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[162f919] | 57 | #include <mm/slab.h>
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[a996ae31] | 58 | #include <mm/page.h>
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| 59 | #include <mm/km.h>
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[162f919] | 60 | #include <errno.h>
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[2b017ba] | 61 | #include <ddi/irq.h>
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[162f919] | 62 | #include <ipc/ipc.h>
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| 63 | #include <ipc/irq.h>
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[e3c762cd] | 64 | #include <syscall/copy.h>
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[d0c5901] | 65 | #include <console/console.h>
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[253f35a1] | 66 | #include <print.h>
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[a996ae31] | 67 | #include <macros.h>
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[3f74275] | 68 | #include <cap/cap.h>
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[a996ae31] | 69 |
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| 70 | static void ranges_unmap(irq_pio_range_t *ranges, size_t rangecount)
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| 71 | {
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[56c167c] | 72 | for (size_t i = 0; i < rangecount; i++) {
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[472d813] | 73 | #ifdef IO_SPACE_BOUNDARY
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[a996ae31] | 74 | if ((void *) ranges[i].base >= IO_SPACE_BOUNDARY)
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[472d813] | 75 | #endif
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[a996ae31] | 76 | km_unmap(ranges[i].base, ranges[i].size);
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| 77 | }
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| 78 | }
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| 79 |
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| 80 | static int ranges_map_and_apply(irq_pio_range_t *ranges, size_t rangecount,
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| 81 | irq_cmd_t *cmds, size_t cmdcount)
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| 82 | {
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| 83 | /* Copy the physical base addresses aside. */
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[56c167c] | 84 | uintptr_t *pbase = malloc(rangecount * sizeof(uintptr_t), 0);
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| 85 | for (size_t i = 0; i < rangecount; i++)
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[a996ae31] | 86 | pbase[i] = ranges[i].base;
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[56c167c] | 87 |
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[a996ae31] | 88 | /* Map the PIO ranges into the kernel virtual address space. */
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[56c167c] | 89 | for (size_t i = 0; i < rangecount; i++) {
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[472d813] | 90 | #ifdef IO_SPACE_BOUNDARY
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[a996ae31] | 91 | if ((void *) ranges[i].base < IO_SPACE_BOUNDARY)
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| 92 | continue;
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[472d813] | 93 | #endif
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[a996ae31] | 94 | ranges[i].base = km_map(pbase[i], ranges[i].size,
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| 95 | PAGE_READ | PAGE_WRITE | PAGE_KERNEL | PAGE_NOT_CACHEABLE);
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| 96 | if (!ranges[i].base) {
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| 97 | ranges_unmap(ranges, i);
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| 98 | free(pbase);
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| 99 | return ENOMEM;
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| 100 | }
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| 101 | }
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[56c167c] | 102 |
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[a5d0143] | 103 | /* Rewrite the IRQ code addresses from physical to kernel virtual. */
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[56c167c] | 104 | for (size_t i = 0; i < cmdcount; i++) {
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[a996ae31] | 105 | uintptr_t addr;
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[f2bbe8c] | 106 | size_t size;
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[56c167c] | 107 |
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[a996ae31] | 108 | /* Process only commands that use an address. */
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| 109 | switch (cmds[i].cmd) {
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| 110 | case CMD_PIO_READ_8:
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[56c167c] | 111 | case CMD_PIO_WRITE_8:
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| 112 | case CMD_PIO_WRITE_A_8:
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[f2bbe8c] | 113 | size = 1;
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| 114 | break;
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[56c167c] | 115 | case CMD_PIO_READ_16:
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| 116 | case CMD_PIO_WRITE_16:
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| 117 | case CMD_PIO_WRITE_A_16:
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[f2bbe8c] | 118 | size = 2;
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| 119 | break;
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[56c167c] | 120 | case CMD_PIO_READ_32:
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| 121 | case CMD_PIO_WRITE_32:
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| 122 | case CMD_PIO_WRITE_A_32:
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[f2bbe8c] | 123 | size = 4;
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[a996ae31] | 124 | break;
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| 125 | default:
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| 126 | /* Move onto the next command. */
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| 127 | continue;
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| 128 | }
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[56c167c] | 129 |
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[a996ae31] | 130 | addr = (uintptr_t) cmds[i].addr;
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| 131 |
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[56c167c] | 132 | size_t j;
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[a996ae31] | 133 | for (j = 0; j < rangecount; j++) {
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| 134 | /* Find the matching range. */
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[f2bbe8c] | 135 | if (!iswithin(pbase[j], ranges[j].size, addr, size))
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[a996ae31] | 136 | continue;
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[56c167c] | 137 |
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[a996ae31] | 138 | /* Switch the command to a kernel virtual address. */
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| 139 | addr -= pbase[j];
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| 140 | addr += ranges[j].base;
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[56c167c] | 141 |
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[a996ae31] | 142 | cmds[i].addr = (void *) addr;
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| 143 | break;
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[bd8c6537] | 144 | }
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[56c167c] | 145 |
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[bd8c6537] | 146 | if (j == rangecount) {
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| 147 | /*
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| 148 | * The address used in this command is outside of all
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| 149 | * defined ranges.
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| 150 | */
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| 151 | ranges_unmap(ranges, rangecount);
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| 152 | free(pbase);
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| 153 | return EINVAL;
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| 154 | }
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[a996ae31] | 155 | }
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[56c167c] | 156 |
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[a996ae31] | 157 | free(pbase);
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| 158 | return EOK;
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| 159 | }
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[162f919] | 160 |
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[a5d0143] | 161 | /** Statically check the top-half IRQ code
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[8486c07] | 162 | *
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[a5d0143] | 163 | * Check the top-half IRQ code for invalid or unsafe constructs.
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[8486c07] | 164 | *
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| 165 | */
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| 166 | static int code_check(irq_cmd_t *cmds, size_t cmdcount)
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| 167 | {
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| 168 | for (size_t i = 0; i < cmdcount; i++) {
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| 169 | /*
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| 170 | * Check for accepted ranges.
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| 171 | */
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| 172 | if (cmds[i].cmd >= CMD_LAST)
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| 173 | return EINVAL;
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| 174 |
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| 175 | if (cmds[i].srcarg >= IPC_CALL_LEN)
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| 176 | return EINVAL;
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| 177 |
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| 178 | if (cmds[i].dstarg >= IPC_CALL_LEN)
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| 179 | return EINVAL;
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| 180 |
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| 181 | switch (cmds[i].cmd) {
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| 182 | case CMD_PREDICATE:
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| 183 | /*
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| 184 | * Check for control flow overflow.
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| 185 | * Note that jumping just beyond the last
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| 186 | * command is a correct behaviour.
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| 187 | */
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| 188 | if (i + cmds[i].value > cmdcount)
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| 189 | return EINVAL;
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| 190 |
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| 191 | break;
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| 192 | default:
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| 193 | break;
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| 194 | }
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| 195 | }
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| 196 |
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| 197 | return EOK;
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| 198 | }
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| 199 |
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[a5d0143] | 200 | /** Free the top-half IRQ code.
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[8b243f2] | 201 | *
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[a5d0143] | 202 | * @param code Pointer to the top-half IRQ code.
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[da1bafb] | 203 | *
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[8b243f2] | 204 | */
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[162f919] | 205 | static void code_free(irq_code_t *code)
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| 206 | {
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| 207 | if (code) {
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[a996ae31] | 208 | ranges_unmap(code->ranges, code->rangecount);
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| 209 | free(code->ranges);
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[162f919] | 210 | free(code->cmds);
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| 211 | free(code);
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| 212 | }
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| 213 | }
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| 214 |
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[a5d0143] | 215 | /** Copy the top-half IRQ code from userspace into the kernel.
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[8b243f2] | 216 | *
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[a5d0143] | 217 | * @param ucode Userspace address of the top-half IRQ code.
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[da1bafb] | 218 | *
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[a5d0143] | 219 | * @return Kernel address of the copied IRQ code.
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[8b243f2] | 220 | *
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| 221 | */
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| 222 | static irq_code_t *code_from_uspace(irq_code_t *ucode)
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[162f919] | 223 | {
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[a996ae31] | 224 | irq_pio_range_t *ranges = NULL;
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| 225 | irq_cmd_t *cmds = NULL;
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[56c167c] | 226 |
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[da1bafb] | 227 | irq_code_t *code = malloc(sizeof(*code), 0);
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| 228 | int rc = copy_from_uspace(code, ucode, sizeof(*code));
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[a996ae31] | 229 | if (rc != EOK)
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| 230 | goto error;
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[162f919] | 231 |
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[a996ae31] | 232 | if ((code->rangecount > IRQ_MAX_RANGE_COUNT) ||
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| 233 | (code->cmdcount > IRQ_MAX_PROG_SIZE))
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| 234 | goto error;
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[da1bafb] | 235 |
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[a996ae31] | 236 | ranges = malloc(sizeof(code->ranges[0]) * code->rangecount, 0);
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| 237 | rc = copy_from_uspace(ranges, code->ranges,
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| 238 | sizeof(code->ranges[0]) * code->rangecount);
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| 239 | if (rc != EOK)
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| 240 | goto error;
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[56c167c] | 241 |
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[a996ae31] | 242 | cmds = malloc(sizeof(code->cmds[0]) * code->cmdcount, 0);
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| 243 | rc = copy_from_uspace(cmds, code->cmds,
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[8b243f2] | 244 | sizeof(code->cmds[0]) * code->cmdcount);
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[a996ae31] | 245 | if (rc != EOK)
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| 246 | goto error;
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[8486c07] | 247 |
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| 248 | rc = code_check(cmds, code->cmdcount);
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| 249 | if (rc != EOK)
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| 250 | goto error;
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| 251 |
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[a996ae31] | 252 | rc = ranges_map_and_apply(ranges, code->rangecount, cmds,
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| 253 | code->cmdcount);
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| 254 | if (rc != EOK)
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| 255 | goto error;
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[56c167c] | 256 |
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[a996ae31] | 257 | code->ranges = ranges;
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| 258 | code->cmds = cmds;
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[56c167c] | 259 |
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[162f919] | 260 | return code;
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[56c167c] | 261 |
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[a996ae31] | 262 | error:
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| 263 | if (cmds)
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| 264 | free(cmds);
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[56c167c] | 265 |
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[a996ae31] | 266 | if (ranges)
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| 267 | free(ranges);
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[56c167c] | 268 |
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[a996ae31] | 269 | free(code);
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| 270 | return NULL;
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[162f919] | 271 | }
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| 272 |
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[c1f68b0] | 273 | static void irq_hash_out(irq_t *irq)
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| 274 | {
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| 275 | irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
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| 276 | irq_spinlock_lock(&irq->lock, false);
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| 277 |
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| 278 | if (irq->notif_cfg.hashed_in) {
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| 279 | /* Remove the IRQ from the uspace IRQ hash table. */
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| 280 | hash_table_remove_item(&irq_uspace_hash_table, &irq->link);
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| 281 | irq->notif_cfg.hashed_in = false;
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| 282 | }
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| 283 |
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| 284 | irq_spinlock_unlock(&irq->lock, false);
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| 285 | irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
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| 286 | }
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| 287 |
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[48bcf49] | 288 | static void irq_destroy(void *arg)
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| 289 | {
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| 290 | irq_t *irq = (irq_t *) arg;
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| 291 |
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[c1f68b0] | 292 | irq_hash_out(irq);
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| 293 |
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[48bcf49] | 294 | /* Free up the IRQ code and associated structures. */
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| 295 | code_free(irq->notif_cfg.code);
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| 296 | slab_free(irq_slab, irq);
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| 297 | }
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| 298 |
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| 299 | static kobject_ops_t irq_kobject_ops = {
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| 300 | .destroy = irq_destroy
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| 301 | };
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| 302 |
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[8820544] | 303 | /** Subscribe an answerbox as a receiving end for IRQ notifications.
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[2b017ba] | 304 | *
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[56c167c] | 305 | * @param box Receiving answerbox.
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| 306 | * @param inr IRQ number.
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[a5d0143] | 307 | * @param imethod Interface and method to be associated with the notification.
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| 308 | * @param ucode Uspace pointer to top-half IRQ code.
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[56c167c] | 309 | *
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[3f74275] | 310 | * @return IRQ capability handle.
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[e9d15d9] | 311 | * @return Negative error code.
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[2b017ba] | 312 | *
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| 313 | */
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[24abb85d] | 314 | int ipc_irq_subscribe(answerbox_t *box, inr_t inr, sysarg_t imethod,
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| 315 | irq_code_t *ucode)
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[162f919] | 316 | {
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[78ffb70] | 317 | if ((inr < 0) || (inr > last_inr))
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| 318 | return ELIMIT;
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[c822026] | 319 |
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[da1bafb] | 320 | irq_code_t *code;
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[162f919] | 321 | if (ucode) {
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| 322 | code = code_from_uspace(ucode);
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| 323 | if (!code)
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| 324 | return EBADMEM;
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[da1bafb] | 325 | } else
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[162f919] | 326 | code = NULL;
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[c822026] | 327 |
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[cecb0789] | 328 | /*
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[e9d15d9] | 329 | * Allocate and populate the IRQ kernel object.
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[cecb0789] | 330 | */
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[48bcf49] | 331 | cap_handle_t handle = cap_alloc(TASK);
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[3f74275] | 332 | if (handle < 0)
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| 333 | return handle;
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[63d8f43] | 334 |
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[431c402] | 335 | irq_t *irq = (irq_t *) slab_alloc(irq_slab, FRAME_ATOMIC);
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[63d8f43] | 336 | if (!irq) {
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| 337 | cap_free(TASK, handle);
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| 338 | return ENOMEM;
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| 339 | }
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[48bcf49] | 340 |
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| 341 | kobject_t *kobject = malloc(sizeof(kobject_t), FRAME_ATOMIC);
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| 342 | if (!kobject) {
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| 343 | cap_free(TASK, handle);
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| 344 | slab_free(irq_slab, irq);
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| 345 | return ENOMEM;
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| 346 | }
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[63d8f43] | 347 |
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[cecb0789] | 348 | irq_initialize(irq);
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| 349 | irq->inr = inr;
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| 350 | irq->claim = ipc_irq_top_half_claim;
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[691eb52] | 351 | irq->handler = ipc_irq_top_half_handler;
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[4874c2d] | 352 | irq->notif_cfg.notify = true;
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[2b017ba] | 353 | irq->notif_cfg.answerbox = box;
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[228e490] | 354 | irq->notif_cfg.imethod = imethod;
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[2b017ba] | 355 | irq->notif_cfg.code = code;
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| 356 | irq->notif_cfg.counter = 0;
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[c822026] | 357 |
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[cecb0789] | 358 | /*
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[9e87562] | 359 | * Insert the IRQ structure into the uspace IRQ hash table.
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[cecb0789] | 360 | */
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[da1bafb] | 361 | irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
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| 362 | irq_spinlock_lock(&irq->lock, false);
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| 363 |
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[48bcf49] | 364 | irq->notif_cfg.hashed_in = true;
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[82cbf8c6] | 365 | hash_table_insert(&irq_uspace_hash_table, &irq->link);
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[c822026] | 366 |
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[da1bafb] | 367 | irq_spinlock_unlock(&irq->lock, false);
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| 368 | irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
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[9e87562] | 369 |
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[48bcf49] | 370 | kobject_initialize(kobject, KOBJECT_TYPE_IRQ, irq, &irq_kobject_ops);
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| 371 | cap_publish(TASK, handle, kobject);
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[da1bafb] | 372 |
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[3f74275] | 373 | return handle;
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[cecb0789] | 374 | }
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| 375 |
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[8820544] | 376 | /** Unsubscribe task from IRQ notification.
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[cecb0789] | 377 | *
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[3f74275] | 378 | * @param box Answerbox associated with the notification.
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| 379 | * @param handle IRQ capability handle.
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[56c167c] | 380 | *
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| 381 | * @return EOK on success or a negative error code.
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| 382 | *
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[cecb0789] | 383 | */
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[3f74275] | 384 | int ipc_irq_unsubscribe(answerbox_t *box, int handle)
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[cecb0789] | 385 | {
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[48bcf49] | 386 | kobject_t *kobj = cap_unpublish(TASK, handle, KOBJECT_TYPE_IRQ);
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| 387 | if (!kobj)
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[cecb0789] | 388 | return ENOENT;
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[9306cd7] | 389 |
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[48bcf49] | 390 | assert(kobj->irq->notif_cfg.answerbox == box);
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| 391 |
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[c1f68b0] | 392 | irq_hash_out(kobj->irq);
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[48bcf49] | 393 |
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| 394 | kobject_put(kobj);
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[3f74275] | 395 | cap_free(TASK, handle);
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[cecb0789] | 396 |
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| 397 | return EOK;
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| 398 | }
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| 399 |
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[8b243f2] | 400 | /** Add a call to the proper answerbox queue.
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[2b017ba] | 401 | *
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[da1bafb] | 402 | * Assume irq->lock is locked and interrupts disabled.
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| 403 | *
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| 404 | * @param irq IRQ structure referencing the target answerbox.
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| 405 | * @param call IRQ notification call.
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[874621f] | 406 | *
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[2b017ba] | 407 | */
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| 408 | static void send_call(irq_t *irq, call_t *call)
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[874621f] | 409 | {
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[da1bafb] | 410 | irq_spinlock_lock(&irq->notif_cfg.answerbox->irq_lock, false);
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[cfaa35a] | 411 | list_append(&call->ab_link, &irq->notif_cfg.answerbox->irq_notifs);
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[da1bafb] | 412 | irq_spinlock_unlock(&irq->notif_cfg.answerbox->irq_lock, false);
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| 413 |
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[2b017ba] | 414 | waitq_wakeup(&irq->notif_cfg.answerbox->wq, WAKEUP_FIRST);
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[874621f] | 415 | }
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| 416 |
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[a5d0143] | 417 | /** Apply the top-half IRQ code to find out whether to accept the IRQ or not.
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[874621f] | 418 | *
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[da1bafb] | 419 | * @param irq IRQ structure.
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| 420 | *
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[a5d0143] | 421 | * @return IRQ_ACCEPT if the interrupt is accepted by the IRQ code.
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| 422 | * @return IRQ_DECLINE if the interrupt is not accepted byt the IRQ code.
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[cecb0789] | 423 | *
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[874621f] | 424 | */
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[cecb0789] | 425 | irq_ownership_t ipc_irq_top_half_claim(irq_t *irq)
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[874621f] | 426 | {
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[cecb0789] | 427 | irq_code_t *code = irq->notif_cfg.code;
|
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[da1bafb] | 428 | uint32_t *scratch = irq->notif_cfg.scratch;
|
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[cecb0789] | 429 |
|
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| 430 | if (!irq->notif_cfg.notify)
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| 431 | return IRQ_DECLINE;
|
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| 432 |
|
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| 433 | if (!code)
|
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| 434 | return IRQ_DECLINE;
|
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| 435 |
|
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[01e39cbe] | 436 | for (size_t i = 0; i < code->cmdcount; i++) {
|
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[da1bafb] | 437 | uintptr_t srcarg = code->cmds[i].srcarg;
|
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| 438 | uintptr_t dstarg = code->cmds[i].dstarg;
|
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[874621f] | 439 |
|
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[cecb0789] | 440 | switch (code->cmds[i].cmd) {
|
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| 441 | case CMD_PIO_READ_8:
|
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[8486c07] | 442 | scratch[dstarg] =
|
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| 443 | pio_read_8((ioport8_t *) code->cmds[i].addr);
|
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[cecb0789] | 444 | break;
|
---|
| 445 | case CMD_PIO_READ_16:
|
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[8486c07] | 446 | scratch[dstarg] =
|
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| 447 | pio_read_16((ioport16_t *) code->cmds[i].addr);
|
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[cecb0789] | 448 | break;
|
---|
| 449 | case CMD_PIO_READ_32:
|
---|
[8486c07] | 450 | scratch[dstarg] =
|
---|
| 451 | pio_read_32((ioport32_t *) code->cmds[i].addr);
|
---|
[cecb0789] | 452 | break;
|
---|
| 453 | case CMD_PIO_WRITE_8:
|
---|
| 454 | pio_write_8((ioport8_t *) code->cmds[i].addr,
|
---|
| 455 | (uint8_t) code->cmds[i].value);
|
---|
| 456 | break;
|
---|
| 457 | case CMD_PIO_WRITE_16:
|
---|
| 458 | pio_write_16((ioport16_t *) code->cmds[i].addr,
|
---|
| 459 | (uint16_t) code->cmds[i].value);
|
---|
| 460 | break;
|
---|
| 461 | case CMD_PIO_WRITE_32:
|
---|
| 462 | pio_write_32((ioport32_t *) code->cmds[i].addr,
|
---|
| 463 | (uint32_t) code->cmds[i].value);
|
---|
| 464 | break;
|
---|
[9cdac5a] | 465 | case CMD_PIO_WRITE_A_8:
|
---|
[8486c07] | 466 | pio_write_8((ioport8_t *) code->cmds[i].addr,
|
---|
| 467 | (uint8_t) scratch[srcarg]);
|
---|
[9cdac5a] | 468 | break;
|
---|
| 469 | case CMD_PIO_WRITE_A_16:
|
---|
[8486c07] | 470 | pio_write_16((ioport16_t *) code->cmds[i].addr,
|
---|
| 471 | (uint16_t) scratch[srcarg]);
|
---|
[9cdac5a] | 472 | break;
|
---|
| 473 | case CMD_PIO_WRITE_A_32:
|
---|
[8486c07] | 474 | pio_write_32((ioport32_t *) code->cmds[i].addr,
|
---|
| 475 | (uint32_t) scratch[srcarg]);
|
---|
| 476 | break;
|
---|
| 477 | case CMD_LOAD:
|
---|
| 478 | scratch[dstarg] = code->cmds[i].value;
|
---|
[9cdac5a] | 479 | break;
|
---|
[8486c07] | 480 | case CMD_AND:
|
---|
| 481 | scratch[dstarg] = scratch[srcarg] &
|
---|
| 482 | code->cmds[i].value;
|
---|
[cecb0789] | 483 | break;
|
---|
| 484 | case CMD_PREDICATE:
|
---|
[8486c07] | 485 | if (scratch[srcarg] == 0)
|
---|
[cecb0789] | 486 | i += code->cmds[i].value;
|
---|
[8486c07] | 487 |
|
---|
[cecb0789] | 488 | break;
|
---|
| 489 | case CMD_ACCEPT:
|
---|
| 490 | return IRQ_ACCEPT;
|
---|
| 491 | case CMD_DECLINE:
|
---|
| 492 | default:
|
---|
| 493 | return IRQ_DECLINE;
|
---|
| 494 | }
|
---|
[874621f] | 495 | }
|
---|
[01e39cbe] | 496 |
|
---|
[cecb0789] | 497 | return IRQ_DECLINE;
|
---|
[874621f] | 498 | }
|
---|
| 499 |
|
---|
[cecb0789] | 500 | /* IRQ top-half handler.
|
---|
[162f919] | 501 | *
|
---|
[2b017ba] | 502 | * We expect interrupts to be disabled and the irq->lock already held.
|
---|
[8b243f2] | 503 | *
|
---|
[da1bafb] | 504 | * @param irq IRQ structure.
|
---|
| 505 | *
|
---|
[162f919] | 506 | */
|
---|
[cecb0789] | 507 | void ipc_irq_top_half_handler(irq_t *irq)
|
---|
[162f919] | 508 | {
|
---|
[63e27ef] | 509 | assert(irq);
|
---|
[56c167c] | 510 |
|
---|
[63e27ef] | 511 | assert(interrupts_disabled());
|
---|
| 512 | assert(irq_spinlock_locked(&irq->lock));
|
---|
[da1bafb] | 513 |
|
---|
[2b017ba] | 514 | if (irq->notif_cfg.answerbox) {
|
---|
[da1bafb] | 515 | call_t *call = ipc_call_alloc(FRAME_ATOMIC);
|
---|
[cecb0789] | 516 | if (!call)
|
---|
[d8f7362] | 517 | return;
|
---|
[cecb0789] | 518 |
|
---|
[162f919] | 519 | call->flags |= IPC_CALL_NOTIF;
|
---|
[43752b6] | 520 | /* Put a counter to the message */
|
---|
[0c1a5d8a] | 521 | call->priv = ++irq->notif_cfg.counter;
|
---|
[da1bafb] | 522 |
|
---|
[43752b6] | 523 | /* Set up args */
|
---|
[228e490] | 524 | IPC_SET_IMETHOD(call->data, irq->notif_cfg.imethod);
|
---|
[cecb0789] | 525 | IPC_SET_ARG1(call->data, irq->notif_cfg.scratch[1]);
|
---|
| 526 | IPC_SET_ARG2(call->data, irq->notif_cfg.scratch[2]);
|
---|
| 527 | IPC_SET_ARG3(call->data, irq->notif_cfg.scratch[3]);
|
---|
| 528 | IPC_SET_ARG4(call->data, irq->notif_cfg.scratch[4]);
|
---|
| 529 | IPC_SET_ARG5(call->data, irq->notif_cfg.scratch[5]);
|
---|
[da1bafb] | 530 |
|
---|
[2b017ba] | 531 | send_call(irq, call);
|
---|
[162f919] | 532 | }
|
---|
| 533 | }
|
---|
| 534 |
|
---|
[cecb0789] | 535 | /** Send notification message.
|
---|
[874621f] | 536 | *
|
---|
[da1bafb] | 537 | * @param irq IRQ structure.
|
---|
| 538 | * @param a1 Driver-specific payload argument.
|
---|
| 539 | * @param a2 Driver-specific payload argument.
|
---|
| 540 | * @param a3 Driver-specific payload argument.
|
---|
| 541 | * @param a4 Driver-specific payload argument.
|
---|
| 542 | * @param a5 Driver-specific payload argument.
|
---|
| 543 | *
|
---|
[162f919] | 544 | */
|
---|
[96b02eb9] | 545 | void ipc_irq_send_msg(irq_t *irq, sysarg_t a1, sysarg_t a2, sysarg_t a3,
|
---|
| 546 | sysarg_t a4, sysarg_t a5)
|
---|
[162f919] | 547 | {
|
---|
[da1bafb] | 548 | irq_spinlock_lock(&irq->lock, true);
|
---|
| 549 |
|
---|
[cecb0789] | 550 | if (irq->notif_cfg.answerbox) {
|
---|
[da1bafb] | 551 | call_t *call = ipc_call_alloc(FRAME_ATOMIC);
|
---|
[cecb0789] | 552 | if (!call) {
|
---|
[da1bafb] | 553 | irq_spinlock_unlock(&irq->lock, true);
|
---|
[cecb0789] | 554 | return;
|
---|
[b14e35f2] | 555 | }
|
---|
[da1bafb] | 556 |
|
---|
[cecb0789] | 557 | call->flags |= IPC_CALL_NOTIF;
|
---|
| 558 | /* Put a counter to the message */
|
---|
| 559 | call->priv = ++irq->notif_cfg.counter;
|
---|
[da1bafb] | 560 |
|
---|
[228e490] | 561 | IPC_SET_IMETHOD(call->data, irq->notif_cfg.imethod);
|
---|
[cecb0789] | 562 | IPC_SET_ARG1(call->data, a1);
|
---|
| 563 | IPC_SET_ARG2(call->data, a2);
|
---|
| 564 | IPC_SET_ARG3(call->data, a3);
|
---|
| 565 | IPC_SET_ARG4(call->data, a4);
|
---|
| 566 | IPC_SET_ARG5(call->data, a5);
|
---|
| 567 |
|
---|
| 568 | send_call(irq, call);
|
---|
[b14e35f2] | 569 | }
|
---|
[da1bafb] | 570 |
|
---|
| 571 | irq_spinlock_unlock(&irq->lock, true);
|
---|
[162f919] | 572 | }
|
---|
[b45c443] | 573 |
|
---|
[cc73a8a1] | 574 | /** @}
|
---|
[b45c443] | 575 | */
|
---|