source: mainline/kernel/generic/src/ipc/irq.c@ 8a45bf09

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 8a45bf09 was 8a45bf09, checked in by Jakub Jermar <jakub@…>, 8 years ago

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[162f919]1/*
[df4ed85]2 * Copyright (c) 2006 Ondrej Palkovsky
3 * Copyright (c) 2006 Jakub Jermar
[162f919]4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
[cc73a8a1]30/** @addtogroup genericipc
[b45c443]31 * @{
32 */
[da1bafb]33
[cc73a8a1]34/**
35 * @file
36 * @brief IRQ notification framework.
[bdc5c516]37 *
[8820544]38 * This framework allows applications to subscribe to receive a notification
[bdc5c516]39 * when interrupt is detected. The application may provide a simple 'top-half'
40 * handler as part of its registration, which can perform simple operations
[56c167c]41 * (read/write port/memory, add information to notification IPC message).
[bdc5c516]42 *
43 * The structure of a notification message is as follows:
[8820544]44 * - IMETHOD: interface and method as set by the SYS_IPC_IRQ_SUBSCRIBE syscall
[56c167c]45 * - ARG1: payload modified by a 'top-half' handler (scratch[1])
46 * - ARG2: payload modified by a 'top-half' handler (scratch[2])
47 * - ARG3: payload modified by a 'top-half' handler (scratch[3])
48 * - ARG4: payload modified by a 'top-half' handler (scratch[4])
49 * - ARG5: payload modified by a 'top-half' handler (scratch[5])
[43752b6]50 * - in_phone_hash: interrupt counter (may be needed to assure correct order
[228e490]51 * in multithreaded drivers)
[cecb0789]52 *
[8820544]53 * Note on synchronization for ipc_irq_subscribe(), ipc_irq_unsubscribe(),
[cecb0789]54 * ipc_irq_cleanup() and IRQ handlers:
55 *
56 * By always taking all of the uspace IRQ hash table lock, IRQ structure lock
57 * and answerbox lock, we can rule out race conditions between the
58 * registration functions and also the cleanup function. Thus the observer can
59 * either see the IRQ structure present in both the hash table and the
60 * answerbox list or absent in both. Views in which the IRQ structure would be
61 * linked in the hash table but not in the answerbox list, or vice versa, are
62 * not possible.
63 *
64 * By always taking the hash table lock and the IRQ structure lock, we can
65 * rule out a scenario in which we would free up an IRQ structure, which is
66 * still referenced by, for example, an IRQ handler. The locking scheme forces
67 * us to lock the IRQ structure only after any progressing IRQs on that
68 * structure are finished. Because we hold the hash table lock, we prevent new
69 * IRQs from taking new references to the IRQ structure.
[da1bafb]70 *
[bdc5c516]71 */
72
[162f919]73#include <arch.h>
[63e27ef]74#include <assert.h>
[162f919]75#include <mm/slab.h>
[a996ae31]76#include <mm/page.h>
77#include <mm/km.h>
[162f919]78#include <errno.h>
[2b017ba]79#include <ddi/irq.h>
[162f919]80#include <ipc/ipc.h>
81#include <ipc/irq.h>
[e3c762cd]82#include <syscall/copy.h>
[d0c5901]83#include <console/console.h>
[253f35a1]84#include <print.h>
[a996ae31]85#include <macros.h>
[3f74275]86#include <cap/cap.h>
[a996ae31]87
88static void ranges_unmap(irq_pio_range_t *ranges, size_t rangecount)
89{
[56c167c]90 for (size_t i = 0; i < rangecount; i++) {
[472d813]91#ifdef IO_SPACE_BOUNDARY
[a996ae31]92 if ((void *) ranges[i].base >= IO_SPACE_BOUNDARY)
[472d813]93#endif
[a996ae31]94 km_unmap(ranges[i].base, ranges[i].size);
95 }
96}
97
98static int ranges_map_and_apply(irq_pio_range_t *ranges, size_t rangecount,
99 irq_cmd_t *cmds, size_t cmdcount)
100{
101 /* Copy the physical base addresses aside. */
[56c167c]102 uintptr_t *pbase = malloc(rangecount * sizeof(uintptr_t), 0);
103 for (size_t i = 0; i < rangecount; i++)
[a996ae31]104 pbase[i] = ranges[i].base;
[56c167c]105
[a996ae31]106 /* Map the PIO ranges into the kernel virtual address space. */
[56c167c]107 for (size_t i = 0; i < rangecount; i++) {
[472d813]108#ifdef IO_SPACE_BOUNDARY
[a996ae31]109 if ((void *) ranges[i].base < IO_SPACE_BOUNDARY)
110 continue;
[472d813]111#endif
[a996ae31]112 ranges[i].base = km_map(pbase[i], ranges[i].size,
113 PAGE_READ | PAGE_WRITE | PAGE_KERNEL | PAGE_NOT_CACHEABLE);
114 if (!ranges[i].base) {
115 ranges_unmap(ranges, i);
116 free(pbase);
117 return ENOMEM;
118 }
119 }
[56c167c]120
[a996ae31]121 /* Rewrite the pseudocode addresses from physical to kernel virtual. */
[56c167c]122 for (size_t i = 0; i < cmdcount; i++) {
[a996ae31]123 uintptr_t addr;
[f2bbe8c]124 size_t size;
[56c167c]125
[a996ae31]126 /* Process only commands that use an address. */
127 switch (cmds[i].cmd) {
128 case CMD_PIO_READ_8:
[56c167c]129 case CMD_PIO_WRITE_8:
130 case CMD_PIO_WRITE_A_8:
[f2bbe8c]131 size = 1;
132 break;
[56c167c]133 case CMD_PIO_READ_16:
134 case CMD_PIO_WRITE_16:
135 case CMD_PIO_WRITE_A_16:
[f2bbe8c]136 size = 2;
137 break;
[56c167c]138 case CMD_PIO_READ_32:
139 case CMD_PIO_WRITE_32:
140 case CMD_PIO_WRITE_A_32:
[f2bbe8c]141 size = 4;
[a996ae31]142 break;
143 default:
144 /* Move onto the next command. */
145 continue;
146 }
[56c167c]147
[a996ae31]148 addr = (uintptr_t) cmds[i].addr;
149
[56c167c]150 size_t j;
[a996ae31]151 for (j = 0; j < rangecount; j++) {
152 /* Find the matching range. */
[f2bbe8c]153 if (!iswithin(pbase[j], ranges[j].size, addr, size))
[a996ae31]154 continue;
[56c167c]155
[a996ae31]156 /* Switch the command to a kernel virtual address. */
157 addr -= pbase[j];
158 addr += ranges[j].base;
[56c167c]159
[a996ae31]160 cmds[i].addr = (void *) addr;
161 break;
[bd8c6537]162 }
[56c167c]163
[bd8c6537]164 if (j == rangecount) {
165 /*
166 * The address used in this command is outside of all
167 * defined ranges.
168 */
169 ranges_unmap(ranges, rangecount);
170 free(pbase);
171 return EINVAL;
172 }
[a996ae31]173 }
[56c167c]174
[a996ae31]175 free(pbase);
176 return EOK;
177}
[162f919]178
[8486c07]179/** Statically check the top-half pseudocode
180 *
181 * Check the top-half pseudocode for invalid or unsafe
182 * constructs.
183 *
184 */
185static int code_check(irq_cmd_t *cmds, size_t cmdcount)
186{
187 for (size_t i = 0; i < cmdcount; i++) {
188 /*
189 * Check for accepted ranges.
190 */
191 if (cmds[i].cmd >= CMD_LAST)
192 return EINVAL;
193
194 if (cmds[i].srcarg >= IPC_CALL_LEN)
195 return EINVAL;
196
197 if (cmds[i].dstarg >= IPC_CALL_LEN)
198 return EINVAL;
199
200 switch (cmds[i].cmd) {
201 case CMD_PREDICATE:
202 /*
203 * Check for control flow overflow.
204 * Note that jumping just beyond the last
205 * command is a correct behaviour.
206 */
207 if (i + cmds[i].value > cmdcount)
208 return EINVAL;
209
210 break;
211 default:
212 break;
213 }
214 }
215
216 return EOK;
217}
218
[cecb0789]219/** Free the top-half pseudocode.
[8b243f2]220 *
[da1bafb]221 * @param code Pointer to the top-half pseudocode.
222 *
[8b243f2]223 */
[162f919]224static void code_free(irq_code_t *code)
225{
226 if (code) {
[a996ae31]227 ranges_unmap(code->ranges, code->rangecount);
228 free(code->ranges);
[162f919]229 free(code->cmds);
230 free(code);
231 }
232}
233
[cecb0789]234/** Copy the top-half pseudocode from userspace into the kernel.
[8b243f2]235 *
[da1bafb]236 * @param ucode Userspace address of the top-half pseudocode.
237 *
238 * @return Kernel address of the copied pseudocode.
[8b243f2]239 *
240 */
241static irq_code_t *code_from_uspace(irq_code_t *ucode)
[162f919]242{
[a996ae31]243 irq_pio_range_t *ranges = NULL;
244 irq_cmd_t *cmds = NULL;
[56c167c]245
[da1bafb]246 irq_code_t *code = malloc(sizeof(*code), 0);
247 int rc = copy_from_uspace(code, ucode, sizeof(*code));
[a996ae31]248 if (rc != EOK)
249 goto error;
[162f919]250
[a996ae31]251 if ((code->rangecount > IRQ_MAX_RANGE_COUNT) ||
252 (code->cmdcount > IRQ_MAX_PROG_SIZE))
253 goto error;
[da1bafb]254
[a996ae31]255 ranges = malloc(sizeof(code->ranges[0]) * code->rangecount, 0);
256 rc = copy_from_uspace(ranges, code->ranges,
257 sizeof(code->ranges[0]) * code->rangecount);
258 if (rc != EOK)
259 goto error;
[56c167c]260
[a996ae31]261 cmds = malloc(sizeof(code->cmds[0]) * code->cmdcount, 0);
262 rc = copy_from_uspace(cmds, code->cmds,
[8b243f2]263 sizeof(code->cmds[0]) * code->cmdcount);
[a996ae31]264 if (rc != EOK)
265 goto error;
[8486c07]266
267 rc = code_check(cmds, code->cmdcount);
268 if (rc != EOK)
269 goto error;
270
[a996ae31]271 rc = ranges_map_and_apply(ranges, code->rangecount, cmds,
272 code->cmdcount);
273 if (rc != EOK)
274 goto error;
[56c167c]275
[a996ae31]276 code->ranges = ranges;
277 code->cmds = cmds;
[56c167c]278
[162f919]279 return code;
[56c167c]280
[a996ae31]281error:
282 if (cmds)
283 free(cmds);
[56c167c]284
[a996ae31]285 if (ranges)
286 free(ranges);
[56c167c]287
[a996ae31]288 free(code);
289 return NULL;
[162f919]290}
291
[8820544]292/** Subscribe an answerbox as a receiving end for IRQ notifications.
[2b017ba]293 *
[56c167c]294 * @param box Receiving answerbox.
295 * @param inr IRQ number.
296 * @param imethod Interface and method to be associated with the
297 * notification.
298 * @param ucode Uspace pointer to top-half pseudocode.
299 *
[3f74275]300 * @return IRQ capability handle.
[e9d15d9]301 * @return Negative error code.
[2b017ba]302 *
303 */
[24abb85d]304int ipc_irq_subscribe(answerbox_t *box, inr_t inr, sysarg_t imethod,
305 irq_code_t *ucode)
[162f919]306{
[96b02eb9]307 sysarg_t key[] = {
[24abb85d]308 [IRQ_HT_KEY_INR] = (sysarg_t) inr,
309 [IRQ_HT_KEY_MODE] = (sysarg_t) IRQ_HT_MODE_NO_CLAIM
[cecb0789]310 };
[56c167c]311
[78ffb70]312 if ((inr < 0) || (inr > last_inr))
313 return ELIMIT;
[c822026]314
[da1bafb]315 irq_code_t *code;
[162f919]316 if (ucode) {
317 code = code_from_uspace(ucode);
318 if (!code)
319 return EBADMEM;
[da1bafb]320 } else
[162f919]321 code = NULL;
[c822026]322
[cecb0789]323 /*
[e9d15d9]324 * Allocate and populate the IRQ kernel object.
[cecb0789]325 */
[3f74275]326 int handle = cap_alloc(TASK);
327 if (handle < 0)
328 return handle;
329 cap_t *cap = cap_get_current(handle, CAP_TYPE_ALLOCATED);
330 assert(cap);
331 cap->type = CAP_TYPE_IRQ;
[e9d15d9]332
[3f74275]333 irq_t *irq = &cap->irq;
[cecb0789]334 irq_initialize(irq);
335 irq->inr = inr;
336 irq->claim = ipc_irq_top_half_claim;
[691eb52]337 irq->handler = ipc_irq_top_half_handler;
[4874c2d]338 irq->notif_cfg.notify = true;
[2b017ba]339 irq->notif_cfg.answerbox = box;
[228e490]340 irq->notif_cfg.imethod = imethod;
[2b017ba]341 irq->notif_cfg.code = code;
342 irq->notif_cfg.counter = 0;
[c822026]343
[cecb0789]344 /*
345 * Enlist the IRQ structure in the uspace IRQ hash table and the
346 * answerbox's list.
347 */
[da1bafb]348 irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
349 irq_spinlock_lock(&irq->lock, false);
350 irq_spinlock_lock(&box->irq_lock, false);
351
[cecb0789]352 hash_table_insert(&irq_uspace_hash_table, key, &irq->link);
[55b77d9]353 list_append(&irq->notif_cfg.link, &box->irq_list);
[c822026]354
[da1bafb]355 irq_spinlock_unlock(&box->irq_lock, false);
356 irq_spinlock_unlock(&irq->lock, false);
357 irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
358
[3f74275]359 return handle;
[cecb0789]360}
361
[8820544]362/** Unsubscribe task from IRQ notification.
[cecb0789]363 *
[3f74275]364 * @param box Answerbox associated with the notification.
365 * @param handle IRQ capability handle.
[56c167c]366 *
367 * @return EOK on success or a negative error code.
368 *
[cecb0789]369 */
[3f74275]370int ipc_irq_unsubscribe(answerbox_t *box, int handle)
[cecb0789]371{
[3f74275]372 cap_t *cap = cap_get_current(handle, CAP_TYPE_IRQ);
373 if (!cap)
[cecb0789]374 return ENOENT;
[3f74275]375 irq_t *irq = &cap->irq;
[e9d15d9]376
377 irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
378 irq_spinlock_lock(&irq->lock, false);
[da1bafb]379 irq_spinlock_lock(&box->irq_lock, false);
[cecb0789]380
[63e27ef]381 assert(irq->notif_cfg.answerbox == box);
[cecb0789]382
[da1bafb]383 /* Remove the IRQ from the answerbox's list. */
[cecb0789]384 list_remove(&irq->notif_cfg.link);
[da1bafb]385
[cecb0789]386 /* Remove the IRQ from the uspace IRQ hash table. */
[e9d15d9]387 hash_table_remove_item(&irq_uspace_hash_table, &irq->link);
[cecb0789]388
[da1bafb]389 irq_spinlock_unlock(&box->irq_lock, false);
[e9d15d9]390 /* irq->lock unlocked by the hash table remove_callback */
[da1bafb]391 irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
[cecb0789]392
[3cc070d]393 /* Free up the pseudo code and associated structures. */
394 code_free(irq->notif_cfg.code);
395
[3f74275]396 /* Free up the IRQ capability and the underlying kernel object. */
397 cap_free(TASK, handle);
[cecb0789]398
399 return EOK;
400}
401
402/** Disconnect all IRQ notifications from an answerbox.
403 *
[e9d15d9]404 * This function is effective because the answerbox contains list of all irq_t
405 * structures that are subscribed to send notifications to it.
[cecb0789]406 *
[da1bafb]407 * @param box Answerbox for which we want to carry out the cleanup.
408 *
[cecb0789]409 */
410void ipc_irq_cleanup(answerbox_t *box)
411{
412loop:
[da1bafb]413 irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
414 irq_spinlock_lock(&box->irq_lock, false);
[cecb0789]415
[55b77d9]416 while (!list_empty(&box->irq_list)) {
[cecb0789]417 DEADLOCK_PROBE_INIT(p_irqlock);
418
[55b77d9]419 irq_t *irq = list_get_instance(list_first(&box->irq_list), irq_t,
[da1bafb]420 notif_cfg.link);
421
422 if (!irq_spinlock_trylock(&irq->lock)) {
[cecb0789]423 /*
424 * Avoid deadlock by trying again.
425 */
[da1bafb]426 irq_spinlock_unlock(&box->irq_lock, false);
427 irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
[cecb0789]428 DEADLOCK_PROBE(p_irqlock, DEADLOCK_THRESHOLD);
429 goto loop;
430 }
[da1bafb]431
[63e27ef]432 assert(irq->notif_cfg.answerbox == box);
[cecb0789]433
434 /* Unlist from the answerbox. */
435 list_remove(&irq->notif_cfg.link);
436
[37be841]437 /* Remove from the hash table. */
[e9d15d9]438 hash_table_remove_item(&irq_uspace_hash_table, &irq->link);
[56c167c]439
[3cc070d]440 /*
[8a45bf09]441 * Release both locks so that we can free the IRQ code.
[3cc070d]442 */
443 irq_spinlock_unlock(&box->irq_lock, false);
444 irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
[56c167c]445
[3cc070d]446 code_free(irq->notif_cfg.code);
[e9d15d9]447
448 // XXX: what to do about the irq capability? The task is in
449 // clean-up anyway.
[3cc070d]450
451 /* Reacquire both locks before taking another round. */
452 irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
453 irq_spinlock_lock(&box->irq_lock, false);
[cecb0789]454 }
455
[da1bafb]456 irq_spinlock_unlock(&box->irq_lock, false);
457 irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
[162f919]458}
459
[8b243f2]460/** Add a call to the proper answerbox queue.
[2b017ba]461 *
[da1bafb]462 * Assume irq->lock is locked and interrupts disabled.
463 *
464 * @param irq IRQ structure referencing the target answerbox.
465 * @param call IRQ notification call.
[874621f]466 *
[2b017ba]467 */
468static void send_call(irq_t *irq, call_t *call)
[874621f]469{
[da1bafb]470 irq_spinlock_lock(&irq->notif_cfg.answerbox->irq_lock, false);
[cfaa35a]471 list_append(&call->ab_link, &irq->notif_cfg.answerbox->irq_notifs);
[da1bafb]472 irq_spinlock_unlock(&irq->notif_cfg.answerbox->irq_lock, false);
473
[2b017ba]474 waitq_wakeup(&irq->notif_cfg.answerbox->wq, WAKEUP_FIRST);
[874621f]475}
476
[cecb0789]477/** Apply the top-half pseudo code to find out whether to accept the IRQ or not.
[874621f]478 *
[da1bafb]479 * @param irq IRQ structure.
480 *
481 * @return IRQ_ACCEPT if the interrupt is accepted by the
482 * pseudocode, IRQ_DECLINE otherwise.
[cecb0789]483 *
[874621f]484 */
[cecb0789]485irq_ownership_t ipc_irq_top_half_claim(irq_t *irq)
[874621f]486{
[cecb0789]487 irq_code_t *code = irq->notif_cfg.code;
[da1bafb]488 uint32_t *scratch = irq->notif_cfg.scratch;
[cecb0789]489
490 if (!irq->notif_cfg.notify)
491 return IRQ_DECLINE;
492
493 if (!code)
494 return IRQ_DECLINE;
495
[01e39cbe]496 for (size_t i = 0; i < code->cmdcount; i++) {
[da1bafb]497 uintptr_t srcarg = code->cmds[i].srcarg;
498 uintptr_t dstarg = code->cmds[i].dstarg;
[874621f]499
[cecb0789]500 switch (code->cmds[i].cmd) {
501 case CMD_PIO_READ_8:
[8486c07]502 scratch[dstarg] =
503 pio_read_8((ioport8_t *) code->cmds[i].addr);
[cecb0789]504 break;
505 case CMD_PIO_READ_16:
[8486c07]506 scratch[dstarg] =
507 pio_read_16((ioport16_t *) code->cmds[i].addr);
[cecb0789]508 break;
509 case CMD_PIO_READ_32:
[8486c07]510 scratch[dstarg] =
511 pio_read_32((ioport32_t *) code->cmds[i].addr);
[cecb0789]512 break;
513 case CMD_PIO_WRITE_8:
514 pio_write_8((ioport8_t *) code->cmds[i].addr,
515 (uint8_t) code->cmds[i].value);
516 break;
517 case CMD_PIO_WRITE_16:
518 pio_write_16((ioport16_t *) code->cmds[i].addr,
519 (uint16_t) code->cmds[i].value);
520 break;
521 case CMD_PIO_WRITE_32:
522 pio_write_32((ioport32_t *) code->cmds[i].addr,
523 (uint32_t) code->cmds[i].value);
524 break;
[9cdac5a]525 case CMD_PIO_WRITE_A_8:
[8486c07]526 pio_write_8((ioport8_t *) code->cmds[i].addr,
527 (uint8_t) scratch[srcarg]);
[9cdac5a]528 break;
529 case CMD_PIO_WRITE_A_16:
[8486c07]530 pio_write_16((ioport16_t *) code->cmds[i].addr,
531 (uint16_t) scratch[srcarg]);
[9cdac5a]532 break;
533 case CMD_PIO_WRITE_A_32:
[8486c07]534 pio_write_32((ioport32_t *) code->cmds[i].addr,
535 (uint32_t) scratch[srcarg]);
536 break;
537 case CMD_LOAD:
538 scratch[dstarg] = code->cmds[i].value;
[9cdac5a]539 break;
[8486c07]540 case CMD_AND:
541 scratch[dstarg] = scratch[srcarg] &
542 code->cmds[i].value;
[cecb0789]543 break;
544 case CMD_PREDICATE:
[8486c07]545 if (scratch[srcarg] == 0)
[cecb0789]546 i += code->cmds[i].value;
[8486c07]547
[cecb0789]548 break;
549 case CMD_ACCEPT:
550 return IRQ_ACCEPT;
551 case CMD_DECLINE:
552 default:
553 return IRQ_DECLINE;
554 }
[874621f]555 }
[01e39cbe]556
[cecb0789]557 return IRQ_DECLINE;
[874621f]558}
559
[cecb0789]560/* IRQ top-half handler.
[162f919]561 *
[2b017ba]562 * We expect interrupts to be disabled and the irq->lock already held.
[8b243f2]563 *
[da1bafb]564 * @param irq IRQ structure.
565 *
[162f919]566 */
[cecb0789]567void ipc_irq_top_half_handler(irq_t *irq)
[162f919]568{
[63e27ef]569 assert(irq);
[56c167c]570
[63e27ef]571 assert(interrupts_disabled());
572 assert(irq_spinlock_locked(&irq->lock));
[da1bafb]573
[2b017ba]574 if (irq->notif_cfg.answerbox) {
[da1bafb]575 call_t *call = ipc_call_alloc(FRAME_ATOMIC);
[cecb0789]576 if (!call)
[d8f7362]577 return;
[cecb0789]578
[162f919]579 call->flags |= IPC_CALL_NOTIF;
[43752b6]580 /* Put a counter to the message */
[0c1a5d8a]581 call->priv = ++irq->notif_cfg.counter;
[da1bafb]582
[43752b6]583 /* Set up args */
[228e490]584 IPC_SET_IMETHOD(call->data, irq->notif_cfg.imethod);
[cecb0789]585 IPC_SET_ARG1(call->data, irq->notif_cfg.scratch[1]);
586 IPC_SET_ARG2(call->data, irq->notif_cfg.scratch[2]);
587 IPC_SET_ARG3(call->data, irq->notif_cfg.scratch[3]);
588 IPC_SET_ARG4(call->data, irq->notif_cfg.scratch[4]);
589 IPC_SET_ARG5(call->data, irq->notif_cfg.scratch[5]);
[da1bafb]590
[2b017ba]591 send_call(irq, call);
[162f919]592 }
593}
594
[cecb0789]595/** Send notification message.
[874621f]596 *
[da1bafb]597 * @param irq IRQ structure.
598 * @param a1 Driver-specific payload argument.
599 * @param a2 Driver-specific payload argument.
600 * @param a3 Driver-specific payload argument.
601 * @param a4 Driver-specific payload argument.
602 * @param a5 Driver-specific payload argument.
603 *
[162f919]604 */
[96b02eb9]605void ipc_irq_send_msg(irq_t *irq, sysarg_t a1, sysarg_t a2, sysarg_t a3,
606 sysarg_t a4, sysarg_t a5)
[162f919]607{
[da1bafb]608 irq_spinlock_lock(&irq->lock, true);
609
[cecb0789]610 if (irq->notif_cfg.answerbox) {
[da1bafb]611 call_t *call = ipc_call_alloc(FRAME_ATOMIC);
[cecb0789]612 if (!call) {
[da1bafb]613 irq_spinlock_unlock(&irq->lock, true);
[cecb0789]614 return;
[b14e35f2]615 }
[da1bafb]616
[cecb0789]617 call->flags |= IPC_CALL_NOTIF;
618 /* Put a counter to the message */
619 call->priv = ++irq->notif_cfg.counter;
[da1bafb]620
[228e490]621 IPC_SET_IMETHOD(call->data, irq->notif_cfg.imethod);
[cecb0789]622 IPC_SET_ARG1(call->data, a1);
623 IPC_SET_ARG2(call->data, a2);
624 IPC_SET_ARG3(call->data, a3);
625 IPC_SET_ARG4(call->data, a4);
626 IPC_SET_ARG5(call->data, a5);
627
628 send_call(irq, call);
[b14e35f2]629 }
[da1bafb]630
631 irq_spinlock_unlock(&irq->lock, true);
[162f919]632}
[b45c443]633
[cc73a8a1]634/** @}
[b45c443]635 */
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