[162f919] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2006 Ondrej Palkovsky
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| 3 | * Copyright (c) 2006 Jakub Jermar
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[162f919] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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[cc73a8a1] | 30 | /** @addtogroup genericipc
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[b45c443] | 31 | * @{
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| 32 | */
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[da1bafb] | 33 |
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[cc73a8a1] | 34 | /**
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| 35 | * @file
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| 36 | * @brief IRQ notification framework.
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[bdc5c516] | 37 | *
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[8820544] | 38 | * This framework allows applications to subscribe to receive a notification
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[bdc5c516] | 39 | * when interrupt is detected. The application may provide a simple 'top-half'
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| 40 | * handler as part of its registration, which can perform simple operations
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[56c167c] | 41 | * (read/write port/memory, add information to notification IPC message).
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[bdc5c516] | 42 | *
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| 43 | * The structure of a notification message is as follows:
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[8820544] | 44 | * - IMETHOD: interface and method as set by the SYS_IPC_IRQ_SUBSCRIBE syscall
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[56c167c] | 45 | * - ARG1: payload modified by a 'top-half' handler (scratch[1])
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| 46 | * - ARG2: payload modified by a 'top-half' handler (scratch[2])
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| 47 | * - ARG3: payload modified by a 'top-half' handler (scratch[3])
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| 48 | * - ARG4: payload modified by a 'top-half' handler (scratch[4])
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| 49 | * - ARG5: payload modified by a 'top-half' handler (scratch[5])
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[43752b6] | 50 | * - in_phone_hash: interrupt counter (may be needed to assure correct order
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[228e490] | 51 | * in multithreaded drivers)
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[cecb0789] | 52 | *
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[8820544] | 53 | * Note on synchronization for ipc_irq_subscribe(), ipc_irq_unsubscribe(),
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[cecb0789] | 54 | * ipc_irq_cleanup() and IRQ handlers:
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| 55 | *
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| 56 | * By always taking all of the uspace IRQ hash table lock, IRQ structure lock
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| 57 | * and answerbox lock, we can rule out race conditions between the
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| 58 | * registration functions and also the cleanup function. Thus the observer can
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| 59 | * either see the IRQ structure present in both the hash table and the
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| 60 | * answerbox list or absent in both. Views in which the IRQ structure would be
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| 61 | * linked in the hash table but not in the answerbox list, or vice versa, are
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| 62 | * not possible.
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| 63 | *
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| 64 | * By always taking the hash table lock and the IRQ structure lock, we can
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| 65 | * rule out a scenario in which we would free up an IRQ structure, which is
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| 66 | * still referenced by, for example, an IRQ handler. The locking scheme forces
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| 67 | * us to lock the IRQ structure only after any progressing IRQs on that
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| 68 | * structure are finished. Because we hold the hash table lock, we prevent new
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| 69 | * IRQs from taking new references to the IRQ structure.
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[da1bafb] | 70 | *
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[bdc5c516] | 71 | */
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| 72 |
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[162f919] | 73 | #include <arch.h>
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[63e27ef] | 74 | #include <assert.h>
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[162f919] | 75 | #include <mm/slab.h>
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[a996ae31] | 76 | #include <mm/page.h>
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| 77 | #include <mm/km.h>
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[162f919] | 78 | #include <errno.h>
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[2b017ba] | 79 | #include <ddi/irq.h>
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[162f919] | 80 | #include <ipc/ipc.h>
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| 81 | #include <ipc/irq.h>
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[e3c762cd] | 82 | #include <syscall/copy.h>
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[d0c5901] | 83 | #include <console/console.h>
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[253f35a1] | 84 | #include <print.h>
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[a996ae31] | 85 | #include <macros.h>
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[3f74275] | 86 | #include <cap/cap.h>
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[a996ae31] | 87 |
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| 88 | static void ranges_unmap(irq_pio_range_t *ranges, size_t rangecount)
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| 89 | {
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[56c167c] | 90 | for (size_t i = 0; i < rangecount; i++) {
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[472d813] | 91 | #ifdef IO_SPACE_BOUNDARY
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[a996ae31] | 92 | if ((void *) ranges[i].base >= IO_SPACE_BOUNDARY)
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[472d813] | 93 | #endif
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[a996ae31] | 94 | km_unmap(ranges[i].base, ranges[i].size);
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| 95 | }
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| 96 | }
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| 97 |
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| 98 | static int ranges_map_and_apply(irq_pio_range_t *ranges, size_t rangecount,
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| 99 | irq_cmd_t *cmds, size_t cmdcount)
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| 100 | {
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| 101 | /* Copy the physical base addresses aside. */
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[56c167c] | 102 | uintptr_t *pbase = malloc(rangecount * sizeof(uintptr_t), 0);
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| 103 | for (size_t i = 0; i < rangecount; i++)
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[a996ae31] | 104 | pbase[i] = ranges[i].base;
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[56c167c] | 105 |
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[a996ae31] | 106 | /* Map the PIO ranges into the kernel virtual address space. */
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[56c167c] | 107 | for (size_t i = 0; i < rangecount; i++) {
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[472d813] | 108 | #ifdef IO_SPACE_BOUNDARY
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[a996ae31] | 109 | if ((void *) ranges[i].base < IO_SPACE_BOUNDARY)
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| 110 | continue;
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[472d813] | 111 | #endif
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[a996ae31] | 112 | ranges[i].base = km_map(pbase[i], ranges[i].size,
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| 113 | PAGE_READ | PAGE_WRITE | PAGE_KERNEL | PAGE_NOT_CACHEABLE);
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| 114 | if (!ranges[i].base) {
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| 115 | ranges_unmap(ranges, i);
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| 116 | free(pbase);
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| 117 | return ENOMEM;
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| 118 | }
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| 119 | }
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[56c167c] | 120 |
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[a996ae31] | 121 | /* Rewrite the pseudocode addresses from physical to kernel virtual. */
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[56c167c] | 122 | for (size_t i = 0; i < cmdcount; i++) {
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[a996ae31] | 123 | uintptr_t addr;
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[f2bbe8c] | 124 | size_t size;
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[56c167c] | 125 |
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[a996ae31] | 126 | /* Process only commands that use an address. */
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| 127 | switch (cmds[i].cmd) {
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| 128 | case CMD_PIO_READ_8:
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[56c167c] | 129 | case CMD_PIO_WRITE_8:
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| 130 | case CMD_PIO_WRITE_A_8:
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[f2bbe8c] | 131 | size = 1;
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| 132 | break;
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[56c167c] | 133 | case CMD_PIO_READ_16:
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| 134 | case CMD_PIO_WRITE_16:
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| 135 | case CMD_PIO_WRITE_A_16:
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[f2bbe8c] | 136 | size = 2;
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| 137 | break;
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[56c167c] | 138 | case CMD_PIO_READ_32:
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| 139 | case CMD_PIO_WRITE_32:
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| 140 | case CMD_PIO_WRITE_A_32:
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[f2bbe8c] | 141 | size = 4;
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[a996ae31] | 142 | break;
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| 143 | default:
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| 144 | /* Move onto the next command. */
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| 145 | continue;
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| 146 | }
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[56c167c] | 147 |
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[a996ae31] | 148 | addr = (uintptr_t) cmds[i].addr;
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| 149 |
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[56c167c] | 150 | size_t j;
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[a996ae31] | 151 | for (j = 0; j < rangecount; j++) {
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| 152 | /* Find the matching range. */
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[f2bbe8c] | 153 | if (!iswithin(pbase[j], ranges[j].size, addr, size))
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[a996ae31] | 154 | continue;
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[56c167c] | 155 |
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[a996ae31] | 156 | /* Switch the command to a kernel virtual address. */
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| 157 | addr -= pbase[j];
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| 158 | addr += ranges[j].base;
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[56c167c] | 159 |
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[a996ae31] | 160 | cmds[i].addr = (void *) addr;
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| 161 | break;
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[bd8c6537] | 162 | }
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[56c167c] | 163 |
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[bd8c6537] | 164 | if (j == rangecount) {
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| 165 | /*
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| 166 | * The address used in this command is outside of all
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| 167 | * defined ranges.
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| 168 | */
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| 169 | ranges_unmap(ranges, rangecount);
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| 170 | free(pbase);
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| 171 | return EINVAL;
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| 172 | }
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[a996ae31] | 173 | }
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[56c167c] | 174 |
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[a996ae31] | 175 | free(pbase);
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| 176 | return EOK;
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| 177 | }
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[162f919] | 178 |
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[8486c07] | 179 | /** Statically check the top-half pseudocode
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| 180 | *
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| 181 | * Check the top-half pseudocode for invalid or unsafe
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| 182 | * constructs.
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| 183 | *
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| 184 | */
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| 185 | static int code_check(irq_cmd_t *cmds, size_t cmdcount)
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| 186 | {
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| 187 | for (size_t i = 0; i < cmdcount; i++) {
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| 188 | /*
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| 189 | * Check for accepted ranges.
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| 190 | */
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| 191 | if (cmds[i].cmd >= CMD_LAST)
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| 192 | return EINVAL;
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| 193 |
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| 194 | if (cmds[i].srcarg >= IPC_CALL_LEN)
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| 195 | return EINVAL;
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| 196 |
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| 197 | if (cmds[i].dstarg >= IPC_CALL_LEN)
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| 198 | return EINVAL;
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| 199 |
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| 200 | switch (cmds[i].cmd) {
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| 201 | case CMD_PREDICATE:
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| 202 | /*
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| 203 | * Check for control flow overflow.
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| 204 | * Note that jumping just beyond the last
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| 205 | * command is a correct behaviour.
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| 206 | */
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| 207 | if (i + cmds[i].value > cmdcount)
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| 208 | return EINVAL;
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| 209 |
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| 210 | break;
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| 211 | default:
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| 212 | break;
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| 213 | }
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| 214 | }
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| 215 |
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| 216 | return EOK;
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| 217 | }
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| 218 |
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[cecb0789] | 219 | /** Free the top-half pseudocode.
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[8b243f2] | 220 | *
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[da1bafb] | 221 | * @param code Pointer to the top-half pseudocode.
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| 222 | *
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[8b243f2] | 223 | */
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[162f919] | 224 | static void code_free(irq_code_t *code)
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| 225 | {
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| 226 | if (code) {
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[a996ae31] | 227 | ranges_unmap(code->ranges, code->rangecount);
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| 228 | free(code->ranges);
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[162f919] | 229 | free(code->cmds);
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| 230 | free(code);
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| 231 | }
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| 232 | }
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| 233 |
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[cecb0789] | 234 | /** Copy the top-half pseudocode from userspace into the kernel.
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[8b243f2] | 235 | *
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[da1bafb] | 236 | * @param ucode Userspace address of the top-half pseudocode.
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| 237 | *
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| 238 | * @return Kernel address of the copied pseudocode.
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[8b243f2] | 239 | *
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| 240 | */
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| 241 | static irq_code_t *code_from_uspace(irq_code_t *ucode)
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[162f919] | 242 | {
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[a996ae31] | 243 | irq_pio_range_t *ranges = NULL;
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| 244 | irq_cmd_t *cmds = NULL;
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[56c167c] | 245 |
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[da1bafb] | 246 | irq_code_t *code = malloc(sizeof(*code), 0);
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| 247 | int rc = copy_from_uspace(code, ucode, sizeof(*code));
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[a996ae31] | 248 | if (rc != EOK)
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| 249 | goto error;
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[162f919] | 250 |
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[a996ae31] | 251 | if ((code->rangecount > IRQ_MAX_RANGE_COUNT) ||
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| 252 | (code->cmdcount > IRQ_MAX_PROG_SIZE))
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| 253 | goto error;
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[da1bafb] | 254 |
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[a996ae31] | 255 | ranges = malloc(sizeof(code->ranges[0]) * code->rangecount, 0);
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| 256 | rc = copy_from_uspace(ranges, code->ranges,
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| 257 | sizeof(code->ranges[0]) * code->rangecount);
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| 258 | if (rc != EOK)
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| 259 | goto error;
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[56c167c] | 260 |
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[a996ae31] | 261 | cmds = malloc(sizeof(code->cmds[0]) * code->cmdcount, 0);
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| 262 | rc = copy_from_uspace(cmds, code->cmds,
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[8b243f2] | 263 | sizeof(code->cmds[0]) * code->cmdcount);
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[a996ae31] | 264 | if (rc != EOK)
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| 265 | goto error;
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[8486c07] | 266 |
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| 267 | rc = code_check(cmds, code->cmdcount);
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| 268 | if (rc != EOK)
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| 269 | goto error;
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| 270 |
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[a996ae31] | 271 | rc = ranges_map_and_apply(ranges, code->rangecount, cmds,
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| 272 | code->cmdcount);
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| 273 | if (rc != EOK)
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| 274 | goto error;
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[56c167c] | 275 |
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[a996ae31] | 276 | code->ranges = ranges;
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| 277 | code->cmds = cmds;
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[56c167c] | 278 |
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[162f919] | 279 | return code;
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[56c167c] | 280 |
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[a996ae31] | 281 | error:
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| 282 | if (cmds)
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| 283 | free(cmds);
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[56c167c] | 284 |
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[a996ae31] | 285 | if (ranges)
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| 286 | free(ranges);
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[56c167c] | 287 |
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[a996ae31] | 288 | free(code);
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| 289 | return NULL;
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[162f919] | 290 | }
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| 291 |
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[8820544] | 292 | /** Subscribe an answerbox as a receiving end for IRQ notifications.
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[2b017ba] | 293 | *
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[56c167c] | 294 | * @param box Receiving answerbox.
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| 295 | * @param inr IRQ number.
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| 296 | * @param imethod Interface and method to be associated with the
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| 297 | * notification.
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| 298 | * @param ucode Uspace pointer to top-half pseudocode.
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| 299 | *
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[3f74275] | 300 | * @return IRQ capability handle.
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[e9d15d9] | 301 | * @return Negative error code.
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[2b017ba] | 302 | *
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| 303 | */
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[24abb85d] | 304 | int ipc_irq_subscribe(answerbox_t *box, inr_t inr, sysarg_t imethod,
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| 305 | irq_code_t *ucode)
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[162f919] | 306 | {
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[96b02eb9] | 307 | sysarg_t key[] = {
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[24abb85d] | 308 | [IRQ_HT_KEY_INR] = (sysarg_t) inr,
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| 309 | [IRQ_HT_KEY_MODE] = (sysarg_t) IRQ_HT_MODE_NO_CLAIM
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[cecb0789] | 310 | };
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[56c167c] | 311 |
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[78ffb70] | 312 | if ((inr < 0) || (inr > last_inr))
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| 313 | return ELIMIT;
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[c822026] | 314 |
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[da1bafb] | 315 | irq_code_t *code;
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[162f919] | 316 | if (ucode) {
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| 317 | code = code_from_uspace(ucode);
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| 318 | if (!code)
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| 319 | return EBADMEM;
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[da1bafb] | 320 | } else
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[162f919] | 321 | code = NULL;
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[c822026] | 322 |
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[cecb0789] | 323 | /*
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[e9d15d9] | 324 | * Allocate and populate the IRQ kernel object.
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[cecb0789] | 325 | */
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[3f74275] | 326 | int handle = cap_alloc(TASK);
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| 327 | if (handle < 0)
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| 328 | return handle;
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| 329 | cap_t *cap = cap_get_current(handle, CAP_TYPE_ALLOCATED);
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| 330 | assert(cap);
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| 331 | cap->type = CAP_TYPE_IRQ;
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[e9d15d9] | 332 |
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[3f74275] | 333 | irq_t *irq = &cap->irq;
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[cecb0789] | 334 | irq_initialize(irq);
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| 335 | irq->inr = inr;
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| 336 | irq->claim = ipc_irq_top_half_claim;
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[691eb52] | 337 | irq->handler = ipc_irq_top_half_handler;
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[4874c2d] | 338 | irq->notif_cfg.notify = true;
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[2b017ba] | 339 | irq->notif_cfg.answerbox = box;
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[228e490] | 340 | irq->notif_cfg.imethod = imethod;
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[2b017ba] | 341 | irq->notif_cfg.code = code;
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| 342 | irq->notif_cfg.counter = 0;
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[c822026] | 343 |
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[cecb0789] | 344 | /*
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| 345 | * Enlist the IRQ structure in the uspace IRQ hash table and the
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| 346 | * answerbox's list.
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| 347 | */
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[da1bafb] | 348 | irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
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| 349 | irq_spinlock_lock(&irq->lock, false);
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| 350 | irq_spinlock_lock(&box->irq_lock, false);
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| 351 |
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[cecb0789] | 352 | hash_table_insert(&irq_uspace_hash_table, key, &irq->link);
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[55b77d9] | 353 | list_append(&irq->notif_cfg.link, &box->irq_list);
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[c822026] | 354 |
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[da1bafb] | 355 | irq_spinlock_unlock(&box->irq_lock, false);
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| 356 | irq_spinlock_unlock(&irq->lock, false);
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| 357 | irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
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| 358 |
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[3f74275] | 359 | return handle;
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[cecb0789] | 360 | }
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| 361 |
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[8820544] | 362 | /** Unsubscribe task from IRQ notification.
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[cecb0789] | 363 | *
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[3f74275] | 364 | * @param box Answerbox associated with the notification.
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| 365 | * @param handle IRQ capability handle.
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[56c167c] | 366 | *
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| 367 | * @return EOK on success or a negative error code.
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| 368 | *
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[cecb0789] | 369 | */
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[3f74275] | 370 | int ipc_irq_unsubscribe(answerbox_t *box, int handle)
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[cecb0789] | 371 | {
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[3f74275] | 372 | cap_t *cap = cap_get_current(handle, CAP_TYPE_IRQ);
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| 373 | if (!cap)
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[cecb0789] | 374 | return ENOENT;
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[3f74275] | 375 | irq_t *irq = &cap->irq;
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[e9d15d9] | 376 |
|
---|
| 377 | irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
|
---|
| 378 | irq_spinlock_lock(&irq->lock, false);
|
---|
[da1bafb] | 379 | irq_spinlock_lock(&box->irq_lock, false);
|
---|
[cecb0789] | 380 |
|
---|
[63e27ef] | 381 | assert(irq->notif_cfg.answerbox == box);
|
---|
[cecb0789] | 382 |
|
---|
[da1bafb] | 383 | /* Remove the IRQ from the answerbox's list. */
|
---|
[cecb0789] | 384 | list_remove(&irq->notif_cfg.link);
|
---|
[da1bafb] | 385 |
|
---|
[cecb0789] | 386 | /* Remove the IRQ from the uspace IRQ hash table. */
|
---|
[e9d15d9] | 387 | hash_table_remove_item(&irq_uspace_hash_table, &irq->link);
|
---|
[cecb0789] | 388 |
|
---|
[da1bafb] | 389 | irq_spinlock_unlock(&box->irq_lock, false);
|
---|
[e9d15d9] | 390 | /* irq->lock unlocked by the hash table remove_callback */
|
---|
[da1bafb] | 391 | irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
|
---|
[cecb0789] | 392 |
|
---|
[3cc070d] | 393 | /* Free up the pseudo code and associated structures. */
|
---|
| 394 | code_free(irq->notif_cfg.code);
|
---|
| 395 |
|
---|
[3f74275] | 396 | /* Free up the IRQ capability and the underlying kernel object. */
|
---|
| 397 | cap_free(TASK, handle);
|
---|
[cecb0789] | 398 |
|
---|
| 399 | return EOK;
|
---|
| 400 | }
|
---|
| 401 |
|
---|
| 402 | /** Disconnect all IRQ notifications from an answerbox.
|
---|
| 403 | *
|
---|
[e9d15d9] | 404 | * This function is effective because the answerbox contains list of all irq_t
|
---|
| 405 | * structures that are subscribed to send notifications to it.
|
---|
[cecb0789] | 406 | *
|
---|
[da1bafb] | 407 | * @param box Answerbox for which we want to carry out the cleanup.
|
---|
| 408 | *
|
---|
[cecb0789] | 409 | */
|
---|
| 410 | void ipc_irq_cleanup(answerbox_t *box)
|
---|
| 411 | {
|
---|
| 412 | loop:
|
---|
[da1bafb] | 413 | irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
|
---|
| 414 | irq_spinlock_lock(&box->irq_lock, false);
|
---|
[cecb0789] | 415 |
|
---|
[55b77d9] | 416 | while (!list_empty(&box->irq_list)) {
|
---|
[cecb0789] | 417 | DEADLOCK_PROBE_INIT(p_irqlock);
|
---|
| 418 |
|
---|
[55b77d9] | 419 | irq_t *irq = list_get_instance(list_first(&box->irq_list), irq_t,
|
---|
[da1bafb] | 420 | notif_cfg.link);
|
---|
| 421 |
|
---|
| 422 | if (!irq_spinlock_trylock(&irq->lock)) {
|
---|
[cecb0789] | 423 | /*
|
---|
| 424 | * Avoid deadlock by trying again.
|
---|
| 425 | */
|
---|
[da1bafb] | 426 | irq_spinlock_unlock(&box->irq_lock, false);
|
---|
| 427 | irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
|
---|
[cecb0789] | 428 | DEADLOCK_PROBE(p_irqlock, DEADLOCK_THRESHOLD);
|
---|
| 429 | goto loop;
|
---|
| 430 | }
|
---|
[da1bafb] | 431 |
|
---|
[63e27ef] | 432 | assert(irq->notif_cfg.answerbox == box);
|
---|
[cecb0789] | 433 |
|
---|
| 434 | /* Unlist from the answerbox. */
|
---|
| 435 | list_remove(&irq->notif_cfg.link);
|
---|
| 436 |
|
---|
[37be841] | 437 | /* Remove from the hash table. */
|
---|
[e9d15d9] | 438 | hash_table_remove_item(&irq_uspace_hash_table, &irq->link);
|
---|
[56c167c] | 439 |
|
---|
[3cc070d] | 440 | /*
|
---|
[8a45bf09] | 441 | * Release both locks so that we can free the IRQ code.
|
---|
[3cc070d] | 442 | */
|
---|
| 443 | irq_spinlock_unlock(&box->irq_lock, false);
|
---|
| 444 | irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
|
---|
[56c167c] | 445 |
|
---|
[3cc070d] | 446 | code_free(irq->notif_cfg.code);
|
---|
[e9d15d9] | 447 |
|
---|
| 448 | // XXX: what to do about the irq capability? The task is in
|
---|
| 449 | // clean-up anyway.
|
---|
[3cc070d] | 450 |
|
---|
| 451 | /* Reacquire both locks before taking another round. */
|
---|
| 452 | irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
|
---|
| 453 | irq_spinlock_lock(&box->irq_lock, false);
|
---|
[cecb0789] | 454 | }
|
---|
| 455 |
|
---|
[da1bafb] | 456 | irq_spinlock_unlock(&box->irq_lock, false);
|
---|
| 457 | irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
|
---|
[162f919] | 458 | }
|
---|
| 459 |
|
---|
[8b243f2] | 460 | /** Add a call to the proper answerbox queue.
|
---|
[2b017ba] | 461 | *
|
---|
[da1bafb] | 462 | * Assume irq->lock is locked and interrupts disabled.
|
---|
| 463 | *
|
---|
| 464 | * @param irq IRQ structure referencing the target answerbox.
|
---|
| 465 | * @param call IRQ notification call.
|
---|
[874621f] | 466 | *
|
---|
[2b017ba] | 467 | */
|
---|
| 468 | static void send_call(irq_t *irq, call_t *call)
|
---|
[874621f] | 469 | {
|
---|
[da1bafb] | 470 | irq_spinlock_lock(&irq->notif_cfg.answerbox->irq_lock, false);
|
---|
[cfaa35a] | 471 | list_append(&call->ab_link, &irq->notif_cfg.answerbox->irq_notifs);
|
---|
[da1bafb] | 472 | irq_spinlock_unlock(&irq->notif_cfg.answerbox->irq_lock, false);
|
---|
| 473 |
|
---|
[2b017ba] | 474 | waitq_wakeup(&irq->notif_cfg.answerbox->wq, WAKEUP_FIRST);
|
---|
[874621f] | 475 | }
|
---|
| 476 |
|
---|
[cecb0789] | 477 | /** Apply the top-half pseudo code to find out whether to accept the IRQ or not.
|
---|
[874621f] | 478 | *
|
---|
[da1bafb] | 479 | * @param irq IRQ structure.
|
---|
| 480 | *
|
---|
| 481 | * @return IRQ_ACCEPT if the interrupt is accepted by the
|
---|
| 482 | * pseudocode, IRQ_DECLINE otherwise.
|
---|
[cecb0789] | 483 | *
|
---|
[874621f] | 484 | */
|
---|
[cecb0789] | 485 | irq_ownership_t ipc_irq_top_half_claim(irq_t *irq)
|
---|
[874621f] | 486 | {
|
---|
[cecb0789] | 487 | irq_code_t *code = irq->notif_cfg.code;
|
---|
[da1bafb] | 488 | uint32_t *scratch = irq->notif_cfg.scratch;
|
---|
[cecb0789] | 489 |
|
---|
| 490 | if (!irq->notif_cfg.notify)
|
---|
| 491 | return IRQ_DECLINE;
|
---|
| 492 |
|
---|
| 493 | if (!code)
|
---|
| 494 | return IRQ_DECLINE;
|
---|
| 495 |
|
---|
[01e39cbe] | 496 | for (size_t i = 0; i < code->cmdcount; i++) {
|
---|
[da1bafb] | 497 | uintptr_t srcarg = code->cmds[i].srcarg;
|
---|
| 498 | uintptr_t dstarg = code->cmds[i].dstarg;
|
---|
[874621f] | 499 |
|
---|
[cecb0789] | 500 | switch (code->cmds[i].cmd) {
|
---|
| 501 | case CMD_PIO_READ_8:
|
---|
[8486c07] | 502 | scratch[dstarg] =
|
---|
| 503 | pio_read_8((ioport8_t *) code->cmds[i].addr);
|
---|
[cecb0789] | 504 | break;
|
---|
| 505 | case CMD_PIO_READ_16:
|
---|
[8486c07] | 506 | scratch[dstarg] =
|
---|
| 507 | pio_read_16((ioport16_t *) code->cmds[i].addr);
|
---|
[cecb0789] | 508 | break;
|
---|
| 509 | case CMD_PIO_READ_32:
|
---|
[8486c07] | 510 | scratch[dstarg] =
|
---|
| 511 | pio_read_32((ioport32_t *) code->cmds[i].addr);
|
---|
[cecb0789] | 512 | break;
|
---|
| 513 | case CMD_PIO_WRITE_8:
|
---|
| 514 | pio_write_8((ioport8_t *) code->cmds[i].addr,
|
---|
| 515 | (uint8_t) code->cmds[i].value);
|
---|
| 516 | break;
|
---|
| 517 | case CMD_PIO_WRITE_16:
|
---|
| 518 | pio_write_16((ioport16_t *) code->cmds[i].addr,
|
---|
| 519 | (uint16_t) code->cmds[i].value);
|
---|
| 520 | break;
|
---|
| 521 | case CMD_PIO_WRITE_32:
|
---|
| 522 | pio_write_32((ioport32_t *) code->cmds[i].addr,
|
---|
| 523 | (uint32_t) code->cmds[i].value);
|
---|
| 524 | break;
|
---|
[9cdac5a] | 525 | case CMD_PIO_WRITE_A_8:
|
---|
[8486c07] | 526 | pio_write_8((ioport8_t *) code->cmds[i].addr,
|
---|
| 527 | (uint8_t) scratch[srcarg]);
|
---|
[9cdac5a] | 528 | break;
|
---|
| 529 | case CMD_PIO_WRITE_A_16:
|
---|
[8486c07] | 530 | pio_write_16((ioport16_t *) code->cmds[i].addr,
|
---|
| 531 | (uint16_t) scratch[srcarg]);
|
---|
[9cdac5a] | 532 | break;
|
---|
| 533 | case CMD_PIO_WRITE_A_32:
|
---|
[8486c07] | 534 | pio_write_32((ioport32_t *) code->cmds[i].addr,
|
---|
| 535 | (uint32_t) scratch[srcarg]);
|
---|
| 536 | break;
|
---|
| 537 | case CMD_LOAD:
|
---|
| 538 | scratch[dstarg] = code->cmds[i].value;
|
---|
[9cdac5a] | 539 | break;
|
---|
[8486c07] | 540 | case CMD_AND:
|
---|
| 541 | scratch[dstarg] = scratch[srcarg] &
|
---|
| 542 | code->cmds[i].value;
|
---|
[cecb0789] | 543 | break;
|
---|
| 544 | case CMD_PREDICATE:
|
---|
[8486c07] | 545 | if (scratch[srcarg] == 0)
|
---|
[cecb0789] | 546 | i += code->cmds[i].value;
|
---|
[8486c07] | 547 |
|
---|
[cecb0789] | 548 | break;
|
---|
| 549 | case CMD_ACCEPT:
|
---|
| 550 | return IRQ_ACCEPT;
|
---|
| 551 | case CMD_DECLINE:
|
---|
| 552 | default:
|
---|
| 553 | return IRQ_DECLINE;
|
---|
| 554 | }
|
---|
[874621f] | 555 | }
|
---|
[01e39cbe] | 556 |
|
---|
[cecb0789] | 557 | return IRQ_DECLINE;
|
---|
[874621f] | 558 | }
|
---|
| 559 |
|
---|
[cecb0789] | 560 | /* IRQ top-half handler.
|
---|
[162f919] | 561 | *
|
---|
[2b017ba] | 562 | * We expect interrupts to be disabled and the irq->lock already held.
|
---|
[8b243f2] | 563 | *
|
---|
[da1bafb] | 564 | * @param irq IRQ structure.
|
---|
| 565 | *
|
---|
[162f919] | 566 | */
|
---|
[cecb0789] | 567 | void ipc_irq_top_half_handler(irq_t *irq)
|
---|
[162f919] | 568 | {
|
---|
[63e27ef] | 569 | assert(irq);
|
---|
[56c167c] | 570 |
|
---|
[63e27ef] | 571 | assert(interrupts_disabled());
|
---|
| 572 | assert(irq_spinlock_locked(&irq->lock));
|
---|
[da1bafb] | 573 |
|
---|
[2b017ba] | 574 | if (irq->notif_cfg.answerbox) {
|
---|
[da1bafb] | 575 | call_t *call = ipc_call_alloc(FRAME_ATOMIC);
|
---|
[cecb0789] | 576 | if (!call)
|
---|
[d8f7362] | 577 | return;
|
---|
[cecb0789] | 578 |
|
---|
[162f919] | 579 | call->flags |= IPC_CALL_NOTIF;
|
---|
[43752b6] | 580 | /* Put a counter to the message */
|
---|
[0c1a5d8a] | 581 | call->priv = ++irq->notif_cfg.counter;
|
---|
[da1bafb] | 582 |
|
---|
[43752b6] | 583 | /* Set up args */
|
---|
[228e490] | 584 | IPC_SET_IMETHOD(call->data, irq->notif_cfg.imethod);
|
---|
[cecb0789] | 585 | IPC_SET_ARG1(call->data, irq->notif_cfg.scratch[1]);
|
---|
| 586 | IPC_SET_ARG2(call->data, irq->notif_cfg.scratch[2]);
|
---|
| 587 | IPC_SET_ARG3(call->data, irq->notif_cfg.scratch[3]);
|
---|
| 588 | IPC_SET_ARG4(call->data, irq->notif_cfg.scratch[4]);
|
---|
| 589 | IPC_SET_ARG5(call->data, irq->notif_cfg.scratch[5]);
|
---|
[da1bafb] | 590 |
|
---|
[2b017ba] | 591 | send_call(irq, call);
|
---|
[162f919] | 592 | }
|
---|
| 593 | }
|
---|
| 594 |
|
---|
[cecb0789] | 595 | /** Send notification message.
|
---|
[874621f] | 596 | *
|
---|
[da1bafb] | 597 | * @param irq IRQ structure.
|
---|
| 598 | * @param a1 Driver-specific payload argument.
|
---|
| 599 | * @param a2 Driver-specific payload argument.
|
---|
| 600 | * @param a3 Driver-specific payload argument.
|
---|
| 601 | * @param a4 Driver-specific payload argument.
|
---|
| 602 | * @param a5 Driver-specific payload argument.
|
---|
| 603 | *
|
---|
[162f919] | 604 | */
|
---|
[96b02eb9] | 605 | void ipc_irq_send_msg(irq_t *irq, sysarg_t a1, sysarg_t a2, sysarg_t a3,
|
---|
| 606 | sysarg_t a4, sysarg_t a5)
|
---|
[162f919] | 607 | {
|
---|
[da1bafb] | 608 | irq_spinlock_lock(&irq->lock, true);
|
---|
| 609 |
|
---|
[cecb0789] | 610 | if (irq->notif_cfg.answerbox) {
|
---|
[da1bafb] | 611 | call_t *call = ipc_call_alloc(FRAME_ATOMIC);
|
---|
[cecb0789] | 612 | if (!call) {
|
---|
[da1bafb] | 613 | irq_spinlock_unlock(&irq->lock, true);
|
---|
[cecb0789] | 614 | return;
|
---|
[b14e35f2] | 615 | }
|
---|
[da1bafb] | 616 |
|
---|
[cecb0789] | 617 | call->flags |= IPC_CALL_NOTIF;
|
---|
| 618 | /* Put a counter to the message */
|
---|
| 619 | call->priv = ++irq->notif_cfg.counter;
|
---|
[da1bafb] | 620 |
|
---|
[228e490] | 621 | IPC_SET_IMETHOD(call->data, irq->notif_cfg.imethod);
|
---|
[cecb0789] | 622 | IPC_SET_ARG1(call->data, a1);
|
---|
| 623 | IPC_SET_ARG2(call->data, a2);
|
---|
| 624 | IPC_SET_ARG3(call->data, a3);
|
---|
| 625 | IPC_SET_ARG4(call->data, a4);
|
---|
| 626 | IPC_SET_ARG5(call->data, a5);
|
---|
| 627 |
|
---|
| 628 | send_call(irq, call);
|
---|
[b14e35f2] | 629 | }
|
---|
[da1bafb] | 630 |
|
---|
| 631 | irq_spinlock_unlock(&irq->lock, true);
|
---|
[162f919] | 632 | }
|
---|
[b45c443] | 633 |
|
---|
[cc73a8a1] | 634 | /** @}
|
---|
[b45c443] | 635 | */
|
---|