source: mainline/kernel/generic/src/ipc/irq.c@ 49319ac

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 49319ac was 49319ac, checked in by Jakub Vana <jakub.vana@…>, 18 years ago

SIMICS added as a simulator kernel runs on

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[162f919]1/*
2 * Copyright (C) 2006 Ondrej Palkovsky
[2b017ba]3 * Copyright (C) 2006 Jakub Jermar
[162f919]4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
[cc73a8a1]30/** @addtogroup genericipc
[b45c443]31 * @{
32 */
[cc73a8a1]33/**
34 * @file
35 * @brief IRQ notification framework.
[bdc5c516]36 *
37 * This framework allows applications to register to receive a notification
38 * when interrupt is detected. The application may provide a simple 'top-half'
39 * handler as part of its registration, which can perform simple operations
40 * (read/write port/memory, add information to notification ipc message).
41 *
42 * The structure of a notification message is as follows:
[2b017ba]43 * - METHOD: method as registered by the SYS_IPC_REGISTER_IRQ syscall
[43752b6]44 * - ARG1: payload modified by a 'top-half' handler
[2b017ba]45 * - ARG2: payload modified by a 'top-half' handler
46 * - ARG3: payload modified by a 'top-half' handler
[43752b6]47 * - in_phone_hash: interrupt counter (may be needed to assure correct order
[bdc5c516]48 * in multithreaded drivers)
49 */
50
[162f919]51#include <arch.h>
52#include <mm/slab.h>
53#include <errno.h>
[2b017ba]54#include <ddi/irq.h>
[162f919]55#include <ipc/ipc.h>
56#include <ipc/irq.h>
[e3c762cd]57#include <syscall/copy.h>
[d0c5901]58#include <console/console.h>
[253f35a1]59#include <print.h>
[162f919]60
[2b017ba]61/** Execute code associated with IRQ notification.
62 *
63 * @param call Notification call.
64 * @param code Top-half pseudocode.
65 */
[162f919]66static void code_execute(call_t *call, irq_code_t *code)
67{
68 int i;
[7f1c620]69 unative_t dstval = 0;
[ae971b3e]70
[162f919]71 if (!code)
72 return;
73
74 for (i=0; i < code->cmdcount;i++) {
75 switch (code->cmds[i].cmd) {
76 case CMD_MEM_READ_1:
[7f1c620]77 dstval = *((uint8_t *)code->cmds[i].addr);
[162f919]78 break;
79 case CMD_MEM_READ_2:
[7f1c620]80 dstval = *((uint16_t *)code->cmds[i].addr);
[162f919]81 break;
82 case CMD_MEM_READ_4:
[7f1c620]83 dstval = *((uint32_t *)code->cmds[i].addr);
[162f919]84 break;
85 case CMD_MEM_READ_8:
[7f1c620]86 dstval = *((uint64_t *)code->cmds[i].addr);
[162f919]87 break;
88 case CMD_MEM_WRITE_1:
[7f1c620]89 *((uint8_t *)code->cmds[i].addr) = code->cmds[i].value;
[162f919]90 break;
91 case CMD_MEM_WRITE_2:
[7f1c620]92 *((uint16_t *)code->cmds[i].addr) = code->cmds[i].value;
[162f919]93 break;
94 case CMD_MEM_WRITE_4:
[7f1c620]95 *((uint32_t *)code->cmds[i].addr) = code->cmds[i].value;
[162f919]96 break;
97 case CMD_MEM_WRITE_8:
[7f1c620]98 *((uint64_t *)code->cmds[i].addr) = code->cmds[i].value;
[162f919]99 break;
[bdc5c516]100#if defined(ia32) || defined(amd64)
101 case CMD_PORT_READ_1:
[43752b6]102 dstval = inb((long)code->cmds[i].addr);
[bdc5c516]103 break;
104 case CMD_PORT_WRITE_1:
105 outb((long)code->cmds[i].addr, code->cmds[i].value);
106 break;
[d0c5901]107#endif
[49319ac]108#if defined(ia64) && defined(SKI)
[d0c5901]109 case CMD_IA64_GETCHAR:
[43752b6]110 dstval = _getc(&ski_uconsole);
[d0c5901]111 break;
[732fd3c]112#endif
[ae971b3e]113#if defined(ppc32)
[732fd3c]114 case CMD_PPC32_GETCHAR:
[43752b6]115 dstval = cuda_get_scancode();
[732fd3c]116 break;
[bdc5c516]117#endif
[162f919]118 default:
119 break;
120 }
[43752b6]121 if (code->cmds[i].dstarg && code->cmds[i].dstarg < 4) {
122 call->data.args[code->cmds[i].dstarg] = dstval;
123 }
[162f919]124 }
125}
126
127static void code_free(irq_code_t *code)
128{
129 if (code) {
130 free(code->cmds);
131 free(code);
132 }
133}
134
135static irq_code_t * code_from_uspace(irq_code_t *ucode)
136{
137 irq_code_t *code;
138 irq_cmd_t *ucmds;
[e3c762cd]139 int rc;
[162f919]140
141 code = malloc(sizeof(*code), 0);
[e3c762cd]142 rc = copy_from_uspace(code, ucode, sizeof(*code));
143 if (rc != 0) {
144 free(code);
145 return NULL;
146 }
[162f919]147
148 if (code->cmdcount > IRQ_MAX_PROG_SIZE) {
149 free(code);
150 return NULL;
151 }
152 ucmds = code->cmds;
153 code->cmds = malloc(sizeof(code->cmds[0]) * (code->cmdcount), 0);
[e3c762cd]154 rc = copy_from_uspace(code->cmds, ucmds, sizeof(code->cmds[0]) * (code->cmdcount));
155 if (rc != 0) {
156 free(code->cmds);
157 free(code);
158 return NULL;
159 }
[162f919]160
161 return code;
162}
163
[2b017ba]164/** Unregister task from IRQ notification.
165 *
166 * @param box Answerbox associated with the notification.
167 * @param inr IRQ numbe.
168 * @param devno Device number.
169 */
170void ipc_irq_unregister(answerbox_t *box, inr_t inr, devno_t devno)
[162f919]171{
172 ipl_t ipl;
[2b017ba]173 irq_t *irq;
[162f919]174
175 ipl = interrupts_disable();
[2b017ba]176 irq = irq_find_and_lock(inr, devno);
177 if (irq) {
178 if (irq->notif_cfg.answerbox == box) {
[b14e35f2]179 code_free(irq->notif_cfg.code);
[4874c2d]180 irq->notif_cfg.notify = false;
[2b017ba]181 irq->notif_cfg.answerbox = NULL;
[4874c2d]182 irq->notif_cfg.code = NULL;
[2b017ba]183 irq->notif_cfg.method = 0;
184 irq->notif_cfg.counter = 0;
[b14e35f2]185
186 spinlock_lock(&box->irq_lock);
187 list_remove(&irq->notif_cfg.link);
188 spinlock_unlock(&box->irq_lock);
189
[2b017ba]190 spinlock_unlock(&irq->lock);
191 }
[162f919]192 }
193 interrupts_restore(ipl);
194}
195
[2b017ba]196/** Register an answerbox as a receiving end for IRQ notifications.
197 *
198 * @param box Receiving answerbox.
199 * @param inr IRQ number.
200 * @param devno Device number.
201 * @param method Method to be associated with the notification.
202 * @param ucode Uspace pointer to top-half pseudocode.
203 *
204 * @return EBADMEM, ENOENT or EEXISTS on failure or 0 on success.
205 */
[b14e35f2]206int ipc_irq_register(answerbox_t *box, inr_t inr, devno_t devno, unative_t method, irq_code_t *ucode)
[162f919]207{
208 ipl_t ipl;
209 irq_code_t *code;
[2b017ba]210 irq_t *irq;
[162f919]211
212 if (ucode) {
213 code = code_from_uspace(ucode);
214 if (!code)
215 return EBADMEM;
216 } else
217 code = NULL;
218
219 ipl = interrupts_disable();
[2b017ba]220 irq = irq_find_and_lock(inr, devno);
221 if (!irq) {
222 interrupts_restore(ipl);
223 code_free(code);
224 return ENOENT;
225 }
226
227 if (irq->notif_cfg.answerbox) {
228 spinlock_unlock(&irq->lock);
[162f919]229 interrupts_restore(ipl);
230 code_free(code);
231 return EEXISTS;
232 }
[2b017ba]233
[4874c2d]234 irq->notif_cfg.notify = true;
[2b017ba]235 irq->notif_cfg.answerbox = box;
236 irq->notif_cfg.method = method;
237 irq->notif_cfg.code = code;
238 irq->notif_cfg.counter = 0;
[b14e35f2]239
240 spinlock_lock(&box->irq_lock);
241 list_append(&irq->notif_cfg.link, &box->irq_head);
242 spinlock_unlock(&box->irq_lock);
243
[2b017ba]244 spinlock_unlock(&irq->lock);
[162f919]245 interrupts_restore(ipl);
246
247 return 0;
248}
249
[2b017ba]250/** Add call to proper answerbox queue.
251 *
252 * Assume irq->lock is locked.
[874621f]253 *
[2b017ba]254 */
255static void send_call(irq_t *irq, call_t *call)
[874621f]256{
[2b017ba]257 spinlock_lock(&irq->notif_cfg.answerbox->irq_lock);
258 list_append(&call->link, &irq->notif_cfg.answerbox->irq_notifs);
259 spinlock_unlock(&irq->notif_cfg.answerbox->irq_lock);
[874621f]260
[2b017ba]261 waitq_wakeup(&irq->notif_cfg.answerbox->wq, WAKEUP_FIRST);
[874621f]262}
263
264/** Send notification message
265 *
266 */
[2b017ba]267void ipc_irq_send_msg(irq_t *irq, unative_t a1, unative_t a2, unative_t a3)
[874621f]268{
269 call_t *call;
270
[2b017ba]271 spinlock_lock(&irq->lock);
[874621f]272
[2b017ba]273 if (irq->notif_cfg.answerbox) {
[874621f]274 call = ipc_call_alloc(FRAME_ATOMIC);
275 if (!call) {
[2b017ba]276 spinlock_unlock(&irq->lock);
[874621f]277 return;
278 }
279 call->flags |= IPC_CALL_NOTIF;
[2b017ba]280 IPC_SET_METHOD(call->data, irq->notif_cfg.method);
[43752b6]281 IPC_SET_ARG1(call->data, a1);
[874621f]282 IPC_SET_ARG2(call->data, a2);
283 IPC_SET_ARG3(call->data, a3);
[43752b6]284 /* Put a counter to the message */
[2b017ba]285 call->private = ++irq->notif_cfg.counter;
[874621f]286
[2b017ba]287 send_call(irq, call);
[874621f]288 }
[2b017ba]289 spinlock_unlock(&irq->lock);
[874621f]290}
291
[f3a3f0d7]292/** Notify task that an irq had occurred.
[162f919]293 *
[2b017ba]294 * We expect interrupts to be disabled and the irq->lock already held.
[162f919]295 */
[2b017ba]296void ipc_irq_send_notif(irq_t *irq)
[162f919]297{
298 call_t *call;
299
[2b017ba]300 ASSERT(irq);
[162f919]301
[2b017ba]302 if (irq->notif_cfg.answerbox) {
[162f919]303 call = ipc_call_alloc(FRAME_ATOMIC);
[d8f7362]304 if (!call) {
305 return;
306 }
[162f919]307 call->flags |= IPC_CALL_NOTIF;
[43752b6]308 /* Put a counter to the message */
[2b017ba]309 call->private = ++irq->notif_cfg.counter;
[43752b6]310 /* Set up args */
[2b017ba]311 IPC_SET_METHOD(call->data, irq->notif_cfg.method);
[162f919]312
313 /* Execute code to handle irq */
[2b017ba]314 code_execute(call, irq->notif_cfg.code);
[874621f]315
[2b017ba]316 send_call(irq, call);
[162f919]317 }
318}
319
[2b017ba]320/** Disconnect all IRQ notifications from an answerbox.
[b14e35f2]321 *
322 * This function is effective because the answerbox contains
323 * list of all irq_t structures that are registered to
324 * send notifications to it.
[874621f]325 *
[2b017ba]326 * @param box Answerbox for which we want to carry out the cleanup.
[162f919]327 */
328void ipc_irq_cleanup(answerbox_t *box)
329{
[b14e35f2]330 ipl_t ipl;
331
332loop:
333 ipl = interrupts_disable();
334 spinlock_lock(&box->irq_lock);
335
336 while (box->irq_head.next != &box->irq_head) {
337 link_t *cur = box->irq_head.next;
338 irq_t *irq;
339
340 irq = list_get_instance(cur, irq_t, notif_cfg.link);
341 if (!spinlock_trylock(&irq->lock)) {
342 /*
343 * Avoid deadlock by trying again.
344 */
345 spinlock_unlock(&box->irq_lock);
346 interrupts_restore(ipl);
347 goto loop;
348 }
349
350 ASSERT(irq->notif_cfg.answerbox == box);
351
352 list_remove(&irq->notif_cfg.link);
353
354 /*
355 * Don't forget to free any top-half pseudocode.
356 */
357 code_free(irq->notif_cfg.code);
358
359 irq->notif_cfg.notify = false;
360 irq->notif_cfg.answerbox = NULL;
361 irq->notif_cfg.code = NULL;
362 irq->notif_cfg.method = 0;
363 irq->notif_cfg.counter = 0;
364
365 spinlock_unlock(&irq->lock);
366 }
367
368 spinlock_unlock(&box->irq_lock);
369 interrupts_restore(ipl);
[162f919]370}
[b45c443]371
[cc73a8a1]372/** @}
[b45c443]373 */
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