[162f919] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2006 Ondrej Palkovsky
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| 3 | * Copyright (c) 2006 Jakub Jermar
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[162f919] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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[cc73a8a1] | 30 | /** @addtogroup genericipc
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[b45c443] | 31 | * @{
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| 32 | */
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[da1bafb] | 33 |
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[cc73a8a1] | 34 | /**
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| 35 | * @file
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| 36 | * @brief IRQ notification framework.
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[bdc5c516] | 37 | *
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[8820544] | 38 | * This framework allows applications to subscribe to receive a notification
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[a5d0143] | 39 | * when an interrupt is detected. The application may provide a simple
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| 40 | * 'top-half' handler as part of its registration, which can perform simple
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| 41 | * operations (read/write port/memory, add information to notification IPC
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| 42 | * message).
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[bdc5c516] | 43 | *
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| 44 | * The structure of a notification message is as follows:
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[8820544] | 45 | * - IMETHOD: interface and method as set by the SYS_IPC_IRQ_SUBSCRIBE syscall
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[56c167c] | 46 | * - ARG1: payload modified by a 'top-half' handler (scratch[1])
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| 47 | * - ARG2: payload modified by a 'top-half' handler (scratch[2])
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| 48 | * - ARG3: payload modified by a 'top-half' handler (scratch[3])
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| 49 | * - ARG4: payload modified by a 'top-half' handler (scratch[4])
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| 50 | * - ARG5: payload modified by a 'top-half' handler (scratch[5])
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[43752b6] | 51 | * - in_phone_hash: interrupt counter (may be needed to assure correct order
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[228e490] | 52 | * in multithreaded drivers)
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[bdc5c516] | 53 | */
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| 54 |
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[162f919] | 55 | #include <arch.h>
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[63e27ef] | 56 | #include <assert.h>
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[162f919] | 57 | #include <mm/slab.h>
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[a996ae31] | 58 | #include <mm/page.h>
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| 59 | #include <mm/km.h>
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[162f919] | 60 | #include <errno.h>
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[2b017ba] | 61 | #include <ddi/irq.h>
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[162f919] | 62 | #include <ipc/ipc.h>
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| 63 | #include <ipc/irq.h>
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[e3c762cd] | 64 | #include <syscall/copy.h>
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[d0c5901] | 65 | #include <console/console.h>
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[253f35a1] | 66 | #include <print.h>
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[a996ae31] | 67 | #include <macros.h>
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[3f74275] | 68 | #include <cap/cap.h>
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[a996ae31] | 69 |
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| 70 | static void ranges_unmap(irq_pio_range_t *ranges, size_t rangecount)
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| 71 | {
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[56c167c] | 72 | for (size_t i = 0; i < rangecount; i++) {
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[472d813] | 73 | #ifdef IO_SPACE_BOUNDARY
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[a996ae31] | 74 | if ((void *) ranges[i].base >= IO_SPACE_BOUNDARY)
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[472d813] | 75 | #endif
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[a996ae31] | 76 | km_unmap(ranges[i].base, ranges[i].size);
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| 77 | }
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| 78 | }
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| 79 |
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[b7fd2a0] | 80 | static errno_t ranges_map_and_apply(irq_pio_range_t *ranges, size_t rangecount,
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[a996ae31] | 81 | irq_cmd_t *cmds, size_t cmdcount)
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| 82 | {
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| 83 | /* Copy the physical base addresses aside. */
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[11b285d] | 84 | uintptr_t *pbase = malloc(rangecount * sizeof(uintptr_t));
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[7473807] | 85 | if (!pbase)
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| 86 | return ENOMEM;
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[56c167c] | 87 | for (size_t i = 0; i < rangecount; i++)
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[a996ae31] | 88 | pbase[i] = ranges[i].base;
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[a35b458] | 89 |
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[a996ae31] | 90 | /* Map the PIO ranges into the kernel virtual address space. */
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[56c167c] | 91 | for (size_t i = 0; i < rangecount; i++) {
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[472d813] | 92 | #ifdef IO_SPACE_BOUNDARY
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[a996ae31] | 93 | if ((void *) ranges[i].base < IO_SPACE_BOUNDARY)
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| 94 | continue;
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[472d813] | 95 | #endif
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[a996ae31] | 96 | ranges[i].base = km_map(pbase[i], ranges[i].size,
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| 97 | PAGE_READ | PAGE_WRITE | PAGE_KERNEL | PAGE_NOT_CACHEABLE);
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| 98 | if (!ranges[i].base) {
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| 99 | ranges_unmap(ranges, i);
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| 100 | free(pbase);
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| 101 | return ENOMEM;
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| 102 | }
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| 103 | }
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[a35b458] | 104 |
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[a5d0143] | 105 | /* Rewrite the IRQ code addresses from physical to kernel virtual. */
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[56c167c] | 106 | for (size_t i = 0; i < cmdcount; i++) {
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[a996ae31] | 107 | uintptr_t addr;
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[f2bbe8c] | 108 | size_t size;
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[a35b458] | 109 |
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[a996ae31] | 110 | /* Process only commands that use an address. */
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| 111 | switch (cmds[i].cmd) {
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| 112 | case CMD_PIO_READ_8:
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[56c167c] | 113 | case CMD_PIO_WRITE_8:
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| 114 | case CMD_PIO_WRITE_A_8:
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[f2bbe8c] | 115 | size = 1;
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| 116 | break;
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[56c167c] | 117 | case CMD_PIO_READ_16:
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| 118 | case CMD_PIO_WRITE_16:
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| 119 | case CMD_PIO_WRITE_A_16:
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[f2bbe8c] | 120 | size = 2;
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| 121 | break;
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[56c167c] | 122 | case CMD_PIO_READ_32:
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| 123 | case CMD_PIO_WRITE_32:
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| 124 | case CMD_PIO_WRITE_A_32:
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[f2bbe8c] | 125 | size = 4;
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[a996ae31] | 126 | break;
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| 127 | default:
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| 128 | /* Move onto the next command. */
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| 129 | continue;
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| 130 | }
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[a35b458] | 131 |
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[a996ae31] | 132 | addr = (uintptr_t) cmds[i].addr;
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[a35b458] | 133 |
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[56c167c] | 134 | size_t j;
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[a996ae31] | 135 | for (j = 0; j < rangecount; j++) {
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| 136 | /* Find the matching range. */
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[f2bbe8c] | 137 | if (!iswithin(pbase[j], ranges[j].size, addr, size))
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[a996ae31] | 138 | continue;
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[a35b458] | 139 |
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[a996ae31] | 140 | /* Switch the command to a kernel virtual address. */
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| 141 | addr -= pbase[j];
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| 142 | addr += ranges[j].base;
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[a35b458] | 143 |
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[a996ae31] | 144 | cmds[i].addr = (void *) addr;
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| 145 | break;
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[bd8c6537] | 146 | }
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[a35b458] | 147 |
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[bd8c6537] | 148 | if (j == rangecount) {
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| 149 | /*
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| 150 | * The address used in this command is outside of all
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| 151 | * defined ranges.
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| 152 | */
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| 153 | ranges_unmap(ranges, rangecount);
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| 154 | free(pbase);
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| 155 | return EINVAL;
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| 156 | }
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[a996ae31] | 157 | }
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[a35b458] | 158 |
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[a996ae31] | 159 | free(pbase);
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| 160 | return EOK;
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| 161 | }
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[162f919] | 162 |
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[a5d0143] | 163 | /** Statically check the top-half IRQ code
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[8486c07] | 164 | *
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[a5d0143] | 165 | * Check the top-half IRQ code for invalid or unsafe constructs.
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[8486c07] | 166 | *
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| 167 | */
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[b7fd2a0] | 168 | static errno_t code_check(irq_cmd_t *cmds, size_t cmdcount)
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[8486c07] | 169 | {
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| 170 | for (size_t i = 0; i < cmdcount; i++) {
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| 171 | /*
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| 172 | * Check for accepted ranges.
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| 173 | */
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| 174 | if (cmds[i].cmd >= CMD_LAST)
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| 175 | return EINVAL;
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[a35b458] | 176 |
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[8486c07] | 177 | if (cmds[i].srcarg >= IPC_CALL_LEN)
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| 178 | return EINVAL;
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[a35b458] | 179 |
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[8486c07] | 180 | if (cmds[i].dstarg >= IPC_CALL_LEN)
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| 181 | return EINVAL;
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[a35b458] | 182 |
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[8486c07] | 183 | switch (cmds[i].cmd) {
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| 184 | case CMD_PREDICATE:
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| 185 | /*
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| 186 | * Check for control flow overflow.
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| 187 | * Note that jumping just beyond the last
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| 188 | * command is a correct behaviour.
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| 189 | */
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| 190 | if (i + cmds[i].value > cmdcount)
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| 191 | return EINVAL;
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[a35b458] | 192 |
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[8486c07] | 193 | break;
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| 194 | default:
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| 195 | break;
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| 196 | }
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| 197 | }
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[a35b458] | 198 |
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[8486c07] | 199 | return EOK;
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| 200 | }
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| 201 |
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[a5d0143] | 202 | /** Free the top-half IRQ code.
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[8b243f2] | 203 | *
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[a5d0143] | 204 | * @param code Pointer to the top-half IRQ code.
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[da1bafb] | 205 | *
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[8b243f2] | 206 | */
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[162f919] | 207 | static void code_free(irq_code_t *code)
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| 208 | {
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| 209 | if (code) {
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[a996ae31] | 210 | ranges_unmap(code->ranges, code->rangecount);
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| 211 | free(code->ranges);
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[162f919] | 212 | free(code->cmds);
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| 213 | free(code);
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| 214 | }
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| 215 | }
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| 216 |
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[a5d0143] | 217 | /** Copy the top-half IRQ code from userspace into the kernel.
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[8b243f2] | 218 | *
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[a5d0143] | 219 | * @param ucode Userspace address of the top-half IRQ code.
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[da1bafb] | 220 | *
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[a5d0143] | 221 | * @return Kernel address of the copied IRQ code.
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[8b243f2] | 222 | *
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| 223 | */
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| 224 | static irq_code_t *code_from_uspace(irq_code_t *ucode)
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[162f919] | 225 | {
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[a996ae31] | 226 | irq_pio_range_t *ranges = NULL;
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| 227 | irq_cmd_t *cmds = NULL;
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[a35b458] | 228 |
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[11b285d] | 229 | irq_code_t *code = malloc(sizeof(*code));
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[7473807] | 230 | if (!code)
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| 231 | return NULL;
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[b7fd2a0] | 232 | errno_t rc = copy_from_uspace(code, ucode, sizeof(*code));
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[a996ae31] | 233 | if (rc != EOK)
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| 234 | goto error;
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[a35b458] | 235 |
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[a996ae31] | 236 | if ((code->rangecount > IRQ_MAX_RANGE_COUNT) ||
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| 237 | (code->cmdcount > IRQ_MAX_PROG_SIZE))
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| 238 | goto error;
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[a35b458] | 239 |
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[11b285d] | 240 | ranges = malloc(sizeof(code->ranges[0]) * code->rangecount);
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[7473807] | 241 | if (!ranges)
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| 242 | goto error;
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[a996ae31] | 243 | rc = copy_from_uspace(ranges, code->ranges,
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| 244 | sizeof(code->ranges[0]) * code->rangecount);
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| 245 | if (rc != EOK)
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| 246 | goto error;
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[a35b458] | 247 |
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[11b285d] | 248 | cmds = malloc(sizeof(code->cmds[0]) * code->cmdcount);
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[7473807] | 249 | if (!cmds)
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| 250 | goto error;
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[a996ae31] | 251 | rc = copy_from_uspace(cmds, code->cmds,
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[8b243f2] | 252 | sizeof(code->cmds[0]) * code->cmdcount);
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[a996ae31] | 253 | if (rc != EOK)
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| 254 | goto error;
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[a35b458] | 255 |
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[8486c07] | 256 | rc = code_check(cmds, code->cmdcount);
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| 257 | if (rc != EOK)
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| 258 | goto error;
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[a35b458] | 259 |
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[a996ae31] | 260 | rc = ranges_map_and_apply(ranges, code->rangecount, cmds,
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| 261 | code->cmdcount);
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| 262 | if (rc != EOK)
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| 263 | goto error;
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[a35b458] | 264 |
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[a996ae31] | 265 | code->ranges = ranges;
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| 266 | code->cmds = cmds;
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[a35b458] | 267 |
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[162f919] | 268 | return code;
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[a35b458] | 269 |
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[a996ae31] | 270 | error:
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| 271 | if (cmds)
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| 272 | free(cmds);
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[a35b458] | 273 |
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[a996ae31] | 274 | if (ranges)
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| 275 | free(ranges);
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[a35b458] | 276 |
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[a996ae31] | 277 | free(code);
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| 278 | return NULL;
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[162f919] | 279 | }
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| 280 |
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[c1f68b0] | 281 | static void irq_hash_out(irq_t *irq)
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| 282 | {
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| 283 | irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
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| 284 | irq_spinlock_lock(&irq->lock, false);
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[a35b458] | 285 |
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[c1f68b0] | 286 | if (irq->notif_cfg.hashed_in) {
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| 287 | /* Remove the IRQ from the uspace IRQ hash table. */
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| 288 | hash_table_remove_item(&irq_uspace_hash_table, &irq->link);
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| 289 | irq->notif_cfg.hashed_in = false;
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| 290 | }
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| 291 |
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| 292 | irq_spinlock_unlock(&irq->lock, false);
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| 293 | irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
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| 294 | }
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| 295 |
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[48bcf49] | 296 | static void irq_destroy(void *arg)
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| 297 | {
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| 298 | irq_t *irq = (irq_t *) arg;
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| 299 |
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[c1f68b0] | 300 | irq_hash_out(irq);
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| 301 |
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[48bcf49] | 302 | /* Free up the IRQ code and associated structures. */
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| 303 | code_free(irq->notif_cfg.code);
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[82d515e9] | 304 | slab_free(irq_cache, irq);
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[48bcf49] | 305 | }
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| 306 |
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| 307 | static kobject_ops_t irq_kobject_ops = {
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| 308 | .destroy = irq_destroy
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| 309 | };
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| 310 |
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[8820544] | 311 | /** Subscribe an answerbox as a receiving end for IRQ notifications.
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[2b017ba] | 312 | *
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[56c167c] | 313 | * @param box Receiving answerbox.
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| 314 | * @param inr IRQ number.
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[a5d0143] | 315 | * @param imethod Interface and method to be associated with the notification.
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| 316 | * @param ucode Uspace pointer to top-half IRQ code.
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[56c167c] | 317 | *
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[9233e9d] | 318 | * @param[out] uspace_handle Uspace pointer to IRQ capability handle
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| 319 | *
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| 320 | * @return Error code.
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[2b017ba] | 321 | *
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| 322 | */
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[b7fd2a0] | 323 | errno_t ipc_irq_subscribe(answerbox_t *box, inr_t inr, sysarg_t imethod,
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[eadaeae8] | 324 | irq_code_t *ucode, cap_irq_handle_t *uspace_handle)
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[162f919] | 325 | {
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[78ffb70] | 326 | if ((inr < 0) || (inr > last_inr))
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| 327 | return ELIMIT;
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[a35b458] | 328 |
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[da1bafb] | 329 | irq_code_t *code;
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[162f919] | 330 | if (ucode) {
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| 331 | code = code_from_uspace(ucode);
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| 332 | if (!code)
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| 333 | return EBADMEM;
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[da1bafb] | 334 | } else
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[162f919] | 335 | code = NULL;
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[a35b458] | 336 |
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[cecb0789] | 337 | /*
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[e9d15d9] | 338 | * Allocate and populate the IRQ kernel object.
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[cecb0789] | 339 | */
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[09d01f2] | 340 | cap_handle_t handle;
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[b7fd2a0] | 341 | errno_t rc = cap_alloc(TASK, &handle);
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[09d01f2] | 342 | if (rc != EOK)
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| 343 | return rc;
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[a35b458] | 344 |
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[09d01f2] | 345 | rc = copy_to_uspace(uspace_handle, &handle, sizeof(cap_handle_t));
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[9233e9d] | 346 | if (rc != EOK) {
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| 347 | cap_free(TASK, handle);
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| 348 | return rc;
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| 349 | }
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| 350 |
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[82d515e9] | 351 | irq_t *irq = (irq_t *) slab_alloc(irq_cache, FRAME_ATOMIC);
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[63d8f43] | 352 | if (!irq) {
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| 353 | cap_free(TASK, handle);
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| 354 | return ENOMEM;
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| 355 | }
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[48bcf49] | 356 |
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[11b285d] | 357 | kobject_t *kobject = malloc(sizeof(kobject_t));
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[48bcf49] | 358 | if (!kobject) {
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| 359 | cap_free(TASK, handle);
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[82d515e9] | 360 | slab_free(irq_cache, irq);
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[48bcf49] | 361 | return ENOMEM;
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| 362 | }
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[a35b458] | 363 |
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[cecb0789] | 364 | irq_initialize(irq);
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| 365 | irq->inr = inr;
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| 366 | irq->claim = ipc_irq_top_half_claim;
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[691eb52] | 367 | irq->handler = ipc_irq_top_half_handler;
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[4874c2d] | 368 | irq->notif_cfg.notify = true;
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[2b017ba] | 369 | irq->notif_cfg.answerbox = box;
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[228e490] | 370 | irq->notif_cfg.imethod = imethod;
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[2b017ba] | 371 | irq->notif_cfg.code = code;
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| 372 | irq->notif_cfg.counter = 0;
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[a35b458] | 373 |
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[cecb0789] | 374 | /*
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[9e87562] | 375 | * Insert the IRQ structure into the uspace IRQ hash table.
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[cecb0789] | 376 | */
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[da1bafb] | 377 | irq_spinlock_lock(&irq_uspace_hash_table_lock, true);
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| 378 | irq_spinlock_lock(&irq->lock, false);
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[a35b458] | 379 |
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[48bcf49] | 380 | irq->notif_cfg.hashed_in = true;
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[82cbf8c6] | 381 | hash_table_insert(&irq_uspace_hash_table, &irq->link);
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[a35b458] | 382 |
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[da1bafb] | 383 | irq_spinlock_unlock(&irq->lock, false);
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| 384 | irq_spinlock_unlock(&irq_uspace_hash_table_lock, true);
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[9e87562] | 385 |
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[48bcf49] | 386 | kobject_initialize(kobject, KOBJECT_TYPE_IRQ, irq, &irq_kobject_ops);
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| 387 | cap_publish(TASK, handle, kobject);
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[a35b458] | 388 |
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[9233e9d] | 389 | return EOK;
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[cecb0789] | 390 | }
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| 391 |
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[8820544] | 392 | /** Unsubscribe task from IRQ notification.
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[cecb0789] | 393 | *
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[3f74275] | 394 | * @param box Answerbox associated with the notification.
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| 395 | * @param handle IRQ capability handle.
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[56c167c] | 396 | *
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[cde999a] | 397 | * @return EOK on success or an error code.
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[56c167c] | 398 | *
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[cecb0789] | 399 | */
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[eadaeae8] | 400 | errno_t ipc_irq_unsubscribe(answerbox_t *box, cap_irq_handle_t handle)
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[cecb0789] | 401 | {
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[48bcf49] | 402 | kobject_t *kobj = cap_unpublish(TASK, handle, KOBJECT_TYPE_IRQ);
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| 403 | if (!kobj)
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[cecb0789] | 404 | return ENOENT;
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[a35b458] | 405 |
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[48bcf49] | 406 | assert(kobj->irq->notif_cfg.answerbox == box);
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| 407 |
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[c1f68b0] | 408 | irq_hash_out(kobj->irq);
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[48bcf49] | 409 |
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| 410 | kobject_put(kobj);
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[3f74275] | 411 | cap_free(TASK, handle);
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[a35b458] | 412 |
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[cecb0789] | 413 | return EOK;
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| 414 | }
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| 415 |
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[8b243f2] | 416 | /** Add a call to the proper answerbox queue.
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[2b017ba] | 417 | *
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[da1bafb] | 418 | * Assume irq->lock is locked and interrupts disabled.
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| 419 | *
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| 420 | * @param irq IRQ structure referencing the target answerbox.
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| 421 | * @param call IRQ notification call.
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[874621f] | 422 | *
|
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[2b017ba] | 423 | */
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| 424 | static void send_call(irq_t *irq, call_t *call)
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[874621f] | 425 | {
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[da1bafb] | 426 | irq_spinlock_lock(&irq->notif_cfg.answerbox->irq_lock, false);
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[cfaa35a] | 427 | list_append(&call->ab_link, &irq->notif_cfg.answerbox->irq_notifs);
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[da1bafb] | 428 | irq_spinlock_unlock(&irq->notif_cfg.answerbox->irq_lock, false);
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[a35b458] | 429 |
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[2b017ba] | 430 | waitq_wakeup(&irq->notif_cfg.answerbox->wq, WAKEUP_FIRST);
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[874621f] | 431 | }
|
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| 432 |
|
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[a5d0143] | 433 | /** Apply the top-half IRQ code to find out whether to accept the IRQ or not.
|
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[874621f] | 434 | *
|
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[da1bafb] | 435 | * @param irq IRQ structure.
|
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| 436 | *
|
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[a5d0143] | 437 | * @return IRQ_ACCEPT if the interrupt is accepted by the IRQ code.
|
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| 438 | * @return IRQ_DECLINE if the interrupt is not accepted byt the IRQ code.
|
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[cecb0789] | 439 | *
|
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[874621f] | 440 | */
|
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[cecb0789] | 441 | irq_ownership_t ipc_irq_top_half_claim(irq_t *irq)
|
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[874621f] | 442 | {
|
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[cecb0789] | 443 | irq_code_t *code = irq->notif_cfg.code;
|
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[da1bafb] | 444 | uint32_t *scratch = irq->notif_cfg.scratch;
|
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[a35b458] | 445 |
|
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[cecb0789] | 446 | if (!irq->notif_cfg.notify)
|
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| 447 | return IRQ_DECLINE;
|
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[a35b458] | 448 |
|
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[cecb0789] | 449 | if (!code)
|
---|
| 450 | return IRQ_DECLINE;
|
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[a35b458] | 451 |
|
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[01e39cbe] | 452 | for (size_t i = 0; i < code->cmdcount; i++) {
|
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[da1bafb] | 453 | uintptr_t srcarg = code->cmds[i].srcarg;
|
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| 454 | uintptr_t dstarg = code->cmds[i].dstarg;
|
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[a35b458] | 455 |
|
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[cecb0789] | 456 | switch (code->cmds[i].cmd) {
|
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| 457 | case CMD_PIO_READ_8:
|
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[8486c07] | 458 | scratch[dstarg] =
|
---|
| 459 | pio_read_8((ioport8_t *) code->cmds[i].addr);
|
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[cecb0789] | 460 | break;
|
---|
| 461 | case CMD_PIO_READ_16:
|
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[8486c07] | 462 | scratch[dstarg] =
|
---|
| 463 | pio_read_16((ioport16_t *) code->cmds[i].addr);
|
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[cecb0789] | 464 | break;
|
---|
| 465 | case CMD_PIO_READ_32:
|
---|
[8486c07] | 466 | scratch[dstarg] =
|
---|
| 467 | pio_read_32((ioport32_t *) code->cmds[i].addr);
|
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[cecb0789] | 468 | break;
|
---|
| 469 | case CMD_PIO_WRITE_8:
|
---|
| 470 | pio_write_8((ioport8_t *) code->cmds[i].addr,
|
---|
| 471 | (uint8_t) code->cmds[i].value);
|
---|
| 472 | break;
|
---|
| 473 | case CMD_PIO_WRITE_16:
|
---|
| 474 | pio_write_16((ioport16_t *) code->cmds[i].addr,
|
---|
| 475 | (uint16_t) code->cmds[i].value);
|
---|
| 476 | break;
|
---|
| 477 | case CMD_PIO_WRITE_32:
|
---|
| 478 | pio_write_32((ioport32_t *) code->cmds[i].addr,
|
---|
| 479 | (uint32_t) code->cmds[i].value);
|
---|
| 480 | break;
|
---|
[9cdac5a] | 481 | case CMD_PIO_WRITE_A_8:
|
---|
[8486c07] | 482 | pio_write_8((ioport8_t *) code->cmds[i].addr,
|
---|
| 483 | (uint8_t) scratch[srcarg]);
|
---|
[9cdac5a] | 484 | break;
|
---|
| 485 | case CMD_PIO_WRITE_A_16:
|
---|
[8486c07] | 486 | pio_write_16((ioport16_t *) code->cmds[i].addr,
|
---|
| 487 | (uint16_t) scratch[srcarg]);
|
---|
[9cdac5a] | 488 | break;
|
---|
| 489 | case CMD_PIO_WRITE_A_32:
|
---|
[8486c07] | 490 | pio_write_32((ioport32_t *) code->cmds[i].addr,
|
---|
| 491 | (uint32_t) scratch[srcarg]);
|
---|
| 492 | break;
|
---|
| 493 | case CMD_LOAD:
|
---|
| 494 | scratch[dstarg] = code->cmds[i].value;
|
---|
[9cdac5a] | 495 | break;
|
---|
[8486c07] | 496 | case CMD_AND:
|
---|
| 497 | scratch[dstarg] = scratch[srcarg] &
|
---|
| 498 | code->cmds[i].value;
|
---|
[cecb0789] | 499 | break;
|
---|
| 500 | case CMD_PREDICATE:
|
---|
[8486c07] | 501 | if (scratch[srcarg] == 0)
|
---|
[cecb0789] | 502 | i += code->cmds[i].value;
|
---|
[a35b458] | 503 |
|
---|
[cecb0789] | 504 | break;
|
---|
| 505 | case CMD_ACCEPT:
|
---|
| 506 | return IRQ_ACCEPT;
|
---|
| 507 | case CMD_DECLINE:
|
---|
| 508 | default:
|
---|
| 509 | return IRQ_DECLINE;
|
---|
| 510 | }
|
---|
[874621f] | 511 | }
|
---|
[a35b458] | 512 |
|
---|
[cecb0789] | 513 | return IRQ_DECLINE;
|
---|
[874621f] | 514 | }
|
---|
| 515 |
|
---|
[cecb0789] | 516 | /* IRQ top-half handler.
|
---|
[162f919] | 517 | *
|
---|
[2b017ba] | 518 | * We expect interrupts to be disabled and the irq->lock already held.
|
---|
[8b243f2] | 519 | *
|
---|
[da1bafb] | 520 | * @param irq IRQ structure.
|
---|
| 521 | *
|
---|
[162f919] | 522 | */
|
---|
[cecb0789] | 523 | void ipc_irq_top_half_handler(irq_t *irq)
|
---|
[162f919] | 524 | {
|
---|
[63e27ef] | 525 | assert(irq);
|
---|
[a35b458] | 526 |
|
---|
[63e27ef] | 527 | assert(interrupts_disabled());
|
---|
| 528 | assert(irq_spinlock_locked(&irq->lock));
|
---|
[a35b458] | 529 |
|
---|
[2b017ba] | 530 | if (irq->notif_cfg.answerbox) {
|
---|
[da1bafb] | 531 | call_t *call = ipc_call_alloc(FRAME_ATOMIC);
|
---|
[cecb0789] | 532 | if (!call)
|
---|
[d8f7362] | 533 | return;
|
---|
[a35b458] | 534 |
|
---|
[162f919] | 535 | call->flags |= IPC_CALL_NOTIF;
|
---|
[43752b6] | 536 | /* Put a counter to the message */
|
---|
[0c1a5d8a] | 537 | call->priv = ++irq->notif_cfg.counter;
|
---|
[a35b458] | 538 |
|
---|
[43752b6] | 539 | /* Set up args */
|
---|
[228e490] | 540 | IPC_SET_IMETHOD(call->data, irq->notif_cfg.imethod);
|
---|
[cecb0789] | 541 | IPC_SET_ARG1(call->data, irq->notif_cfg.scratch[1]);
|
---|
| 542 | IPC_SET_ARG2(call->data, irq->notif_cfg.scratch[2]);
|
---|
| 543 | IPC_SET_ARG3(call->data, irq->notif_cfg.scratch[3]);
|
---|
| 544 | IPC_SET_ARG4(call->data, irq->notif_cfg.scratch[4]);
|
---|
| 545 | IPC_SET_ARG5(call->data, irq->notif_cfg.scratch[5]);
|
---|
[a35b458] | 546 |
|
---|
[2b017ba] | 547 | send_call(irq, call);
|
---|
[162f919] | 548 | }
|
---|
| 549 | }
|
---|
| 550 |
|
---|
[cecb0789] | 551 | /** Send notification message.
|
---|
[874621f] | 552 | *
|
---|
[da1bafb] | 553 | * @param irq IRQ structure.
|
---|
| 554 | * @param a1 Driver-specific payload argument.
|
---|
| 555 | * @param a2 Driver-specific payload argument.
|
---|
| 556 | * @param a3 Driver-specific payload argument.
|
---|
| 557 | * @param a4 Driver-specific payload argument.
|
---|
| 558 | * @param a5 Driver-specific payload argument.
|
---|
| 559 | *
|
---|
[162f919] | 560 | */
|
---|
[96b02eb9] | 561 | void ipc_irq_send_msg(irq_t *irq, sysarg_t a1, sysarg_t a2, sysarg_t a3,
|
---|
| 562 | sysarg_t a4, sysarg_t a5)
|
---|
[162f919] | 563 | {
|
---|
[da1bafb] | 564 | irq_spinlock_lock(&irq->lock, true);
|
---|
[a35b458] | 565 |
|
---|
[cecb0789] | 566 | if (irq->notif_cfg.answerbox) {
|
---|
[da1bafb] | 567 | call_t *call = ipc_call_alloc(FRAME_ATOMIC);
|
---|
[cecb0789] | 568 | if (!call) {
|
---|
[da1bafb] | 569 | irq_spinlock_unlock(&irq->lock, true);
|
---|
[cecb0789] | 570 | return;
|
---|
[b14e35f2] | 571 | }
|
---|
[a35b458] | 572 |
|
---|
[cecb0789] | 573 | call->flags |= IPC_CALL_NOTIF;
|
---|
| 574 | /* Put a counter to the message */
|
---|
| 575 | call->priv = ++irq->notif_cfg.counter;
|
---|
[a35b458] | 576 |
|
---|
[228e490] | 577 | IPC_SET_IMETHOD(call->data, irq->notif_cfg.imethod);
|
---|
[cecb0789] | 578 | IPC_SET_ARG1(call->data, a1);
|
---|
| 579 | IPC_SET_ARG2(call->data, a2);
|
---|
| 580 | IPC_SET_ARG3(call->data, a3);
|
---|
| 581 | IPC_SET_ARG4(call->data, a4);
|
---|
| 582 | IPC_SET_ARG5(call->data, a5);
|
---|
[a35b458] | 583 |
|
---|
[cecb0789] | 584 | send_call(irq, call);
|
---|
[b14e35f2] | 585 | }
|
---|
[a35b458] | 586 |
|
---|
[da1bafb] | 587 | irq_spinlock_unlock(&irq->lock, true);
|
---|
[162f919] | 588 | }
|
---|
[b45c443] | 589 |
|
---|
[cc73a8a1] | 590 | /** @}
|
---|
[b45c443] | 591 | */
|
---|