[162f919] | 1 | /*
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| 2 | * Copyright (C) 2006 Ondrej Palkovsky
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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[cc73a8a1] | 29 | /** @addtogroup genericipc
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[b45c443] | 30 | * @{
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| 31 | */
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[cc73a8a1] | 32 | /**
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| 33 | * @file
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| 34 | * @brief IRQ notification framework.
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[bdc5c516] | 35 | *
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| 36 | * This framework allows applications to register to receive a notification
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| 37 | * when interrupt is detected. The application may provide a simple 'top-half'
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| 38 | * handler as part of its registration, which can perform simple operations
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| 39 | * (read/write port/memory, add information to notification ipc message).
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| 40 | *
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| 41 | * The structure of a notification message is as follows:
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[43752b6] | 42 | * - METHOD: interrupt number
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| 43 | * - ARG1: payload modified by a 'top-half' handler
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| 44 | * - ARG2: payload
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| 45 | * - ARG3: payload
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| 46 | * - in_phone_hash: interrupt counter (may be needed to assure correct order
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[bdc5c516] | 47 | * in multithreaded drivers)
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| 48 | */
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| 49 |
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[162f919] | 50 | #include <arch.h>
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| 51 | #include <mm/slab.h>
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| 52 | #include <errno.h>
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| 53 | #include <ipc/ipc.h>
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| 54 | #include <ipc/irq.h>
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[bdc5c516] | 55 | #include <atomic.h>
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[e3c762cd] | 56 | #include <syscall/copy.h>
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[d0c5901] | 57 | #include <console/console.h>
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[162f919] | 58 |
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| 59 | typedef struct {
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| 60 | SPINLOCK_DECLARE(lock);
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| 61 | answerbox_t *box;
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| 62 | irq_code_t *code;
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[bdc5c516] | 63 | atomic_t counter;
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[162f919] | 64 | } ipc_irq_t;
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| 65 |
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| 66 |
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| 67 | static ipc_irq_t *irq_conns = NULL;
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| 68 | static int irq_conns_size;
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| 69 |
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| 70 | #include <print.h>
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| 71 | /* Execute code associated with IRQ notification */
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| 72 | static void code_execute(call_t *call, irq_code_t *code)
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| 73 | {
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| 74 | int i;
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[7f1c620] | 75 | unative_t dstval = 0;
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[ae971b3e] | 76 |
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[162f919] | 77 | if (!code)
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| 78 | return;
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| 79 |
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| 80 | for (i=0; i < code->cmdcount;i++) {
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| 81 | switch (code->cmds[i].cmd) {
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| 82 | case CMD_MEM_READ_1:
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[7f1c620] | 83 | dstval = *((uint8_t *)code->cmds[i].addr);
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[162f919] | 84 | break;
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| 85 | case CMD_MEM_READ_2:
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[7f1c620] | 86 | dstval = *((uint16_t *)code->cmds[i].addr);
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[162f919] | 87 | break;
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| 88 | case CMD_MEM_READ_4:
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[7f1c620] | 89 | dstval = *((uint32_t *)code->cmds[i].addr);
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[162f919] | 90 | break;
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| 91 | case CMD_MEM_READ_8:
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[7f1c620] | 92 | dstval = *((uint64_t *)code->cmds[i].addr);
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[162f919] | 93 | break;
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| 94 | case CMD_MEM_WRITE_1:
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[7f1c620] | 95 | *((uint8_t *)code->cmds[i].addr) = code->cmds[i].value;
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[162f919] | 96 | break;
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| 97 | case CMD_MEM_WRITE_2:
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[7f1c620] | 98 | *((uint16_t *)code->cmds[i].addr) = code->cmds[i].value;
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[162f919] | 99 | break;
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| 100 | case CMD_MEM_WRITE_4:
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[7f1c620] | 101 | *((uint32_t *)code->cmds[i].addr) = code->cmds[i].value;
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[162f919] | 102 | break;
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| 103 | case CMD_MEM_WRITE_8:
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[7f1c620] | 104 | *((uint64_t *)code->cmds[i].addr) = code->cmds[i].value;
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[162f919] | 105 | break;
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[bdc5c516] | 106 | #if defined(ia32) || defined(amd64)
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| 107 | case CMD_PORT_READ_1:
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[43752b6] | 108 | dstval = inb((long)code->cmds[i].addr);
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[bdc5c516] | 109 | break;
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| 110 | case CMD_PORT_WRITE_1:
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| 111 | outb((long)code->cmds[i].addr, code->cmds[i].value);
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| 112 | break;
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[d0c5901] | 113 | #endif
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| 114 | #if defined(ia64)
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| 115 | case CMD_IA64_GETCHAR:
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[43752b6] | 116 | dstval = _getc(&ski_uconsole);
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[d0c5901] | 117 | break;
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[732fd3c] | 118 | #endif
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[ae971b3e] | 119 | #if defined(ppc32)
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[732fd3c] | 120 | case CMD_PPC32_GETCHAR:
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[43752b6] | 121 | dstval = cuda_get_scancode();
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[732fd3c] | 122 | break;
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[bdc5c516] | 123 | #endif
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[162f919] | 124 | default:
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| 125 | break;
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| 126 | }
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[43752b6] | 127 | if (code->cmds[i].dstarg && code->cmds[i].dstarg < 4) {
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| 128 | call->data.args[code->cmds[i].dstarg] = dstval;
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| 129 | }
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[162f919] | 130 | }
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| 131 | }
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| 132 |
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| 133 | static void code_free(irq_code_t *code)
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| 134 | {
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| 135 | if (code) {
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| 136 | free(code->cmds);
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| 137 | free(code);
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| 138 | }
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| 139 | }
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| 140 |
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| 141 | static irq_code_t * code_from_uspace(irq_code_t *ucode)
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| 142 | {
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| 143 | irq_code_t *code;
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| 144 | irq_cmd_t *ucmds;
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[e3c762cd] | 145 | int rc;
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[162f919] | 146 |
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| 147 | code = malloc(sizeof(*code), 0);
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[e3c762cd] | 148 | rc = copy_from_uspace(code, ucode, sizeof(*code));
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| 149 | if (rc != 0) {
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| 150 | free(code);
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| 151 | return NULL;
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| 152 | }
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[162f919] | 153 |
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| 154 | if (code->cmdcount > IRQ_MAX_PROG_SIZE) {
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| 155 | free(code);
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| 156 | return NULL;
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| 157 | }
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| 158 | ucmds = code->cmds;
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| 159 | code->cmds = malloc(sizeof(code->cmds[0]) * (code->cmdcount), 0);
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[e3c762cd] | 160 | rc = copy_from_uspace(code->cmds, ucmds, sizeof(code->cmds[0]) * (code->cmdcount));
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| 161 | if (rc != 0) {
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| 162 | free(code->cmds);
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| 163 | free(code);
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| 164 | return NULL;
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| 165 | }
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[162f919] | 166 |
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| 167 | return code;
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| 168 | }
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| 169 |
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| 170 | /** Unregister task from irq */
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| 171 | void ipc_irq_unregister(answerbox_t *box, int irq)
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| 172 | {
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| 173 | ipl_t ipl;
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[874621f] | 174 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL;
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[162f919] | 175 |
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| 176 | ipl = interrupts_disable();
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[874621f] | 177 | spinlock_lock(&irq_conns[mq].lock);
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| 178 | if (irq_conns[mq].box == box) {
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| 179 | irq_conns[mq].box = NULL;
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| 180 | code_free(irq_conns[mq].code);
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| 181 | irq_conns[mq].code = NULL;
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[162f919] | 182 | }
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| 183 |
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[874621f] | 184 | spinlock_unlock(&irq_conns[mq].lock);
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[162f919] | 185 | interrupts_restore(ipl);
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| 186 | }
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| 187 |
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| 188 | /** Register an answerbox as a receiving end of interrupts notifications */
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| 189 | int ipc_irq_register(answerbox_t *box, int irq, irq_code_t *ucode)
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| 190 | {
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| 191 | ipl_t ipl;
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| 192 | irq_code_t *code;
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[874621f] | 193 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL;
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[162f919] | 194 |
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| 195 | ASSERT(irq_conns);
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| 196 |
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| 197 | if (ucode) {
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| 198 | code = code_from_uspace(ucode);
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| 199 | if (!code)
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| 200 | return EBADMEM;
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| 201 | } else
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| 202 | code = NULL;
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| 203 |
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| 204 | ipl = interrupts_disable();
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[874621f] | 205 | spinlock_lock(&irq_conns[mq].lock);
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[162f919] | 206 |
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[874621f] | 207 | if (irq_conns[mq].box) {
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| 208 | spinlock_unlock(&irq_conns[mq].lock);
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[162f919] | 209 | interrupts_restore(ipl);
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| 210 | code_free(code);
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| 211 | return EEXISTS;
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| 212 | }
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[874621f] | 213 | irq_conns[mq].box = box;
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| 214 | irq_conns[mq].code = code;
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| 215 | atomic_set(&irq_conns[mq].counter, 0);
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| 216 | spinlock_unlock(&irq_conns[mq].lock);
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[162f919] | 217 | interrupts_restore(ipl);
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| 218 |
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| 219 | return 0;
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| 220 | }
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| 221 |
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[874621f] | 222 | /** Add call to proper answerbox queue
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| 223 | *
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| 224 | * Assume irq_conns[mq].lock is locked */
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| 225 | static void send_call(int mq, call_t *call)
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| 226 | {
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| 227 | spinlock_lock(&irq_conns[mq].box->irq_lock);
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| 228 | list_append(&call->link, &irq_conns[mq].box->irq_notifs);
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| 229 | spinlock_unlock(&irq_conns[mq].box->irq_lock);
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| 230 |
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| 231 | waitq_wakeup(&irq_conns[mq].box->wq, 0);
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| 232 | }
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| 233 |
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| 234 | /** Send notification message
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| 235 | *
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| 236 | */
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[7f1c620] | 237 | void ipc_irq_send_msg(int irq, unative_t a1, unative_t a2, unative_t a3)
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[874621f] | 238 | {
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| 239 | call_t *call;
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| 240 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL;
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| 241 |
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| 242 | spinlock_lock(&irq_conns[mq].lock);
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| 243 |
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| 244 | if (irq_conns[mq].box) {
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| 245 | call = ipc_call_alloc(FRAME_ATOMIC);
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| 246 | if (!call) {
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| 247 | spinlock_unlock(&irq_conns[mq].lock);
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| 248 | return;
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| 249 | }
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| 250 | call->flags |= IPC_CALL_NOTIF;
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[43752b6] | 251 | IPC_SET_METHOD(call->data, irq);
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| 252 | IPC_SET_ARG1(call->data, a1);
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[874621f] | 253 | IPC_SET_ARG2(call->data, a2);
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| 254 | IPC_SET_ARG3(call->data, a3);
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[43752b6] | 255 | /* Put a counter to the message */
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| 256 | call->private = atomic_preinc(&irq_conns[mq].counter);
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[874621f] | 257 |
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| 258 | send_call(mq, call);
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| 259 | }
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| 260 | spinlock_unlock(&irq_conns[mq].lock);
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| 261 | }
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| 262 |
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[f3a3f0d7] | 263 | /** Notify task that an irq had occurred.
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[162f919] | 264 | *
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| 265 | * We expect interrupts to be disabled
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| 266 | */
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| 267 | void ipc_irq_send_notif(int irq)
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| 268 | {
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| 269 | call_t *call;
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[874621f] | 270 | int mq = irq + IPC_IRQ_RESERVED_VIRTUAL;
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[162f919] | 271 |
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| 272 | ASSERT(irq_conns);
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[874621f] | 273 | spinlock_lock(&irq_conns[mq].lock);
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[162f919] | 274 |
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[874621f] | 275 | if (irq_conns[mq].box) {
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[162f919] | 276 | call = ipc_call_alloc(FRAME_ATOMIC);
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[d8f7362] | 277 | if (!call) {
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[874621f] | 278 | spinlock_unlock(&irq_conns[mq].lock);
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[d8f7362] | 279 | return;
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| 280 | }
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[162f919] | 281 | call->flags |= IPC_CALL_NOTIF;
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[43752b6] | 282 | /* Put a counter to the message */
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| 283 | call->private = atomic_preinc(&irq_conns[mq].counter);
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| 284 | /* Set up args */
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| 285 | IPC_SET_METHOD(call->data, irq);
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[162f919] | 286 |
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| 287 | /* Execute code to handle irq */
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[874621f] | 288 | code_execute(call, irq_conns[mq].code);
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| 289 |
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| 290 | send_call(mq, call);
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[162f919] | 291 | }
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| 292 |
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[874621f] | 293 | spinlock_unlock(&irq_conns[mq].lock);
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[162f919] | 294 | }
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| 295 |
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| 296 |
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[874621f] | 297 | /** Initialize table of interrupt handlers
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| 298 | *
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| 299 | * @param irqcount Count of required hardware IRQs to be supported
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| 300 | */
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[162f919] | 301 | void ipc_irq_make_table(int irqcount)
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| 302 | {
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| 303 | int i;
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| 304 |
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[874621f] | 305 | irqcount += IPC_IRQ_RESERVED_VIRTUAL;
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| 306 |
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[162f919] | 307 | irq_conns_size = irqcount;
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| 308 | irq_conns = malloc(irqcount * (sizeof(*irq_conns)), 0);
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| 309 | for (i=0; i < irqcount; i++) {
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| 310 | spinlock_initialize(&irq_conns[i].lock, "irq_ipc_lock");
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| 311 | irq_conns[i].box = NULL;
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| 312 | irq_conns[i].code = NULL;
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| 313 | }
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| 314 | }
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| 315 |
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| 316 | /** Disconnect all irq's notifications
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| 317 | *
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[cc73a8a1] | 318 | * @todo It may be better to do some linked list, so that
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[162f919] | 319 | * we wouldn't need to go through whole array every cleanup
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| 320 | */
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| 321 | void ipc_irq_cleanup(answerbox_t *box)
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| 322 | {
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| 323 | int i;
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| 324 | ipl_t ipl;
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| 325 |
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| 326 | for (i=0; i < irq_conns_size; i++) {
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| 327 | ipl = interrupts_disable();
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| 328 | spinlock_lock(&irq_conns[i].lock);
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| 329 | if (irq_conns[i].box == box)
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| 330 | irq_conns[i].box = NULL;
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| 331 | spinlock_unlock(&irq_conns[i].lock);
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| 332 | interrupts_restore(ipl);
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| 333 | }
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| 334 | }
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[b45c443] | 335 |
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[cc73a8a1] | 336 | /** @}
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[b45c443] | 337 | */
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