source: mainline/kernel/genarch/src/mm/page_pt.c@ c72dc15

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since c72dc15 was c72dc15, checked in by Jakub Jermar <jakub@…>, 14 years ago

When unmapping pages, do not cleanup the first level page tables
in the subtree which corresponds to the kernel non-identity mapping.

  • Property mode set to 100644
File size: 8.3 KB
Line 
1/*
2 * Copyright (c) 2006 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup genarchmm
30 * @{
31 */
32
33/**
34 * @file
35 * @brief Virtual Address Translation for hierarchical 4-level page tables.
36 */
37
38#include <genarch/mm/page_pt.h>
39#include <mm/page.h>
40#include <mm/frame.h>
41#include <mm/km.h>
42#include <mm/as.h>
43#include <arch/mm/page.h>
44#include <arch/mm/as.h>
45#include <typedefs.h>
46#include <arch/asm.h>
47#include <memstr.h>
48
49static void pt_mapping_insert(as_t *, uintptr_t, uintptr_t, unsigned int);
50static void pt_mapping_remove(as_t *, uintptr_t);
51static pte_t *pt_mapping_find(as_t *, uintptr_t, bool);
52
53page_mapping_operations_t pt_mapping_operations = {
54 .mapping_insert = pt_mapping_insert,
55 .mapping_remove = pt_mapping_remove,
56 .mapping_find = pt_mapping_find
57};
58
59/** Map page to frame using hierarchical page tables.
60 *
61 * Map virtual address page to physical address frame
62 * using flags.
63 *
64 * @param as Address space to wich page belongs.
65 * @param page Virtual address of the page to be mapped.
66 * @param frame Physical address of memory frame to which the mapping is done.
67 * @param flags Flags to be used for mapping.
68 *
69 */
70void pt_mapping_insert(as_t *as, uintptr_t page, uintptr_t frame,
71 unsigned int flags)
72{
73 pte_t *ptl0 = (pte_t *) PA2KA((uintptr_t) as->genarch.page_table);
74
75 ASSERT(page_table_locked(as));
76
77 if (GET_PTL1_FLAGS(ptl0, PTL0_INDEX(page)) & PAGE_NOT_PRESENT) {
78 pte_t *newpt = (pte_t *) frame_alloc(PTL1_SIZE,
79 FRAME_LOWMEM | FRAME_KA);
80 memsetb(newpt, FRAME_SIZE << PTL1_SIZE, 0);
81 SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page), KA2PA(newpt));
82 SET_PTL1_FLAGS(ptl0, PTL0_INDEX(page),
83 PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
84 PAGE_WRITE);
85 }
86
87 pte_t *ptl1 = (pte_t *) PA2KA(GET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page)));
88
89 if (GET_PTL2_FLAGS(ptl1, PTL1_INDEX(page)) & PAGE_NOT_PRESENT) {
90 pte_t *newpt = (pte_t *) frame_alloc(PTL2_SIZE,
91 FRAME_LOWMEM | FRAME_KA);
92 memsetb(newpt, FRAME_SIZE << PTL2_SIZE, 0);
93 SET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page), KA2PA(newpt));
94 SET_PTL2_FLAGS(ptl1, PTL1_INDEX(page),
95 PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
96 PAGE_WRITE);
97 }
98
99 pte_t *ptl2 = (pte_t *) PA2KA(GET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page)));
100
101 if (GET_PTL3_FLAGS(ptl2, PTL2_INDEX(page)) & PAGE_NOT_PRESENT) {
102 pte_t *newpt = (pte_t *) frame_alloc(PTL3_SIZE,
103 FRAME_LOWMEM | FRAME_KA);
104 memsetb(newpt, FRAME_SIZE << PTL3_SIZE, 0);
105 SET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page), KA2PA(newpt));
106 SET_PTL3_FLAGS(ptl2, PTL2_INDEX(page),
107 PAGE_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
108 PAGE_WRITE);
109 }
110
111 pte_t *ptl3 = (pte_t *) PA2KA(GET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page)));
112
113 SET_FRAME_ADDRESS(ptl3, PTL3_INDEX(page), frame);
114 SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags);
115}
116
117/** Remove mapping of page from hierarchical page tables.
118 *
119 * Remove any mapping of page within address space as.
120 * TLB shootdown should follow in order to make effects of
121 * this call visible.
122 *
123 * Empty page tables except PTL0 are freed.
124 *
125 * @param as Address space to wich page belongs.
126 * @param page Virtual address of the page to be demapped.
127 *
128 */
129void pt_mapping_remove(as_t *as, uintptr_t page)
130{
131 ASSERT(page_table_locked(as));
132
133 /*
134 * First, remove the mapping, if it exists.
135 *
136 */
137
138 pte_t *ptl0 = (pte_t *) PA2KA((uintptr_t) as->genarch.page_table);
139 if (GET_PTL1_FLAGS(ptl0, PTL0_INDEX(page)) & PAGE_NOT_PRESENT)
140 return;
141
142 pte_t *ptl1 = (pte_t *) PA2KA(GET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page)));
143 if (GET_PTL2_FLAGS(ptl1, PTL1_INDEX(page)) & PAGE_NOT_PRESENT)
144 return;
145
146 pte_t *ptl2 = (pte_t *) PA2KA(GET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page)));
147 if (GET_PTL3_FLAGS(ptl2, PTL2_INDEX(page)) & PAGE_NOT_PRESENT)
148 return;
149
150 pte_t *ptl3 = (pte_t *) PA2KA(GET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page)));
151
152 /* Destroy the mapping. Setting to PAGE_NOT_PRESENT is not sufficient. */
153 memsetb(&ptl3[PTL3_INDEX(page)], sizeof(pte_t), 0);
154
155 /*
156 * Second, free all empty tables along the way from PTL3 down to PTL0
157 * except those needed for sharing the kernel non-identity mappings.
158 */
159
160 /* Check PTL3 */
161 bool empty = true;
162
163 unsigned int i;
164 for (i = 0; i < PTL3_ENTRIES; i++) {
165 if (PTE_VALID(&ptl3[i])) {
166 empty = false;
167 break;
168 }
169 }
170
171 if (empty) {
172 /*
173 * PTL3 is empty.
174 * Release the frame and remove PTL3 pointer from the parent
175 * table.
176 */
177#if (PTL2_ENTRIES != 0)
178 memsetb(&ptl2[PTL2_INDEX(page)], sizeof(pte_t), 0);
179#elif (PTL1_ENTRIES != 0)
180 memsetb(&ptl1[PTL1_INDEX(page)], sizeof(pte_t), 0);
181#else
182 if (km_is_non_identity(page))
183 return;
184
185 memsetb(&ptl0[PTL0_INDEX(page)], sizeof(pte_t), 0);
186#endif
187 frame_free(KA2PA((uintptr_t) ptl3));
188 } else {
189 /*
190 * PTL3 is not empty.
191 * Therefore, there must be a path from PTL0 to PTL3 and
192 * thus nothing to free in higher levels.
193 *
194 */
195 return;
196 }
197
198 /* Check PTL2, empty is still true */
199#if (PTL2_ENTRIES != 0)
200 for (i = 0; i < PTL2_ENTRIES; i++) {
201 if (PTE_VALID(&ptl2[i])) {
202 empty = false;
203 break;
204 }
205 }
206
207 if (empty) {
208 /*
209 * PTL2 is empty.
210 * Release the frame and remove PTL2 pointer from the parent
211 * table.
212 */
213#if (PTL1_ENTRIES != 0)
214 memsetb(&ptl1[PTL1_INDEX(page)], sizeof(pte_t), 0);
215#else
216 if (km_is_non_identity(page))
217 return;
218
219 memsetb(&ptl0[PTL0_INDEX(page)], sizeof(pte_t), 0);
220#endif
221 frame_free(KA2PA((uintptr_t) ptl2));
222 } else {
223 /*
224 * PTL2 is not empty.
225 * Therefore, there must be a path from PTL0 to PTL2 and
226 * thus nothing to free in higher levels.
227 *
228 */
229 return;
230 }
231#endif /* PTL2_ENTRIES != 0 */
232
233 /* check PTL1, empty is still true */
234#if (PTL1_ENTRIES != 0)
235 for (i = 0; i < PTL1_ENTRIES; i++) {
236 if (PTE_VALID(&ptl1[i])) {
237 empty = false;
238 break;
239 }
240 }
241
242 if (empty) {
243 /*
244 * PTL1 is empty.
245 * Release the frame and remove PTL1 pointer from the parent
246 * table.
247 */
248 if (km_is_non_identity(page))
249 return;
250
251 memsetb(&ptl0[PTL0_INDEX(page)], sizeof(pte_t), 0);
252 frame_free(KA2PA((uintptr_t) ptl1));
253 }
254#endif /* PTL1_ENTRIES != 0 */
255}
256
257/** Find mapping for virtual page in hierarchical page tables.
258 *
259 * @param as Address space to which page belongs.
260 * @param page Virtual page.
261 * @param nolock True if the page tables need not be locked.
262 *
263 * @return NULL if there is no such mapping; entry from PTL3 describing
264 * the mapping otherwise.
265 *
266 */
267pte_t *pt_mapping_find(as_t *as, uintptr_t page, bool nolock)
268{
269 ASSERT(nolock || page_table_locked(as));
270
271 pte_t *ptl0 = (pte_t *) PA2KA((uintptr_t) as->genarch.page_table);
272 if (GET_PTL1_FLAGS(ptl0, PTL0_INDEX(page)) & PAGE_NOT_PRESENT)
273 return NULL;
274
275 pte_t *ptl1 = (pte_t *) PA2KA(GET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page)));
276 if (GET_PTL2_FLAGS(ptl1, PTL1_INDEX(page)) & PAGE_NOT_PRESENT)
277 return NULL;
278
279 pte_t *ptl2 = (pte_t *) PA2KA(GET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page)));
280 if (GET_PTL3_FLAGS(ptl2, PTL2_INDEX(page)) & PAGE_NOT_PRESENT)
281 return NULL;
282
283 pte_t *ptl3 = (pte_t *) PA2KA(GET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page)));
284
285 return &ptl3[PTL3_INDEX(page)];
286}
287
288/** @}
289 */
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