source: mainline/kernel/genarch/src/mm/page_pt.c@ 609a417

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 609a417 was 609a417, checked in by Jakub Jermar <jakub@…>, 13 years ago

Add write memory barriers to pt_mapping_insert() so that setting a new
page table level is separated from marking it present in the previous
level.

This is to make sure that a concurrent hardware page table walk or
pt_page_find() will see the new level only after it is fully
initialized.

  • Property mode set to 100644
File size: 10.4 KB
Line 
1/*
2 * Copyright (c) 2006 Jakub Jermar
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup genarchmm
30 * @{
31 */
32
33/**
34 * @file
35 * @brief Virtual Address Translation for hierarchical 4-level page tables.
36 */
37
38#include <genarch/mm/page_pt.h>
39#include <mm/page.h>
40#include <mm/frame.h>
41#include <mm/km.h>
42#include <mm/as.h>
43#include <arch/mm/page.h>
44#include <arch/mm/as.h>
45#include <arch/barrier.h>
46#include <typedefs.h>
47#include <arch/asm.h>
48#include <memstr.h>
49#include <align.h>
50#include <macros.h>
51#include <bitops.h>
52
53static void pt_mapping_insert(as_t *, uintptr_t, uintptr_t, unsigned int);
54static void pt_mapping_remove(as_t *, uintptr_t);
55static pte_t *pt_mapping_find(as_t *, uintptr_t, bool);
56static void pt_mapping_make_global(uintptr_t, size_t);
57
58page_mapping_operations_t pt_mapping_operations = {
59 .mapping_insert = pt_mapping_insert,
60 .mapping_remove = pt_mapping_remove,
61 .mapping_find = pt_mapping_find,
62 .mapping_make_global = pt_mapping_make_global
63};
64
65/** Map page to frame using hierarchical page tables.
66 *
67 * Map virtual address page to physical address frame
68 * using flags.
69 *
70 * @param as Address space to wich page belongs.
71 * @param page Virtual address of the page to be mapped.
72 * @param frame Physical address of memory frame to which the mapping is done.
73 * @param flags Flags to be used for mapping.
74 *
75 */
76void pt_mapping_insert(as_t *as, uintptr_t page, uintptr_t frame,
77 unsigned int flags)
78{
79 pte_t *ptl0 = (pte_t *) PA2KA((uintptr_t) as->genarch.page_table);
80
81 ASSERT(page_table_locked(as));
82
83 if (GET_PTL1_FLAGS(ptl0, PTL0_INDEX(page)) & PAGE_NOT_PRESENT) {
84 pte_t *newpt = (pte_t *) frame_alloc(PTL1_SIZE,
85 FRAME_LOWMEM | FRAME_KA);
86 memsetb(newpt, FRAME_SIZE << PTL1_SIZE, 0);
87 SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page), KA2PA(newpt));
88 SET_PTL1_FLAGS(ptl0, PTL0_INDEX(page),
89 PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
90 PAGE_WRITE);
91 write_barrier();
92 SET_PTL1_PRESENT(ptl0, PTL0_INDEX(page));
93 }
94
95 pte_t *ptl1 = (pte_t *) PA2KA(GET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page)));
96
97 if (GET_PTL2_FLAGS(ptl1, PTL1_INDEX(page)) & PAGE_NOT_PRESENT) {
98 pte_t *newpt = (pte_t *) frame_alloc(PTL2_SIZE,
99 FRAME_LOWMEM | FRAME_KA);
100 memsetb(newpt, FRAME_SIZE << PTL2_SIZE, 0);
101 SET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page), KA2PA(newpt));
102 SET_PTL2_FLAGS(ptl1, PTL1_INDEX(page),
103 PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
104 PAGE_WRITE);
105 write_barrier();
106 SET_PTL2_PRESENT(ptl1, PTL1_INDEX(page));
107 }
108
109 pte_t *ptl2 = (pte_t *) PA2KA(GET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page)));
110
111 if (GET_PTL3_FLAGS(ptl2, PTL2_INDEX(page)) & PAGE_NOT_PRESENT) {
112 pte_t *newpt = (pte_t *) frame_alloc(PTL3_SIZE,
113 FRAME_LOWMEM | FRAME_KA);
114 memsetb(newpt, FRAME_SIZE << PTL3_SIZE, 0);
115 SET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page), KA2PA(newpt));
116 SET_PTL3_FLAGS(ptl2, PTL2_INDEX(page),
117 PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |
118 PAGE_WRITE);
119 write_barrier();
120 SET_PTL3_PRESENT(ptl2, PTL2_INDEX(page));
121 }
122
123 pte_t *ptl3 = (pte_t *) PA2KA(GET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page)));
124
125 SET_FRAME_ADDRESS(ptl3, PTL3_INDEX(page), frame);
126 SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags | PAGE_NOT_PRESENT);
127 write_barrier();
128 SET_FRAME_PRESENT(ptl3, PTL3_INDEX(page));
129}
130
131/** Remove mapping of page from hierarchical page tables.
132 *
133 * Remove any mapping of page within address space as.
134 * TLB shootdown should follow in order to make effects of
135 * this call visible.
136 *
137 * Empty page tables except PTL0 are freed.
138 *
139 * @param as Address space to wich page belongs.
140 * @param page Virtual address of the page to be demapped.
141 *
142 */
143void pt_mapping_remove(as_t *as, uintptr_t page)
144{
145 ASSERT(page_table_locked(as));
146
147 /*
148 * First, remove the mapping, if it exists.
149 */
150
151 pte_t *ptl0 = (pte_t *) PA2KA((uintptr_t) as->genarch.page_table);
152 if (GET_PTL1_FLAGS(ptl0, PTL0_INDEX(page)) & PAGE_NOT_PRESENT)
153 return;
154
155 pte_t *ptl1 = (pte_t *) PA2KA(GET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page)));
156 if (GET_PTL2_FLAGS(ptl1, PTL1_INDEX(page)) & PAGE_NOT_PRESENT)
157 return;
158
159 pte_t *ptl2 = (pte_t *) PA2KA(GET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page)));
160 if (GET_PTL3_FLAGS(ptl2, PTL2_INDEX(page)) & PAGE_NOT_PRESENT)
161 return;
162
163 pte_t *ptl3 = (pte_t *) PA2KA(GET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page)));
164
165 /*
166 * Destroy the mapping.
167 * Setting to PAGE_NOT_PRESENT is not sufficient.
168 */
169 memsetb(&ptl3[PTL3_INDEX(page)], sizeof(pte_t), 0);
170
171 /*
172 * Second, free all empty tables along the way from PTL3 down to PTL0
173 * except those needed for sharing the kernel non-identity mappings.
174 */
175
176 /* Check PTL3 */
177 bool empty = true;
178
179 unsigned int i;
180 for (i = 0; i < PTL3_ENTRIES; i++) {
181 if (PTE_VALID(&ptl3[i])) {
182 empty = false;
183 break;
184 }
185 }
186
187 if (empty) {
188 /*
189 * PTL3 is empty.
190 * Release the frame and remove PTL3 pointer from the parent
191 * table.
192 */
193#if (PTL2_ENTRIES != 0)
194 memsetb(&ptl2[PTL2_INDEX(page)], sizeof(pte_t), 0);
195#elif (PTL1_ENTRIES != 0)
196 memsetb(&ptl1[PTL1_INDEX(page)], sizeof(pte_t), 0);
197#else
198 if (km_is_non_identity(page))
199 return;
200
201 memsetb(&ptl0[PTL0_INDEX(page)], sizeof(pte_t), 0);
202#endif
203 frame_free(KA2PA((uintptr_t) ptl3));
204 } else {
205 /*
206 * PTL3 is not empty.
207 * Therefore, there must be a path from PTL0 to PTL3 and
208 * thus nothing to free in higher levels.
209 *
210 */
211 return;
212 }
213
214 /* Check PTL2, empty is still true */
215#if (PTL2_ENTRIES != 0)
216 for (i = 0; i < PTL2_ENTRIES; i++) {
217 if (PTE_VALID(&ptl2[i])) {
218 empty = false;
219 break;
220 }
221 }
222
223 if (empty) {
224 /*
225 * PTL2 is empty.
226 * Release the frame and remove PTL2 pointer from the parent
227 * table.
228 */
229#if (PTL1_ENTRIES != 0)
230 memsetb(&ptl1[PTL1_INDEX(page)], sizeof(pte_t), 0);
231#else
232 if (km_is_non_identity(page))
233 return;
234
235 memsetb(&ptl0[PTL0_INDEX(page)], sizeof(pte_t), 0);
236#endif
237 frame_free(KA2PA((uintptr_t) ptl2));
238 } else {
239 /*
240 * PTL2 is not empty.
241 * Therefore, there must be a path from PTL0 to PTL2 and
242 * thus nothing to free in higher levels.
243 *
244 */
245 return;
246 }
247#endif /* PTL2_ENTRIES != 0 */
248
249 /* check PTL1, empty is still true */
250#if (PTL1_ENTRIES != 0)
251 for (i = 0; i < PTL1_ENTRIES; i++) {
252 if (PTE_VALID(&ptl1[i])) {
253 empty = false;
254 break;
255 }
256 }
257
258 if (empty) {
259 /*
260 * PTL1 is empty.
261 * Release the frame and remove PTL1 pointer from the parent
262 * table.
263 */
264 if (km_is_non_identity(page))
265 return;
266
267 memsetb(&ptl0[PTL0_INDEX(page)], sizeof(pte_t), 0);
268 frame_free(KA2PA((uintptr_t) ptl1));
269 }
270#endif /* PTL1_ENTRIES != 0 */
271}
272
273/** Find mapping for virtual page in hierarchical page tables.
274 *
275 * @param as Address space to which page belongs.
276 * @param page Virtual page.
277 * @param nolock True if the page tables need not be locked.
278 *
279 * @return NULL if there is no such mapping; entry from PTL3 describing
280 * the mapping otherwise.
281 *
282 */
283pte_t *pt_mapping_find(as_t *as, uintptr_t page, bool nolock)
284{
285 ASSERT(nolock || page_table_locked(as));
286
287 pte_t *ptl0 = (pte_t *) PA2KA((uintptr_t) as->genarch.page_table);
288 if (GET_PTL1_FLAGS(ptl0, PTL0_INDEX(page)) & PAGE_NOT_PRESENT)
289 return NULL;
290
291 pte_t *ptl1 = (pte_t *) PA2KA(GET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page)));
292 if (GET_PTL2_FLAGS(ptl1, PTL1_INDEX(page)) & PAGE_NOT_PRESENT)
293 return NULL;
294
295 pte_t *ptl2 = (pte_t *) PA2KA(GET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page)));
296 if (GET_PTL3_FLAGS(ptl2, PTL2_INDEX(page)) & PAGE_NOT_PRESENT)
297 return NULL;
298
299 pte_t *ptl3 = (pte_t *) PA2KA(GET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page)));
300
301 return &ptl3[PTL3_INDEX(page)];
302}
303
304/** Return the size of the region mapped by a single PTL0 entry.
305 *
306 * @return Size of the region mapped by a single PTL0 entry.
307 */
308static uintptr_t ptl0_step_get(void)
309{
310 size_t va_bits;
311
312 va_bits = fnzb(PTL0_ENTRIES) + fnzb(PTL1_ENTRIES) + fnzb(PTL2_ENTRIES) +
313 fnzb(PTL3_ENTRIES) + PAGE_WIDTH;
314
315 return 1UL << (va_bits - fnzb(PTL0_ENTRIES));
316}
317
318/** Make the mappings in the given range global accross all address spaces.
319 *
320 * All PTL0 entries in the given range will be mapped to a next level page
321 * table. The next level page table will be allocated and cleared.
322 *
323 * pt_mapping_remove() will never deallocate these page tables even when there
324 * are no PTEs in them.
325 *
326 * @param as Address space.
327 * @param base Base address corresponding to the first PTL0 entry that will be
328 * altered by this function.
329 * @param size Size in bytes defining the range of PTL0 entries that will be
330 * altered by this function.
331 */
332void pt_mapping_make_global(uintptr_t base, size_t size)
333{
334 uintptr_t ptl0 = PA2KA((uintptr_t) AS_KERNEL->genarch.page_table);
335 uintptr_t ptl0_step = ptl0_step_get();
336 size_t order;
337 uintptr_t addr;
338
339#if (PTL1_ENTRIES != 0)
340 order = PTL1_SIZE;
341#elif (PTL2_ENTRIES != 0)
342 order = PTL2_SIZE;
343#else
344 order = PTL3_SIZE;
345#endif
346
347 ASSERT(size > 0);
348
349 for (addr = ALIGN_DOWN(base, ptl0_step); addr - 1 < base + size - 1;
350 addr += ptl0_step) {
351 uintptr_t l1;
352
353 l1 = (uintptr_t) frame_alloc(order, FRAME_KA | FRAME_LOWMEM);
354 memsetb((void *) l1, FRAME_SIZE << order, 0);
355 SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(addr), KA2PA(l1));
356 SET_PTL1_FLAGS(ptl0, PTL0_INDEX(addr),
357 PAGE_PRESENT | PAGE_USER | PAGE_CACHEABLE |
358 PAGE_EXEC | PAGE_WRITE | PAGE_READ);
359 }
360}
361
362/** @}
363 */
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