source: mainline/kernel/genarch/src/drivers/via-cuda/cuda.c@ e47ed05

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since e47ed05 was d9c11fc3, checked in by Martin Decky <martin@…>, 15 years ago

remove unused variable
  • Property mode set to 100644
File size: 8.7 KB
Line 
1/*
2 * Copyright (c) 2006 Martin Decky
3 * Copyright (c) 2009 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup genarch
31 * @{
32 */
33/** @file
34 */
35
36#include <genarch/drivers/via-cuda/cuda.h>
37#include <console/chardev.h>
38#include <ddi/irq.h>
39#include <arch/asm.h>
40#include <mm/slab.h>
41#include <ddi/device.h>
42#include <synch/spinlock.h>
43#include <memstr.h>
44
45static irq_ownership_t cuda_claim(irq_t *irq);
46static void cuda_irq_handler(irq_t *irq);
47
48static void cuda_irq_listen(irq_t *irq);
49static void cuda_irq_receive(irq_t *irq);
50static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len);
51static void cuda_irq_send_start(irq_t *irq);
52static void cuda_irq_send(irq_t *irq);
53
54static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *buf, size_t len);
55static void cuda_send_start(cuda_instance_t *instance);
56static void cuda_autopoll_set(cuda_instance_t *instance, bool enable);
57
58/** B register fields */
59enum {
60 TREQ = 0x08,
61 TACK = 0x10,
62 TIP = 0x20
63};
64
65/** IER register fields */
66enum {
67 IER_CLR = 0x00,
68 IER_SET = 0x80,
69
70 SR_INT = 0x04,
71 ALL_INT = 0x7f
72};
73
74/** ACR register fields */
75enum {
76 SR_OUT = 0x10
77};
78
79/** Packet types */
80enum {
81 PT_ADB = 0x00,
82 PT_CUDA = 0x01
83};
84
85/** CUDA packet types */
86enum {
87 CPT_AUTOPOLL = 0x01
88};
89
90cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg)
91{
92 cuda_instance_t *instance
93 = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC);
94 if (instance) {
95 instance->cuda = dev;
96 instance->kbrdin = NULL;
97 instance->xstate = cx_listen;
98 instance->bidx = 0;
99 instance->snd_bytes = 0;
100
101 spinlock_initialize(&instance->dev_lock, "cuda.instance.dev_lock");
102
103 /* Disable all interrupts from CUDA. */
104 pio_write_8(&dev->ier, IER_CLR | ALL_INT);
105
106 irq_initialize(&instance->irq);
107 instance->irq.devno = device_assign_devno();
108 instance->irq.inr = inr;
109 instance->irq.claim = cuda_claim;
110 instance->irq.handler = cuda_irq_handler;
111 instance->irq.instance = instance;
112 instance->irq.cir = cir;
113 instance->irq.cir_arg = cir_arg;
114 instance->irq.preack = true;
115 }
116
117 return instance;
118}
119
120#include <print.h>
121void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
122{
123 cuda_t *dev = instance->cuda;
124
125 ASSERT(instance);
126 ASSERT(kbrdin);
127
128 instance->kbrdin = kbrdin;
129 irq_register(&instance->irq);
130
131 /* Enable SR interrupt. */
132 pio_write_8(&dev->ier, TIP | TREQ);
133 pio_write_8(&dev->ier, IER_SET | SR_INT);
134
135 /* Enable ADB autopolling. */
136 cuda_autopoll_set(instance, true);
137}
138
139static irq_ownership_t cuda_claim(irq_t *irq)
140{
141 cuda_instance_t *instance = irq->instance;
142 cuda_t *dev = instance->cuda;
143 uint8_t ifr;
144
145 spinlock_lock(&instance->dev_lock);
146 ifr = pio_read_8(&dev->ifr);
147 spinlock_unlock(&instance->dev_lock);
148
149 if ((ifr & SR_INT) == 0)
150 return IRQ_DECLINE;
151
152 return IRQ_ACCEPT;
153}
154
155static void cuda_irq_handler(irq_t *irq)
156{
157 cuda_instance_t *instance = irq->instance;
158 uint8_t rbuf[CUDA_RCV_BUF_SIZE];
159 size_t len;
160 bool handle;
161
162 handle = false;
163 len = 0;
164
165 spinlock_lock(&instance->dev_lock);
166
167 /* Lower IFR.SR_INT so that CUDA can generate next int by raising it. */
168 pio_write_8(&instance->cuda->ifr, SR_INT);
169
170 switch (instance->xstate) {
171 case cx_listen: cuda_irq_listen(irq); break;
172 case cx_receive: cuda_irq_receive(irq); break;
173 case cx_rcv_end: cuda_irq_rcv_end(irq, rbuf, &len);
174 handle = true; break;
175 case cx_send_start: cuda_irq_send_start(irq); break;
176 case cx_send: cuda_irq_send(irq); break;
177 }
178
179 spinlock_unlock(&instance->dev_lock);
180
181 /* Handle an incoming packet. */
182 if (handle)
183 cuda_packet_handle(instance, rbuf, len);
184}
185
186/** Interrupt in listen state.
187 *
188 * Start packet reception.
189 */
190static void cuda_irq_listen(irq_t *irq)
191{
192 cuda_instance_t *instance = irq->instance;
193 cuda_t *dev = instance->cuda;
194 uint8_t b;
195
196 b = pio_read_8(&dev->b);
197
198 if ((b & TREQ) != 0) {
199 printf("cuda_irq_listen: no TREQ?!\n");
200 return;
201 }
202
203 pio_read_8(&dev->sr);
204 pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
205 instance->xstate = cx_receive;
206}
207
208/** Interrupt in receive state.
209 *
210 * Receive next byte of packet.
211 */
212static void cuda_irq_receive(irq_t *irq)
213{
214 cuda_instance_t *instance = irq->instance;
215 cuda_t *dev = instance->cuda;
216 uint8_t b, data;
217
218 data = pio_read_8(&dev->sr);
219 if (instance->bidx < CUDA_RCV_BUF_SIZE)
220 instance->rcv_buf[instance->bidx++] = data;
221
222 b = pio_read_8(&dev->b);
223
224 if ((b & TREQ) == 0) {
225 pio_write_8(&dev->b, b ^ TACK);
226 } else {
227 pio_write_8(&dev->b, b | TACK | TIP);
228 instance->xstate = cx_rcv_end;
229 }
230}
231
232/** Interrupt in rcv_end state.
233 *
234 * Terminate packet reception. Either go back to listen state or start
235 * receiving another packet if CUDA has one for us.
236 */
237static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len)
238{
239 cuda_instance_t *instance = irq->instance;
240 cuda_t *dev = instance->cuda;
241 uint8_t b;
242
243 b = pio_read_8(&dev->b);
244 pio_read_8(&dev->sr);
245
246 if ((b & TREQ) == 0) {
247 instance->xstate = cx_receive;
248 pio_write_8(&dev->b, b & ~TIP);
249 } else {
250 instance->xstate = cx_listen;
251 cuda_send_start(instance);
252 }
253
254 memcpy(buf, instance->rcv_buf, instance->bidx);
255 *len = instance->bidx;
256 instance->bidx = 0;
257}
258
259/** Interrupt in send_start state.
260 *
261 * Process result of sending first byte (and send second on success).
262 */
263static void cuda_irq_send_start(irq_t *irq)
264{
265 cuda_instance_t *instance = irq->instance;
266 cuda_t *dev = instance->cuda;
267 uint8_t b;
268
269 b = pio_read_8(&dev->b);
270
271 if ((b & TREQ) == 0) {
272 /* Collision */
273 pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
274 pio_read_8(&dev->sr);
275 pio_write_8(&dev->b, pio_read_8(&dev->b) | TIP | TACK);
276 instance->xstate = cx_listen;
277 return;
278 }
279
280 pio_write_8(&dev->sr, instance->snd_buf[1]);
281 pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
282 instance->bidx = 2;
283
284 instance->xstate = cx_send;
285}
286
287/** Interrupt in send state.
288 *
289 * Send next byte or terminate transmission.
290 */
291static void cuda_irq_send(irq_t *irq)
292{
293 cuda_instance_t *instance = irq->instance;
294 cuda_t *dev = instance->cuda;
295
296 if (instance->bidx < instance->snd_bytes) {
297 /* Send next byte. */
298 pio_write_8(&dev->sr, instance->snd_buf[instance->bidx++]);
299 pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
300 return;
301 }
302
303 /* End transfer. */
304 instance->snd_bytes = 0;
305 instance->bidx = 0;
306
307 pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
308 pio_read_8(&dev->sr);
309 pio_write_8(&dev->b, pio_read_8(&dev->b) | TACK | TIP);
310
311 instance->xstate = cx_listen;
312 /* TODO: Match reply with request. */
313}
314
315static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *data, size_t len)
316{
317 if (data[0] != 0x00 || data[1] != 0x40 || (data[2] != 0x2c
318 && data[2] != 0x8c))
319 return;
320
321 /* The packet contains one or two scancodes. */
322 if (data[3] != 0xff)
323 indev_push_character(instance->kbrdin, data[3]);
324 if (data[4] != 0xff)
325 indev_push_character(instance->kbrdin, data[4]);
326}
327
328static void cuda_autopoll_set(cuda_instance_t *instance, bool enable)
329{
330 instance->snd_buf[0] = PT_CUDA;
331 instance->snd_buf[1] = CPT_AUTOPOLL;
332 instance->snd_buf[2] = enable ? 0x01 : 0x00;
333 instance->snd_bytes = 3;
334 instance->bidx = 0;
335
336 cuda_send_start(instance);
337}
338
339static void cuda_send_start(cuda_instance_t *instance)
340{
341 cuda_t *dev = instance->cuda;
342
343 ASSERT(instance->xstate == cx_listen);
344
345 if (instance->snd_bytes == 0)
346 return;
347
348 /* Check for incoming data. */
349 if ((pio_read_8(&dev->b) & TREQ) == 0)
350 return;
351
352 pio_write_8(&dev->acr, pio_read_8(&dev->acr) | SR_OUT);
353 pio_write_8(&dev->sr, instance->snd_buf[0]);
354 pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
355
356 instance->xstate = cx_send_start;
357}
358
359
360/** @}
361 */
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