source: mainline/kernel/genarch/src/drivers/via-cuda/cuda.c@ 6404aca

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 6404aca was 6404aca, checked in by Jakub Jermar <jakub@…>, 7 years ago

Disambiguate doxygroup genarch*
  • Property mode set to 100644
File size: 8.7 KB
Line 
1/*
2 * Copyright (c) 2006 Martin Decky
3 * Copyright (c) 2009 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup kernel_genarch
31 * @{
32 */
33/** @file
34 */
35
36#include <assert.h>
37#include <genarch/drivers/via-cuda/cuda.h>
38#include <console/chardev.h>
39#include <ddi/irq.h>
40#include <arch/asm.h>
41#include <mm/slab.h>
42#include <synch/spinlock.h>
43#include <mem.h>
44
45static irq_ownership_t cuda_claim(irq_t *irq);
46static void cuda_irq_handler(irq_t *irq);
47
48static void cuda_irq_listen(irq_t *irq);
49static void cuda_irq_receive(irq_t *irq);
50static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len);
51static void cuda_irq_send_start(irq_t *irq);
52static void cuda_irq_send(irq_t *irq);
53
54static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *buf, size_t len);
55static void cuda_send_start(cuda_instance_t *instance);
56static void cuda_autopoll_set(cuda_instance_t *instance, bool enable);
57
58/** B register fields */
59enum {
60 TREQ = 0x08,
61 TACK = 0x10,
62 TIP = 0x20
63};
64
65/** IER register fields */
66enum {
67 IER_CLR = 0x00,
68 IER_SET = 0x80,
69
70 SR_INT = 0x04,
71 ALL_INT = 0x7f
72};
73
74/** ACR register fields */
75enum {
76 SR_OUT = 0x10
77};
78
79/** Packet types */
80enum {
81 PT_ADB = 0x00,
82 PT_CUDA = 0x01
83};
84
85/** CUDA packet types */
86enum {
87 CPT_AUTOPOLL = 0x01
88};
89
90cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg)
91{
92 cuda_instance_t *instance =
93 malloc(sizeof(cuda_instance_t));
94 if (instance) {
95 instance->cuda = dev;
96 instance->kbrdin = NULL;
97 instance->xstate = cx_listen;
98 instance->bidx = 0;
99 instance->snd_bytes = 0;
100
101 spinlock_initialize(&instance->dev_lock, "cuda.instance.dev_lock");
102
103 /* Disable all interrupts from CUDA. */
104 pio_write_8(&dev->ier, IER_CLR | ALL_INT);
105
106 irq_initialize(&instance->irq);
107 instance->irq.inr = inr;
108 instance->irq.claim = cuda_claim;
109 instance->irq.handler = cuda_irq_handler;
110 instance->irq.instance = instance;
111 instance->irq.cir = cir;
112 instance->irq.cir_arg = cir_arg;
113 instance->irq.preack = true;
114 }
115
116 return instance;
117}
118
119#include <log.h>
120void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
121{
122 cuda_t *dev = instance->cuda;
123
124 assert(instance);
125 assert(kbrdin);
126
127 instance->kbrdin = kbrdin;
128 irq_register(&instance->irq);
129
130 /* Enable SR interrupt. */
131 pio_write_8(&dev->ier, TIP | TREQ);
132 pio_write_8(&dev->ier, IER_SET | SR_INT);
133
134 /* Enable ADB autopolling. */
135 cuda_autopoll_set(instance, true);
136}
137
138static irq_ownership_t cuda_claim(irq_t *irq)
139{
140 cuda_instance_t *instance = irq->instance;
141 cuda_t *dev = instance->cuda;
142 uint8_t ifr;
143
144 spinlock_lock(&instance->dev_lock);
145 ifr = pio_read_8(&dev->ifr);
146 spinlock_unlock(&instance->dev_lock);
147
148 if ((ifr & SR_INT) == 0)
149 return IRQ_DECLINE;
150
151 return IRQ_ACCEPT;
152}
153
154static void cuda_irq_handler(irq_t *irq)
155{
156 cuda_instance_t *instance = irq->instance;
157 uint8_t rbuf[CUDA_RCV_BUF_SIZE];
158 size_t len;
159 bool handle;
160
161 handle = false;
162 len = 0;
163
164 spinlock_lock(&instance->dev_lock);
165
166 /* Lower IFR.SR_INT so that CUDA can generate next int by raising it. */
167 pio_write_8(&instance->cuda->ifr, SR_INT);
168
169 switch (instance->xstate) {
170 case cx_listen:
171 cuda_irq_listen(irq);
172 break;
173 case cx_receive:
174 cuda_irq_receive(irq);
175 break;
176 case cx_rcv_end:
177 cuda_irq_rcv_end(irq, rbuf, &len);
178 handle = true;
179 break;
180 case cx_send_start:
181 cuda_irq_send_start(irq);
182 break;
183 case cx_send:
184 cuda_irq_send(irq);
185 break;
186 }
187
188 spinlock_unlock(&instance->dev_lock);
189
190 /* Handle an incoming packet. */
191 if (handle)
192 cuda_packet_handle(instance, rbuf, len);
193}
194
195/** Interrupt in listen state.
196 *
197 * Start packet reception.
198 */
199static void cuda_irq_listen(irq_t *irq)
200{
201 cuda_instance_t *instance = irq->instance;
202 cuda_t *dev = instance->cuda;
203 uint8_t b;
204
205 b = pio_read_8(&dev->b);
206
207 if ((b & TREQ) != 0) {
208 log(LF_OTHER, LVL_ERROR, "cuda_irq_listen: no TREQ?!");
209 return;
210 }
211
212 pio_read_8(&dev->sr);
213 pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
214 instance->xstate = cx_receive;
215}
216
217/** Interrupt in receive state.
218 *
219 * Receive next byte of packet.
220 */
221static void cuda_irq_receive(irq_t *irq)
222{
223 cuda_instance_t *instance = irq->instance;
224 cuda_t *dev = instance->cuda;
225 uint8_t b, data;
226
227 data = pio_read_8(&dev->sr);
228 if (instance->bidx < CUDA_RCV_BUF_SIZE)
229 instance->rcv_buf[instance->bidx++] = data;
230
231 b = pio_read_8(&dev->b);
232
233 if ((b & TREQ) == 0) {
234 pio_write_8(&dev->b, b ^ TACK);
235 } else {
236 pio_write_8(&dev->b, b | TACK | TIP);
237 instance->xstate = cx_rcv_end;
238 }
239}
240
241/** Interrupt in rcv_end state.
242 *
243 * Terminate packet reception. Either go back to listen state or start
244 * receiving another packet if CUDA has one for us.
245 */
246static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len)
247{
248 cuda_instance_t *instance = irq->instance;
249 cuda_t *dev = instance->cuda;
250 uint8_t b;
251
252 b = pio_read_8(&dev->b);
253 pio_read_8(&dev->sr);
254
255 if ((b & TREQ) == 0) {
256 instance->xstate = cx_receive;
257 pio_write_8(&dev->b, b & ~TIP);
258 } else {
259 instance->xstate = cx_listen;
260 cuda_send_start(instance);
261 }
262
263 memcpy(buf, instance->rcv_buf, instance->bidx);
264 *len = instance->bidx;
265 instance->bidx = 0;
266}
267
268/** Interrupt in send_start state.
269 *
270 * Process result of sending first byte (and send second on success).
271 */
272static void cuda_irq_send_start(irq_t *irq)
273{
274 cuda_instance_t *instance = irq->instance;
275 cuda_t *dev = instance->cuda;
276 uint8_t b;
277
278 b = pio_read_8(&dev->b);
279
280 if ((b & TREQ) == 0) {
281 /* Collision */
282 pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
283 pio_read_8(&dev->sr);
284 pio_write_8(&dev->b, pio_read_8(&dev->b) | TIP | TACK);
285 instance->xstate = cx_listen;
286 return;
287 }
288
289 pio_write_8(&dev->sr, instance->snd_buf[1]);
290 pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
291 instance->bidx = 2;
292
293 instance->xstate = cx_send;
294}
295
296/** Interrupt in send state.
297 *
298 * Send next byte or terminate transmission.
299 */
300static void cuda_irq_send(irq_t *irq)
301{
302 cuda_instance_t *instance = irq->instance;
303 cuda_t *dev = instance->cuda;
304
305 if (instance->bidx < instance->snd_bytes) {
306 /* Send next byte. */
307 pio_write_8(&dev->sr, instance->snd_buf[instance->bidx++]);
308 pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
309 return;
310 }
311
312 /* End transfer. */
313 instance->snd_bytes = 0;
314 instance->bidx = 0;
315
316 pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
317 pio_read_8(&dev->sr);
318 pio_write_8(&dev->b, pio_read_8(&dev->b) | TACK | TIP);
319
320 instance->xstate = cx_listen;
321 /* TODO: Match reply with request. */
322}
323
324static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *data, size_t len)
325{
326 if (data[0] != 0x00 || data[1] != 0x40 || (data[2] != 0x2c &&
327 data[2] != 0x8c))
328 return;
329
330 /* The packet contains one or two scancodes. */
331 if (data[3] != 0xff)
332 indev_push_character(instance->kbrdin, data[3]);
333 if (data[4] != 0xff)
334 indev_push_character(instance->kbrdin, data[4]);
335}
336
337static void cuda_autopoll_set(cuda_instance_t *instance, bool enable)
338{
339 instance->snd_buf[0] = PT_CUDA;
340 instance->snd_buf[1] = CPT_AUTOPOLL;
341 instance->snd_buf[2] = enable ? 0x01 : 0x00;
342 instance->snd_bytes = 3;
343 instance->bidx = 0;
344
345 cuda_send_start(instance);
346}
347
348static void cuda_send_start(cuda_instance_t *instance)
349{
350 cuda_t *dev = instance->cuda;
351
352 assert(instance->xstate == cx_listen);
353
354 if (instance->snd_bytes == 0)
355 return;
356
357 /* Check for incoming data. */
358 if ((pio_read_8(&dev->b) & TREQ) == 0)
359 return;
360
361 pio_write_8(&dev->acr, pio_read_8(&dev->acr) | SR_OUT);
362 pio_write_8(&dev->sr, instance->snd_buf[0]);
363 pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
364
365 instance->xstate = cx_send_start;
366}
367
368/** @}
369 */
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