source: mainline/kernel/genarch/src/drivers/via-cuda/cuda.c@ 3009164

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 3009164 was 63e27ef, checked in by Jiri Svoboda <jiri@…>, 8 years ago

ASSERT → assert
  • Property mode set to 100644
File size: 8.7 KB
Line 
1/*
2 * Copyright (c) 2006 Martin Decky
3 * Copyright (c) 2009 Jiri Svoboda
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * - Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * - Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * - The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/** @addtogroup genarch
31 * @{
32 */
33/** @file
34 */
35
36#include <assert.h>
37#include <genarch/drivers/via-cuda/cuda.h>
38#include <console/chardev.h>
39#include <ddi/irq.h>
40#include <arch/asm.h>
41#include <mm/slab.h>
42#include <ddi/device.h>
43#include <synch/spinlock.h>
44#include <mem.h>
45
46static irq_ownership_t cuda_claim(irq_t *irq);
47static void cuda_irq_handler(irq_t *irq);
48
49static void cuda_irq_listen(irq_t *irq);
50static void cuda_irq_receive(irq_t *irq);
51static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len);
52static void cuda_irq_send_start(irq_t *irq);
53static void cuda_irq_send(irq_t *irq);
54
55static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *buf, size_t len);
56static void cuda_send_start(cuda_instance_t *instance);
57static void cuda_autopoll_set(cuda_instance_t *instance, bool enable);
58
59/** B register fields */
60enum {
61 TREQ = 0x08,
62 TACK = 0x10,
63 TIP = 0x20
64};
65
66/** IER register fields */
67enum {
68 IER_CLR = 0x00,
69 IER_SET = 0x80,
70
71 SR_INT = 0x04,
72 ALL_INT = 0x7f
73};
74
75/** ACR register fields */
76enum {
77 SR_OUT = 0x10
78};
79
80/** Packet types */
81enum {
82 PT_ADB = 0x00,
83 PT_CUDA = 0x01
84};
85
86/** CUDA packet types */
87enum {
88 CPT_AUTOPOLL = 0x01
89};
90
91cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg)
92{
93 cuda_instance_t *instance
94 = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC);
95 if (instance) {
96 instance->cuda = dev;
97 instance->kbrdin = NULL;
98 instance->xstate = cx_listen;
99 instance->bidx = 0;
100 instance->snd_bytes = 0;
101
102 spinlock_initialize(&instance->dev_lock, "cuda.instance.dev_lock");
103
104 /* Disable all interrupts from CUDA. */
105 pio_write_8(&dev->ier, IER_CLR | ALL_INT);
106
107 irq_initialize(&instance->irq);
108 instance->irq.devno = device_assign_devno();
109 instance->irq.inr = inr;
110 instance->irq.claim = cuda_claim;
111 instance->irq.handler = cuda_irq_handler;
112 instance->irq.instance = instance;
113 instance->irq.cir = cir;
114 instance->irq.cir_arg = cir_arg;
115 instance->irq.preack = true;
116 }
117
118 return instance;
119}
120
121#include <log.h>
122void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
123{
124 cuda_t *dev = instance->cuda;
125
126 assert(instance);
127 assert(kbrdin);
128
129 instance->kbrdin = kbrdin;
130 irq_register(&instance->irq);
131
132 /* Enable SR interrupt. */
133 pio_write_8(&dev->ier, TIP | TREQ);
134 pio_write_8(&dev->ier, IER_SET | SR_INT);
135
136 /* Enable ADB autopolling. */
137 cuda_autopoll_set(instance, true);
138}
139
140static irq_ownership_t cuda_claim(irq_t *irq)
141{
142 cuda_instance_t *instance = irq->instance;
143 cuda_t *dev = instance->cuda;
144 uint8_t ifr;
145
146 spinlock_lock(&instance->dev_lock);
147 ifr = pio_read_8(&dev->ifr);
148 spinlock_unlock(&instance->dev_lock);
149
150 if ((ifr & SR_INT) == 0)
151 return IRQ_DECLINE;
152
153 return IRQ_ACCEPT;
154}
155
156static void cuda_irq_handler(irq_t *irq)
157{
158 cuda_instance_t *instance = irq->instance;
159 uint8_t rbuf[CUDA_RCV_BUF_SIZE];
160 size_t len;
161 bool handle;
162
163 handle = false;
164 len = 0;
165
166 spinlock_lock(&instance->dev_lock);
167
168 /* Lower IFR.SR_INT so that CUDA can generate next int by raising it. */
169 pio_write_8(&instance->cuda->ifr, SR_INT);
170
171 switch (instance->xstate) {
172 case cx_listen: cuda_irq_listen(irq); break;
173 case cx_receive: cuda_irq_receive(irq); break;
174 case cx_rcv_end: cuda_irq_rcv_end(irq, rbuf, &len);
175 handle = true; break;
176 case cx_send_start: cuda_irq_send_start(irq); break;
177 case cx_send: cuda_irq_send(irq); break;
178 }
179
180 spinlock_unlock(&instance->dev_lock);
181
182 /* Handle an incoming packet. */
183 if (handle)
184 cuda_packet_handle(instance, rbuf, len);
185}
186
187/** Interrupt in listen state.
188 *
189 * Start packet reception.
190 */
191static void cuda_irq_listen(irq_t *irq)
192{
193 cuda_instance_t *instance = irq->instance;
194 cuda_t *dev = instance->cuda;
195 uint8_t b;
196
197 b = pio_read_8(&dev->b);
198
199 if ((b & TREQ) != 0) {
200 log(LF_OTHER, LVL_ERROR, "cuda_irq_listen: no TREQ?!");
201 return;
202 }
203
204 pio_read_8(&dev->sr);
205 pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
206 instance->xstate = cx_receive;
207}
208
209/** Interrupt in receive state.
210 *
211 * Receive next byte of packet.
212 */
213static void cuda_irq_receive(irq_t *irq)
214{
215 cuda_instance_t *instance = irq->instance;
216 cuda_t *dev = instance->cuda;
217 uint8_t b, data;
218
219 data = pio_read_8(&dev->sr);
220 if (instance->bidx < CUDA_RCV_BUF_SIZE)
221 instance->rcv_buf[instance->bidx++] = data;
222
223 b = pio_read_8(&dev->b);
224
225 if ((b & TREQ) == 0) {
226 pio_write_8(&dev->b, b ^ TACK);
227 } else {
228 pio_write_8(&dev->b, b | TACK | TIP);
229 instance->xstate = cx_rcv_end;
230 }
231}
232
233/** Interrupt in rcv_end state.
234 *
235 * Terminate packet reception. Either go back to listen state or start
236 * receiving another packet if CUDA has one for us.
237 */
238static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len)
239{
240 cuda_instance_t *instance = irq->instance;
241 cuda_t *dev = instance->cuda;
242 uint8_t b;
243
244 b = pio_read_8(&dev->b);
245 pio_read_8(&dev->sr);
246
247 if ((b & TREQ) == 0) {
248 instance->xstate = cx_receive;
249 pio_write_8(&dev->b, b & ~TIP);
250 } else {
251 instance->xstate = cx_listen;
252 cuda_send_start(instance);
253 }
254
255 memcpy(buf, instance->rcv_buf, instance->bidx);
256 *len = instance->bidx;
257 instance->bidx = 0;
258}
259
260/** Interrupt in send_start state.
261 *
262 * Process result of sending first byte (and send second on success).
263 */
264static void cuda_irq_send_start(irq_t *irq)
265{
266 cuda_instance_t *instance = irq->instance;
267 cuda_t *dev = instance->cuda;
268 uint8_t b;
269
270 b = pio_read_8(&dev->b);
271
272 if ((b & TREQ) == 0) {
273 /* Collision */
274 pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
275 pio_read_8(&dev->sr);
276 pio_write_8(&dev->b, pio_read_8(&dev->b) | TIP | TACK);
277 instance->xstate = cx_listen;
278 return;
279 }
280
281 pio_write_8(&dev->sr, instance->snd_buf[1]);
282 pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
283 instance->bidx = 2;
284
285 instance->xstate = cx_send;
286}
287
288/** Interrupt in send state.
289 *
290 * Send next byte or terminate transmission.
291 */
292static void cuda_irq_send(irq_t *irq)
293{
294 cuda_instance_t *instance = irq->instance;
295 cuda_t *dev = instance->cuda;
296
297 if (instance->bidx < instance->snd_bytes) {
298 /* Send next byte. */
299 pio_write_8(&dev->sr, instance->snd_buf[instance->bidx++]);
300 pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
301 return;
302 }
303
304 /* End transfer. */
305 instance->snd_bytes = 0;
306 instance->bidx = 0;
307
308 pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
309 pio_read_8(&dev->sr);
310 pio_write_8(&dev->b, pio_read_8(&dev->b) | TACK | TIP);
311
312 instance->xstate = cx_listen;
313 /* TODO: Match reply with request. */
314}
315
316static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *data, size_t len)
317{
318 if (data[0] != 0x00 || data[1] != 0x40 || (data[2] != 0x2c
319 && data[2] != 0x8c))
320 return;
321
322 /* The packet contains one or two scancodes. */
323 if (data[3] != 0xff)
324 indev_push_character(instance->kbrdin, data[3]);
325 if (data[4] != 0xff)
326 indev_push_character(instance->kbrdin, data[4]);
327}
328
329static void cuda_autopoll_set(cuda_instance_t *instance, bool enable)
330{
331 instance->snd_buf[0] = PT_CUDA;
332 instance->snd_buf[1] = CPT_AUTOPOLL;
333 instance->snd_buf[2] = enable ? 0x01 : 0x00;
334 instance->snd_bytes = 3;
335 instance->bidx = 0;
336
337 cuda_send_start(instance);
338}
339
340static void cuda_send_start(cuda_instance_t *instance)
341{
342 cuda_t *dev = instance->cuda;
343
344 assert(instance->xstate == cx_listen);
345
346 if (instance->snd_bytes == 0)
347 return;
348
349 /* Check for incoming data. */
350 if ((pio_read_8(&dev->b) & TREQ) == 0)
351 return;
352
353 pio_write_8(&dev->acr, pio_read_8(&dev->acr) | SR_OUT);
354 pio_write_8(&dev->sr, instance->snd_buf[0]);
355 pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
356
357 instance->xstate = cx_send_start;
358}
359
360
361/** @}
362 */
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