[8b1439e] | 1 | /*
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[df4ed85] | 2 | * Copyright (c) 2006 Martin Decky
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[2a77841d] | 3 | * Copyright (c) 2009 Jiri Svoboda
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[8b1439e] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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[c2417bc] | 30 | /** @addtogroup genarch
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[b45c443] | 31 | * @{
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| 32 | */
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| 33 | /** @file
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| 34 | */
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| 35 |
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[c2417bc] | 36 | #include <genarch/drivers/via-cuda/cuda.h>
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| 37 | #include <console/chardev.h>
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| 38 | #include <ddi/irq.h>
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| 39 | #include <arch/asm.h>
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| 40 | #include <mm/slab.h>
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| 41 | #include <ddi/device.h>
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[2a77841d] | 42 | #include <synch/spinlock.h>
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[eae4e8f] | 43 | #include <memstr.h>
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[2a77841d] | 44 |
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[450448d] | 45 | static irq_ownership_t cuda_claim(irq_t *irq);
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| 46 | static void cuda_irq_handler(irq_t *irq);
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| 47 |
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[1f0db02e] | 48 | static void cuda_irq_listen(irq_t *irq);
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| 49 | static void cuda_irq_receive(irq_t *irq);
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| 50 | static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len);
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[450448d] | 51 | static void cuda_irq_send_start(irq_t *irq);
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| 52 | static void cuda_irq_send(irq_t *irq);
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| 53 |
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| 54 | static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *buf, size_t len);
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| 55 | static void cuda_send_start(cuda_instance_t *instance);
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| 56 | static void cuda_autopoll_set(cuda_instance_t *instance, bool enable);
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[2a77841d] | 57 |
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| 58 | /** B register fields */
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| 59 | enum {
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| 60 | TREQ = 0x08,
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| 61 | TACK = 0x10,
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| 62 | TIP = 0x20
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| 63 | };
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| 64 |
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| 65 | /** IER register fields */
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| 66 | enum {
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[1f0db02e] | 67 | IER_CLR = 0x00,
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[2a77841d] | 68 | IER_SET = 0x80,
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[1f0db02e] | 69 |
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| 70 | SR_INT = 0x04,
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| 71 | ALL_INT = 0x7f
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| 72 | };
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| 73 |
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| 74 | /** ACR register fields */
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| 75 | enum {
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| 76 | SR_OUT = 0x10
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[2a77841d] | 77 | };
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[8b1439e] | 78 |
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[450448d] | 79 | /** Packet types */
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| 80 | enum {
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| 81 | PT_ADB = 0x00,
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| 82 | PT_CUDA = 0x01
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| 83 | };
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| 84 |
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| 85 | /** CUDA packet types */
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| 86 | enum {
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| 87 | CPT_AUTOPOLL = 0x01
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| 88 | };
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| 89 |
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| 90 | cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg)
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| 91 | {
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| 92 | cuda_instance_t *instance
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| 93 | = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC);
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| 94 | if (instance) {
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| 95 | instance->cuda = dev;
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| 96 | instance->kbrdin = NULL;
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| 97 | instance->xstate = cx_listen;
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| 98 | instance->bidx = 0;
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| 99 | instance->snd_bytes = 0;
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| 100 |
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| 101 | spinlock_initialize(&instance->dev_lock, "cuda_dev");
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| 102 |
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| 103 | /* Disable all interrupts from CUDA. */
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| 104 | pio_write_8(&dev->ier, IER_CLR | ALL_INT);
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| 105 |
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| 106 | irq_initialize(&instance->irq);
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| 107 | instance->irq.devno = device_assign_devno();
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| 108 | instance->irq.inr = inr;
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| 109 | instance->irq.claim = cuda_claim;
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| 110 | instance->irq.handler = cuda_irq_handler;
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| 111 | instance->irq.instance = instance;
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| 112 | instance->irq.cir = cir;
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| 113 | instance->irq.cir_arg = cir_arg;
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| 114 | instance->irq.preack = true;
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| 115 | }
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| 116 |
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| 117 | return instance;
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| 118 | }
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| 119 |
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[1f0db02e] | 120 | #include <print.h>
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[450448d] | 121 | void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
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| 122 | {
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| 123 | cuda_t *dev = instance->cuda;
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| 124 |
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| 125 | ASSERT(instance);
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| 126 | ASSERT(kbrdin);
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| 127 |
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| 128 | instance->kbrdin = kbrdin;
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| 129 | irq_register(&instance->irq);
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| 130 |
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| 131 | /* Enable SR interrupt. */
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| 132 | pio_write_8(&dev->ier, TIP | TREQ);
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| 133 | pio_write_8(&dev->ier, IER_SET | SR_INT);
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| 134 |
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| 135 | /* Enable ADB autopolling. */
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| 136 | cuda_autopoll_set(instance, true);
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| 137 | }
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| 138 |
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[c2417bc] | 139 | static irq_ownership_t cuda_claim(irq_t *irq)
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| 140 | {
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[2a77841d] | 141 | cuda_instance_t *instance = irq->instance;
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| 142 | cuda_t *dev = instance->cuda;
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| 143 | uint8_t ifr;
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| 144 |
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[450448d] | 145 | spinlock_lock(&instance->dev_lock);
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[2a77841d] | 146 | ifr = pio_read_8(&dev->ifr);
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[450448d] | 147 | spinlock_unlock(&instance->dev_lock);
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[2a77841d] | 148 |
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[1f0db02e] | 149 | if ((ifr & SR_INT) == 0)
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[2a77841d] | 150 | return IRQ_DECLINE;
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[1f0db02e] | 151 |
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| 152 | return IRQ_ACCEPT;
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[c2417bc] | 153 | }
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[8b1439e] | 154 |
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[c2417bc] | 155 | static void cuda_irq_handler(irq_t *irq)
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| 156 | {
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[2a77841d] | 157 | cuda_instance_t *instance = irq->instance;
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[1f0db02e] | 158 | uint8_t rbuf[CUDA_RCV_BUF_SIZE];
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| 159 | size_t len;
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| 160 | bool handle;
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| 161 |
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| 162 | handle = false;
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| 163 | len = 0;
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[2a77841d] | 164 |
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| 165 | spinlock_lock(&instance->dev_lock);
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| 166 |
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[1f0db02e] | 167 | /* Lower IFR.SR_INT so that CUDA can generate next int by raising it. */
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| 168 | pio_write_8(&instance->cuda->ifr, SR_INT);
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| 169 |
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| 170 | switch (instance->xstate) {
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| 171 | case cx_listen: cuda_irq_listen(irq); break;
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| 172 | case cx_receive: cuda_irq_receive(irq); break;
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| 173 | case cx_rcv_end: cuda_irq_rcv_end(irq, rbuf, &len);
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| 174 | handle = true; break;
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[450448d] | 175 | case cx_send_start: cuda_irq_send_start(irq); break;
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| 176 | case cx_send: cuda_irq_send(irq); break;
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[1f0db02e] | 177 | }
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[2a77841d] | 178 |
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[1f0db02e] | 179 | spinlock_unlock(&instance->dev_lock);
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[2a77841d] | 180 |
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[1f0db02e] | 181 | /* Handle an incoming packet. */
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| 182 | if (handle)
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| 183 | cuda_packet_handle(instance, rbuf, len);
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| 184 | }
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| 185 |
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| 186 | /** Interrupt in listen state.
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| 187 | *
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| 188 | * Start packet reception.
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| 189 | */
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| 190 | static void cuda_irq_listen(irq_t *irq)
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| 191 | {
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| 192 | cuda_instance_t *instance = irq->instance;
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| 193 | cuda_t *dev = instance->cuda;
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| 194 | uint8_t b;
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[2a77841d] | 195 |
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[1f0db02e] | 196 | b = pio_read_8(&dev->b);
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[2a77841d] | 197 |
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[1f0db02e] | 198 | if ((b & TREQ) != 0) {
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| 199 | printf("cuda_irq_listen: no TREQ?!\n");
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| 200 | return;
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| 201 | }
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[2a77841d] | 202 |
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[1f0db02e] | 203 | pio_read_8(&dev->sr);
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| 204 | pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
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| 205 | instance->xstate = cx_receive;
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| 206 | }
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[2a77841d] | 207 |
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[1f0db02e] | 208 | /** Interrupt in receive state.
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| 209 | *
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| 210 | * Receive next byte of packet.
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| 211 | */
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| 212 | static void cuda_irq_receive(irq_t *irq)
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| 213 | {
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| 214 | cuda_instance_t *instance = irq->instance;
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| 215 | cuda_t *dev = instance->cuda;
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| 216 | uint8_t b, data;
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| 217 |
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| 218 | data = pio_read_8(&dev->sr);
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| 219 | if (instance->bidx < CUDA_RCV_BUF_SIZE)
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| 220 | instance->rcv_buf[instance->bidx++] = data;
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| 221 |
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| 222 | b = pio_read_8(&dev->b);
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| 223 |
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| 224 | if ((b & TREQ) == 0) {
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| 225 | pio_write_8(&dev->b, b ^ TACK);
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| 226 | } else {
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[2a77841d] | 227 | pio_write_8(&dev->b, b | TACK | TIP);
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[1f0db02e] | 228 | instance->xstate = cx_rcv_end;
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| 229 | }
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| 230 | }
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[2a77841d] | 231 |
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[1f0db02e] | 232 | /** Interrupt in rcv_end state.
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| 233 | *
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| 234 | * Terminate packet reception. Either go back to listen state or start
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| 235 | * receiving another packet if CUDA has one for us.
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| 236 | */
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| 237 | static void cuda_irq_rcv_end(irq_t *irq, void *buf, size_t *len)
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| 238 | {
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| 239 | cuda_instance_t *instance = irq->instance;
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| 240 | cuda_t *dev = instance->cuda;
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| 241 | uint8_t data, b;
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| 242 |
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| 243 | b = pio_read_8(&dev->b);
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| 244 | data = pio_read_8(&dev->sr);
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| 245 |
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| 246 | if ((b & TREQ) == 0) {
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| 247 | instance->xstate = cx_receive;
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| 248 | pio_write_8(&dev->b, b & ~TIP);
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| 249 | } else {
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| 250 | instance->xstate = cx_listen;
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[450448d] | 251 | cuda_send_start(instance);
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[2a77841d] | 252 | }
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| 253 |
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[1f0db02e] | 254 | memcpy(buf, instance->rcv_buf, instance->bidx);
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| 255 | *len = instance->bidx;
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| 256 | instance->bidx = 0;
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[2a77841d] | 257 | }
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| 258 |
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[450448d] | 259 | /** Interrupt in send_start state.
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| 260 | *
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| 261 | * Process result of sending first byte (and send second on success).
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| 262 | */
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| 263 | static void cuda_irq_send_start(irq_t *irq)
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| 264 | {
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| 265 | cuda_instance_t *instance = irq->instance;
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| 266 | cuda_t *dev = instance->cuda;
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| 267 | uint8_t b;
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| 268 |
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| 269 | b = pio_read_8(&dev->b);
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| 270 |
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| 271 | if ((b & TREQ) == 0) {
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| 272 | /* Collision */
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| 273 | pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
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| 274 | pio_read_8(&dev->sr);
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| 275 | pio_write_8(&dev->b, pio_read_8(&dev->b) | TIP | TACK);
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| 276 | instance->xstate = cx_listen;
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| 277 | return;
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| 278 | }
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| 279 |
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| 280 | pio_write_8(&dev->sr, instance->snd_buf[1]);
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| 281 | pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
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| 282 | instance->bidx = 2;
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| 283 |
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| 284 | instance->xstate = cx_send;
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| 285 | }
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| 286 |
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| 287 | /** Interrupt in send state.
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| 288 | *
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| 289 | * Send next byte or terminate transmission.
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| 290 | */
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| 291 | static void cuda_irq_send(irq_t *irq)
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| 292 | {
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| 293 | cuda_instance_t *instance = irq->instance;
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| 294 | cuda_t *dev = instance->cuda;
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| 295 |
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| 296 | if (instance->bidx < instance->snd_bytes) {
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| 297 | /* Send next byte. */
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| 298 | pio_write_8(&dev->sr, instance->snd_buf[instance->bidx++]);
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| 299 | pio_write_8(&dev->b, pio_read_8(&dev->b) ^ TACK);
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| 300 | return;
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| 301 | }
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| 302 |
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| 303 | /* End transfer. */
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| 304 | instance->snd_bytes = 0;
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| 305 | instance->bidx = 0;
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| 306 |
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| 307 | pio_write_8(&dev->acr, pio_read_8(&dev->acr) & ~SR_OUT);
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| 308 | pio_read_8(&dev->sr);
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| 309 | pio_write_8(&dev->b, pio_read_8(&dev->b) | TACK | TIP);
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| 310 |
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| 311 | instance->xstate = cx_listen;
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| 312 | /* TODO: Match reply with request. */
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| 313 | }
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| 314 |
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[1f0db02e] | 315 | static void cuda_packet_handle(cuda_instance_t *instance, uint8_t *data, size_t len)
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[2a77841d] | 316 | {
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[1f0db02e] | 317 | if (data[0] != 0x00 || data[1] != 0x40 || (data[2] != 0x2c
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| 318 | && data[2] != 0x8c))
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[2a77841d] | 319 | return;
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| 320 |
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| 321 | /* The packet contains one or two scancodes. */
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| 322 | if (data[3] != 0xff)
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| 323 | indev_push_character(instance->kbrdin, data[3]);
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| 324 | if (data[4] != 0xff)
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| 325 | indev_push_character(instance->kbrdin, data[4]);
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[c2417bc] | 326 | }
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| 327 |
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[450448d] | 328 | static void cuda_autopoll_set(cuda_instance_t *instance, bool enable)
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[c2417bc] | 329 | {
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[450448d] | 330 | instance->snd_buf[0] = PT_CUDA;
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| 331 | instance->snd_buf[1] = CPT_AUTOPOLL;
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| 332 | instance->snd_buf[2] = enable ? 0x01 : 0x00;
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| 333 | instance->snd_bytes = 3;
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| 334 | instance->bidx = 0;
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[1f0db02e] | 335 |
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[450448d] | 336 | cuda_send_start(instance);
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[c2417bc] | 337 | }
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| 338 |
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[450448d] | 339 | static void cuda_send_start(cuda_instance_t *instance)
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[c2417bc] | 340 | {
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[1f0db02e] | 341 | cuda_t *dev = instance->cuda;
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| 342 |
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[450448d] | 343 | ASSERT(instance->xstate == cx_listen);
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[2a77841d] | 344 |
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[450448d] | 345 | if (instance->snd_bytes == 0)
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| 346 | return;
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[e4ddfa8] | 347 |
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[450448d] | 348 | /* Check for incoming data. */
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| 349 | if ((pio_read_8(&dev->b) & TREQ) == 0)
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| 350 | return;
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| 351 |
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| 352 | pio_write_8(&dev->acr, pio_read_8(&dev->acr) | SR_OUT);
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| 353 | pio_write_8(&dev->sr, instance->snd_buf[0]);
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| 354 | pio_write_8(&dev->b, pio_read_8(&dev->b) & ~TIP);
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| 355 |
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| 356 | instance->xstate = cx_send_start;
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[2a77841d] | 357 | }
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[b45c443] | 358 |
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[450448d] | 359 |
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[281994b] | 360 | /** @}
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[b45c443] | 361 | */
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