[8b4be29] | 1 | /*
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[4c7257b] | 2 | * Copyright (c) 2009 Jakub Jermar
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[38b0ae2] | 3 | * Copyright (c) 2018 CZ.NIC, z.s.p.o.
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[8b4be29] | 4 | * All rights reserved.
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| 5 | *
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| 6 | * Redistribution and use in source and binary forms, with or without
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| 7 | * modification, are permitted provided that the following conditions
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| 8 | * are met:
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| 9 | *
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| 10 | * - Redistributions of source code must retain the above copyright
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| 11 | * notice, this list of conditions and the following disclaimer.
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| 12 | * - Redistributions in binary form must reproduce the above copyright
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| 13 | * notice, this list of conditions and the following disclaimer in the
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| 14 | * documentation and/or other materials provided with the distribution.
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| 15 | * - The name of the author may not be used to endorse or promote products
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| 16 | * derived from this software without specific prior written permission.
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| 17 | *
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| 18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 28 | */
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| 29 |
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[6404aca] | 30 | /** @addtogroup kernel_genarch
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[8b4be29] | 31 | * @{
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| 32 | */
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| 33 | /**
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| 34 | * @file
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[3c79afe] | 35 | * @brief NS 16550 serial controller driver.
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[8b4be29] | 36 | */
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| 37 |
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[63e27ef] | 38 | #include <assert.h>
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[411b6a6] | 39 | #include <genarch/drivers/ns16550/ns16550.h>
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[7dcf22a] | 40 | #include <ddi/irq.h>
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[82dcd25] | 41 | #include <ddi/ddi.h>
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[8b4be29] | 42 | #include <arch/asm.h>
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| 43 | #include <console/chardev.h>
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[aafed15] | 44 | #include <stdlib.h>
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[82dcd25] | 45 | #include <align.h>
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[6bbe470] | 46 | #include <str.h>
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[8b4be29] | 47 |
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[3c79afe] | 48 | #define LSR_DATA_READY 0x01
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[6bbe470] | 49 | #define LSR_TH_READY 0x20
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[3c79afe] | 50 |
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[cbc3587] | 51 | #define RETRY_CNT 100000
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| 52 |
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| 53 | #define NOTHING \
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| 54 | do { \
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| 55 | } while(0)
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| 56 |
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| 57 | #define WHILE_CNT_AND_COND_DO(cnt, expr, statement) \
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| 58 | do { \
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| 59 | for (volatile unsigned i = 0; i < (cnt); i++) \
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| 60 | if ((expr)) \
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| 61 | statement; \
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| 62 | else \
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| 63 | break; \
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| 64 | } while (0)
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| 65 |
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[448e093] | 66 | static uint8_t ns16550_reg_read(ns16550_instance_t *inst, ns16550_reg_t reg)
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| 67 | {
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[38b0ae2] | 68 | return pio_read_8(&inst->ns16550[reg << inst->reg_shift]);
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| 69 | }
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| 70 |
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[448e093] | 71 | static void ns16550_reg_write(ns16550_instance_t *inst, ns16550_reg_t reg,
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| 72 | uint8_t val)
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| 73 | {
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[38b0ae2] | 74 | pio_write_8(&inst->ns16550[reg << inst->reg_shift], val);
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| 75 | }
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| 76 |
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[3c79afe] | 77 | static irq_ownership_t ns16550_claim(irq_t *irq)
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| 78 | {
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| 79 | ns16550_instance_t *instance = irq->instance;
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[38b0ae2] | 80 |
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[448e093] | 81 | if (ns16550_reg_read(instance, NS16550_REG_LSR) & LSR_DATA_READY)
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[3c79afe] | 82 | return IRQ_ACCEPT;
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| 83 | else
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| 84 | return IRQ_DECLINE;
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| 85 | }
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| 86 |
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| 87 | static void ns16550_irq_handler(irq_t *irq)
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| 88 | {
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| 89 | ns16550_instance_t *instance = irq->instance;
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[a35b458] | 90 |
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[448e093] | 91 | while (ns16550_reg_read(instance, NS16550_REG_LSR) & LSR_DATA_READY) {
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| 92 | uint8_t data = ns16550_reg_read(instance, NS16550_REG_RBR);
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[6bbe470] | 93 | indev_push_character(instance->input, data);
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[3c79afe] | 94 | }
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| 95 | }
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[8b4be29] | 96 |
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[cbc3587] | 97 | /** Clear input buffer. */
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[38b0ae2] | 98 | static void ns16550_clear_buffer(ns16550_instance_t *instance)
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[c2417bc] | 99 | {
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[cbc3587] | 100 | WHILE_CNT_AND_COND_DO(RETRY_CNT,
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| 101 | ns16550_reg_read(instance, NS16550_REG_LSR) & LSR_DATA_READY,
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| 102 | (void) ns16550_reg_read(instance, NS16550_REG_RBR));
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[c2417bc] | 103 | }
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| 104 |
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[38b0ae2] | 105 | static void ns16550_sendb(ns16550_instance_t *instance, uint8_t byte)
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[6bbe470] | 106 | {
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[cbc3587] | 107 | WHILE_CNT_AND_COND_DO(RETRY_CNT,
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| 108 | !(ns16550_reg_read(instance, NS16550_REG_LSR) & LSR_TH_READY),
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| 109 | NOTHING);
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| 110 |
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[448e093] | 111 | ns16550_reg_write(instance, NS16550_REG_THR, byte);
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[6bbe470] | 112 | }
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| 113 |
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[39e1b9a] | 114 | static void ns16550_write(outdev_t *dev, const char *s, size_t n)
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[6bbe470] | 115 | {
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| 116 | ns16550_instance_t *instance = (ns16550_instance_t *) dev->data;
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[a35b458] | 117 |
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[39e1b9a] | 118 | if (instance->parea.mapped && !console_override)
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| 119 | return;
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| 120 |
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| 121 | const char *top = s + n;
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| 122 | assert(top >= s);
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| 123 |
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| 124 | for (; s < top; s++) {
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| 125 | if (*s == '\n')
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[fa70134] | 126 | ns16550_sendb(instance, '\r');
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| 127 |
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[39e1b9a] | 128 | ns16550_sendb(instance, (uint8_t) *s);
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[6bbe470] | 129 | }
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| 130 | }
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| 131 |
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| 132 | static outdev_operations_t ns16550_ops = {
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[39e1b9a] | 133 | .write = ns16550_write,
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[6bbe470] | 134 | .redraw = NULL
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| 135 | };
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| 136 |
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[98a935e] | 137 | /** Configure ns16550 transmission format.
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| 138 | *
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| 139 | * @param instance NS 16550 driver instance.
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| 140 | * @param baud_rate Transmission speed in bits per second, also known as baud,
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| 141 | * maximum value is 115200.
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| 142 | * @param lcr_format Line Control Register configuration bits, as defined by
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| 143 | * the @c LCR_ macros. These configure the word width,
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| 144 | * parity type, and stop bit count.
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| 145 | */
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| 146 | void ns16550_format_set(ns16550_instance_t *instance,
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| 147 | unsigned baud_rate, uint8_t lcr_format)
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| 148 | {
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| 149 | uint16_t divisor;
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| 150 |
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| 151 | divisor = (uint16_t)(NS156440_CLOCK / baud_rate);
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| 152 | if (divisor == 0)
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| 153 | divisor = 1; /* Avoid division by zero. */
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| 154 |
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| 155 | ns16550_reg_write(instance, NS16550_REG_LCR, LCR_DLAB);
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| 156 | ns16550_reg_write(instance, NS16550_REG_DLL, divisor & 0xFF);
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| 157 | ns16550_reg_write(instance, NS16550_REG_DLH, (divisor >> 8) & 0xFF);
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| 158 | ns16550_reg_write(instance, NS16550_REG_LCR, lcr_format & ~LCR_DLAB);
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| 159 | }
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| 160 |
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[63530c62] | 161 | /** Initialize ns16550.
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| 162 | *
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[38b0ae2] | 163 | * @param dev Address of the beginning of the device in I/O space.
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| 164 | * @param reg_shift Spacing between individual register addresses, in log2.
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| 165 | * The individual register location is calculated as
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| 166 | * `base + (register offset << reg_shift)`.
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| 167 | * @param inr Interrupt number.
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| 168 | * @param cir Clear interrupt function.
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| 169 | * @param cir_arg First argument to cir.
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| 170 | * @param output Where to store pointer to the output device
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| 171 | * or NULL if the caller is not interested in
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| 172 | * writing to the serial port.
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[3c79afe] | 173 | *
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[c2417bc] | 174 | * @return Keyboard instance or NULL on failure.
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[013c4d6] | 175 | *
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[63530c62] | 176 | */
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[82dcd25] | 177 | ns16550_instance_t *ns16550_init(ioport8_t *dev_phys, unsigned reg_shift,
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| 178 | inr_t inr, cir_t cir, void *cir_arg, outdev_t **output)
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[8b4be29] | 179 | {
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[82dcd25] | 180 | size_t size = 6 * (1U << reg_shift);
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| 181 | ioport8_t *dev = pio_map((void *) dev_phys, size);
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| 182 |
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| 183 | ns16550_instance_t *instance = malloc(sizeof(ns16550_instance_t));
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[c2417bc] | 184 | if (instance) {
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| 185 | instance->ns16550 = dev;
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[38b0ae2] | 186 | instance->reg_shift = reg_shift;
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[6bbe470] | 187 | instance->input = NULL;
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| 188 | instance->output = NULL;
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[a35b458] | 189 |
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[21b6307] | 190 | if (output) {
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[11b285d] | 191 | instance->output = malloc(sizeof(outdev_t));
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[21b6307] | 192 | if (!instance->output) {
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| 193 | free(instance);
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[82dcd25] | 194 | pio_unmap((void *) dev_phys, (void *) dev,
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| 195 | size);
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[21b6307] | 196 | return NULL;
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| 197 | }
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[a35b458] | 198 |
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[21b6307] | 199 | outdev_initialize("ns16550", instance->output,
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| 200 | &ns16550_ops);
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| 201 | instance->output->data = instance;
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| 202 | *output = instance->output;
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| 203 | }
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[a35b458] | 204 |
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[c2417bc] | 205 | irq_initialize(&instance->irq);
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| 206 | instance->irq.inr = inr;
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| 207 | instance->irq.claim = ns16550_claim;
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| 208 | instance->irq.handler = ns16550_irq_handler;
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| 209 | instance->irq.instance = instance;
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| 210 | instance->irq.cir = cir;
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| 211 | instance->irq.cir_arg = cir_arg;
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[a35b458] | 212 |
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[6f7071b] | 213 | ddi_parea_init(&instance->parea);
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[82dcd25] | 214 | instance->parea.pbase = ALIGN_DOWN((uintptr_t) dev_phys,
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| 215 | PAGE_SIZE);
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| 216 | instance->parea.frames = ALIGN_UP(size, PAGE_SIZE);
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[6bbe470] | 217 | instance->parea.unpriv = false;
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| 218 | instance->parea.mapped = false;
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| 219 | ddi_parea_register(&instance->parea);
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[c2417bc] | 220 | }
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[a35b458] | 221 |
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[c2417bc] | 222 | return instance;
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| 223 | }
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| 224 |
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[6bbe470] | 225 | void ns16550_wire(ns16550_instance_t *instance, indev_t *input)
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[c2417bc] | 226 | {
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[63e27ef] | 227 | assert(instance);
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| 228 | assert(input);
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[a35b458] | 229 |
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[6bbe470] | 230 | instance->input = input;
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[dc22844] | 231 | irq_register(&instance->irq);
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[a35b458] | 232 |
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[38b0ae2] | 233 | ns16550_clear_buffer(instance);
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[a35b458] | 234 |
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[3e53ab7] | 235 | /* Enable interrupts */
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[448e093] | 236 | ns16550_reg_write(instance, NS16550_REG_IER, IER_ERBFI);
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| 237 | ns16550_reg_write(instance, NS16550_REG_MCR, MCR_OUT2);
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[0d107f31] | 238 | }
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| 239 |
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[8b4be29] | 240 | /** @}
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| 241 | */
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