source: mainline/kernel/genarch/src/drivers/grlib_irqmp/grlib_irqmp.c@ 4d2dba7

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4d2dba7 was 4d2dba7, checked in by Jakub Klama <jakub.klama@…>, 12 years ago

Implementation of IRQMP interrupt controller and UART drivers, part 2.
Modified kernel config files to reflect presence of new drivers.

  • Property mode set to 100644
File size: 2.6 KB
Line 
1/*
2 * Copyright (c) 2013 Jakub Klama
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup genarch
30 * @{
31 */
32/**
33 * @file
34 * @brief Gaisler GRLIB interrupt controller.
35 */
36
37#include <genarch/drivers/grlib_irqmp/grlib_irqmp.h>
38#include <arch/asm.h>
39
40#include <mm/km.h>
41
42void grlib_irqmp_init(grlib_irqmp_t *irqc, bootinfo_t *bootinfo)
43{
44 irqc->regs = (void *) km_map(bootinfo->intc_base, PAGE_SIZE,
45 PAGE_NOT_CACHEABLE);
46
47 /* Mask all interrupts */
48 pio_write_32((void *)&irqc->regs + GRLIB_IRQMP_MASK_OFFSET, 0);
49}
50
51int grlib_irqmp_inum_get(grlib_irqmp_t *irqc)
52{
53 int i;
54 uint32_t pending = pio_read_32(&irqc->regs->pending);
55
56 for (i = 1; i < 16; i++) {
57 if (pending & (1 << i))
58 return i;
59 }
60
61 return -1;
62}
63
64void grlib_irqmp_clear(grlib_irqmp_t *irqc, int inum)
65{
66 pio_write_32(&irqc->regs->clear, (1 << inum));
67}
68
69void grlib_irqmp_mask(grlib_irqmp_t *irqc, int src)
70{
71 uint32_t mask = pio_read_32((void *)&irqc->regs + GRLIB_IRQMP_MASK_OFFSET);
72
73 mask &= ~(1 << src);
74
75 pio_write_32((void *)&irqc->regs + GRLIB_IRQMP_MASK_OFFSET, mask);
76}
77
78void grlib_irqmp_unmask(grlib_irqmp_t *irqc, int src)
79{
80 uint32_t mask = pio_read_32((void *)&irqc->regs + GRLIB_IRQMP_MASK_OFFSET);
81
82 mask |= (1 << src);
83
84 pio_write_32((void *)&irqc->regs + GRLIB_IRQMP_MASK_OFFSET, mask);
85}
86
87/** @}
88 */
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