| 1 | /*
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| 2 | * Copyright (c) 2009 Vineeth Pillai
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | /** @addtogroup kernel_genarch
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| 30 | * @{
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| 31 | */
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| 32 | /** @file
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| 33 | * @brief Describes the pl050 keyboard/mouse controller
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| 34 | */
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| 35 |
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| 36 | /**
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| 37 | * This file implements pl050 specific functions for keyboard and mouse
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| 38 | */
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| 39 |
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| 40 | #ifndef KERN_genarch_PL050_H
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| 41 | #define KERN_genarch_PL050_H
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| 42 |
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| 43 | #include <ddi/irq.h>
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| 44 | #include <console/chardev.h>
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| 45 | #include <typedefs.h>
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| 46 |
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| 47 | /*
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| 48 | * pl050 register offsets from the base address
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| 49 | */
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| 50 | #define PL050_CR 0x00
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| 51 | #define PL050_STAT 0x04
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| 52 | #define PL050_DATA 0x08
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| 53 | #define PL050_CLOCKDIV 0x0C
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| 54 | #define PL050_INTRSTAT 0x10
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| 55 |
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| 56 | /*
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| 57 | * Control Register Bits
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| 58 | */
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| 59 | #define PL050_CR_TYPE (1 << 5) /* Type 0: PS2/AT mode, 1: No Line control bit mode */
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| 60 | #define PL050_CR_RXINTR (1 << 4) /* Recieve Interrupt Enable */
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| 61 | #define PL050_CR_TXINTR (1 << 3) /* Transmit Interrupt Enable */
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| 62 | #define PL050_CR_INTR (1 << 2) /* Interrupt Enable */
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| 63 | #define PL050_CR_FKMID (1 << 1) /* Force KMI Data Low */
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| 64 | #define PL050_CR_FKMIC 1 /* Force KMI Clock Low */
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| 65 |
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| 66 | /*
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| 67 | * Status register bits
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| 68 | */
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| 69 | #define PL050_STAT_TXEMPTY (1 << 6) /* 1: Transmit register empty */
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| 70 | #define PL050_STAT_TXBUSY (1 << 5) /* 1: Busy, sending data */
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| 71 | #define PL050_STAT_RXFULL (1 << 4) /* 1: register Full */
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| 72 | #define PL050_STAT_RXBUSY (1 << 3) /* 1: Busy, recieving Data */
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| 73 | #define PL050_STAT_RXPARITY (1 << 2) /* odd parity of the last bit received */
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| 74 | #define PL050_STAT_KMIC (1 << 1) /* status of KMICLKIN */
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| 75 | #define PL050_STAT_KMID 1 /* status of KMIDATAIN */
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| 76 |
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| 77 | /*
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| 78 | * Interrupt status register bits.
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| 79 | */
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| 80 | #define PL050_TX_INTRSTAT (1 << 1) /* Transmit intr asserted */
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| 81 | #define PL050_RX_INTRSTAT 1 /* Recieve intr asserted */
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| 82 |
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| 83 | typedef struct {
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| 84 | ioport8_t *base;
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| 85 | ioport8_t *data;
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| 86 | ioport8_t *status;
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| 87 | ioport8_t *ctrl;
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| 88 | } pl050_t;
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| 89 |
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| 90 | typedef struct {
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| 91 | irq_t irq;
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| 92 | pl050_t *pl050;
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| 93 | indev_t *kbrdin;
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| 94 | } pl050_instance_t;
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| 95 |
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| 96 | extern pl050_instance_t *pl050_init(pl050_t *, inr_t);
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| 97 | extern void pl050_wire(pl050_instance_t *, indev_t *);
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| 98 |
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| 99 | #endif
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| 100 |
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| 101 | /** @}
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| 102 | */
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