| 1 | /*
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| 2 | * Copyright (c) 2012 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 | /** @addtogroup genarch
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| 29 | * @{
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| 30 | */
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| 31 | /**
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| 32 | * @file
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| 33 | * @brief Texas Instruments AM/DM37x MPU general purpose timer driver.
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| 34 | */
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| 35 |
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| 36 | #ifndef KERN_AMDM37x_GPT_H_
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| 37 | #define KERN_AMDM37x_GPT_H_
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| 38 |
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| 39 | #include <typedefs.h>
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| 40 | #include <mm/km.h>
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| 41 | #include <time/clock.h>
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| 42 |
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| 43 | /* AMDM37x TRM p. 2740 */
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| 44 | #define AMDM37x_GPT1_BASE_ADDRESS 0x48318000
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| 45 | #define AMDM37x_GPT1_SIZE 4096
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| 46 | #define AMDM37x_GPT1_IRQ 37
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| 47 | #define AMDM37x_GPT2_BASE_ADDRESS 0x49032000
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| 48 | #define AMDM37x_GPT2_SIZE 4096
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| 49 | #define AMDM37x_GPT2_IRQ 38
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| 50 | #define AMDM37x_GPT3_BASE_ADDRESS 0x49034000
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| 51 | #define AMDM37x_GPT3_SIZE 4096
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| 52 | #define AMDM37x_GPT3_IRQ 39
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| 53 | #define AMDM37x_GPT4_BASE_ADDRESS 0x49036000
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| 54 | #define AMDM37x_GPT4_SIZE 4096
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| 55 | #define AMDM37x_GPT4_IRQ 40
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| 56 | #define AMDM37x_GPT5_BASE_ADDRESS 0x49038000
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| 57 | #define AMDM37x_GPT5_SIZE 4096
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| 58 | #define AMDM37x_GPT5_IRQ 41
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| 59 | #define AMDM37x_GPT6_BASE_ADDRESS 0x4903a000
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| 60 | #define AMDM37x_GPT6_SIZE 4096
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| 61 | #define AMDM37x_GPT6_IRQ 42
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| 62 | #define AMDM37x_GPT7_BASE_ADDRESS 0x4903c000
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| 63 | #define AMDM37x_GPT7_SIZE 4096
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| 64 | #define AMDM37x_GPT7_IRQ 43
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| 65 | #define AMDM37x_GPT8_BASE_ADDRESS 0x4903e000
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| 66 | #define AMDM37x_GPT8_SIZE 4096
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| 67 | #define AMDM37x_GPT8_IRQ 44
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| 68 | #define AMDM37x_GPT9_BASE_ADDRESS 0x49040000
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| 69 | #define AMDM37x_GPT9_SIZE 4096
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| 70 | #define AMDM37x_GPT9_IRQ 45
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| 71 | #define AMDM37x_GPT10_BASE_ADDRESS 0x48086000
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| 72 | #define AMDM37x_GPT10_SIZE 4096
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| 73 | #define AMDM37x_GPT10_IRQ 46
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| 74 | #define AMDM37x_GPT11_BASE_ADDRESS 0x48088000
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| 75 | #define AMDM37x_GPT11_SIZE 4096
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| 76 | #define AMDM37x_GPT11_IRQ 47
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| 77 |
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| 78 |
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| 79 | /** GPT register map AMDM37x TRM p. 2740 */
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| 80 | typedef struct {
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| 81 | /** IP revision */
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| 82 | const ioport32_t tidr;
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| 83 | #define AMDM37x_GPT_TIDR_MINOR_MASK (0xf)
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| 84 | #define AMDM37x_GPT_TIDR_MINOR_SHIFT (0)
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| 85 | #define AMDM37x_GPT_TIDR_MAJOR_MASK (0xf)
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| 86 | #define AMDM37x_GPT_TIDR_MAJOR_SHIFT (4)
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| 87 | uint32_t padd0_[3];
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| 88 |
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| 89 | /** L4 Interface parameters */
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| 90 | ioport32_t tiocp_cfg;
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| 91 | #define AMDM37x_GPT_TIOCP_CFG_AUTOIDLE_FLAG (1 << 0)
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| 92 | #define AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG (1 << 1)
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| 93 | #define AMDM37x_GPT_TIOCP_CFG_ENWAKEUP_FLAG (1 << 2)
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| 94 | #define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_MASK (0x3)
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| 95 | #define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_SHIFT (3)
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| 96 | #define AMDM37x_GPT_TIOCP_CFG_EMUFREE_FlAG (1 << 5)
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| 97 | #define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_MASK (0x3)
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| 98 | #define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_SHIFT (8)
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| 99 |
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| 100 | /** Module status information, excluding irq */
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| 101 | const ioport32_t tistat;
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| 102 | #define AMDM37x_GPT_TISTAT_RESET_DONE_FLAG (1 << 0)
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| 103 |
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| 104 | /** Interrupt status register */
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| 105 | ioport32_t tisr;
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| 106 | #define AMDM37x_GPT_TISR_MAT_IRQ_FLAG (1 << 0)
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| 107 | #define AMDM37x_GPT_TISR_OVF_IRQ_FLAG (1 << 1)
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| 108 | #define AMDM37x_GPT_TISR_TCAR_IRQ_FLAG (1 << 2)
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| 109 |
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| 110 | /* Interrupt enable register */
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| 111 | ioport32_t tier;
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| 112 | #define AMDM37x_GPT_TIER_MAT_IRQ_FLAG (1 << 0)
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| 113 | #define AMDM37x_GPT_TIER_OVF_IRQ_FLAG (1 << 1)
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| 114 | #define AMDM37x_GPT_TIER_TCAR_IRQ_FLAG (1 << 2)
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| 115 |
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| 116 | /** Wakeup enable register */
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| 117 | ioport32_t twer;
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| 118 | #define AMDM37x_GPT_TWER_MAT_IRQ_FLAG (1 << 0)
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| 119 | #define AMDM37x_GPT_TWER_OVF_IRQ_FLAG (1 << 1)
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| 120 | #define AMDM37x_GPT_TWER_TCAR_IRQ_FLAG (1 << 2)
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| 121 |
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| 122 | /** Optional features control register */
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| 123 | ioport32_t tclr;
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| 124 | #define AMDM37x_GPT_TCLR_ST_FLAG (1 << 0)
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| 125 | #define AMDM37x_GPT_TCLR_AR_FLAG (1 << 1)
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| 126 | #define AMDM37x_GPT_TCLR_PTV_MASK (0x7)
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| 127 | #define AMDM37x_GPT_TCLR_PTV_SHIFT (2)
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| 128 | #define AMDM37x_GPT_TCLR_PRE_FLAG (1 << 5)
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| 129 | #define AMDM37x_GPT_TCLR_CE_FLAG (1 << 6)
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| 130 | #define AMDM37x_GPT_TCLR_SCPWM (1 << 7)
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| 131 | #define AMDM37x_GPT_TCLR_TCM_MASK (0x3 << 8)
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| 132 | #define AMDM37x_GPT_TCLR_TCM_NO_CAPTURE (0x0 << 8)
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| 133 | #define AMDM37x_GPT_TCLR_TCM_RAISE_CAPTURE (0x1 << 8)
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| 134 | #define AMDM37x_GPT_TCLR_TCM_FALL_CAPTURE (0x2 << 8)
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| 135 | #define AMDM37x_GPT_TCLR_TCM_BOTH_CAPTURE (0x3 << 8)
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| 136 | #define AMDM37x_GPT_TCLR_TRG_MASK (0x3 << 10)
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| 137 | #define AMDM37x_GPT_TCLR_TRG_NO (0x0 << 10)
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| 138 | #define AMDM37x_GPT_TCLR_TRG_OVERFLOW (0x1 << 10)
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| 139 | #define AMDM37x_GPT_TCLR_TRG_OVERMATCH (0x2 << 10)
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| 140 | #define AMDM37x_GPT_TCLR_PT_FLAG (1 << 12)
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| 141 | #define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG (1 << 13)
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| 142 | #define AMDM37x_GPT_TCLR_GPO_CFG_FLAG (1 << 14)
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| 143 |
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| 144 | /** Value of timer counter */
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| 145 | ioport32_t tccr;
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| 146 |
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| 147 | /** Timer load register */
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| 148 | ioport32_t tldr;
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| 149 |
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| 150 | /** Timer trigger register */
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| 151 | ioport32_t ttgr;
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| 152 |
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| 153 | /** Write-posted pending register */
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| 154 | const ioport32_t twps;
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| 155 | #define AMDM37x_GPT_TWPS_TCLR_FLAG (1 << 0)
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| 156 | #define AMDM37x_GPT_TWPS_TCRR_FLAG (1 << 1)
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| 157 | #define AMDM37x_GPT_TWPS_TLDR_FLAG (1 << 2)
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| 158 | #define AMDM37x_GPT_TWPS_TTGR_FLAG (1 << 3)
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| 159 | #define AMDM37x_GPT_TWPS_TMAR_FLAG (1 << 4)
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| 160 | #define AMDM37x_GPT_TWPS_TPIR_FLAG (1 << 5)
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| 161 | #define AMDM37x_GPT_TWPS_TNIR_FLAG (1 << 6)
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| 162 | #define AMDM37x_GPT_TWPS_TCVR_FLAG (1 << 7)
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| 163 | #define AMDM37x_GPT_TWPS_TOCR_FLAG (1 << 8)
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| 164 | #define AMDM37x_GPT_TWPS_TOWR_FLAG (1 << 9)
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| 165 |
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| 166 | /** Timer match register */
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| 167 | ioport32_t tmar;
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| 168 |
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| 169 | /** Capture value 1 register */
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| 170 | const ioport32_t tcar1;
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| 171 |
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| 172 | /** Software interface control register */
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| 173 | ioport32_t tsicr;
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| 174 | #define AMDM37x_GPT_TSICR_SFT_FLAG (1 << 1)
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| 175 | #define AMDM37x_GPT_TSICR_POSTED_FLAG (1 << 2)
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| 176 |
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| 177 | /** Capture value 2 register */
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| 178 | const ioport32_t tcar2;
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| 179 |
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| 180 | /* GPT1,2,10 only (used for 1ms time period generation)*/
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| 181 |
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| 182 | /** Positive increment register */
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| 183 | ioport32_t tpir;
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| 184 |
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| 185 | /** Negative increment register */
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| 186 | ioport32_t tnir;
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| 187 |
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| 188 | /** Counter value register */
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| 189 | ioport32_t tcvr;
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| 190 |
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| 191 | /** Mask the tick interrupt for selected number of ticks */
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| 192 | ioport32_t tocr;
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| 193 |
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| 194 | /** Number of masked overflow interrupts */
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| 195 | ioport32_t towr;
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| 196 | } amdm37x_gpt_regs_t;
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| 197 |
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| 198 | typedef struct {
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| 199 | amdm37x_gpt_regs_t *regs;
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| 200 | bool special_available;
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| 201 | } amdm37x_gpt_t;
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| 202 |
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| 203 | static inline void amdm37x_gpt_timer_ticks_init(
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| 204 | amdm37x_gpt_t* timer, uintptr_t ioregs, size_t iosize, unsigned hz)
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| 205 | {
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| 206 | /* Set 32768 Hz clock as source */
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| 207 | // TODO find a nicer way to setup 32kHz clock source for timer1
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| 208 | // reg 0x48004C40 is CM_CLKSEL_WKUP see page 485 of the manual
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| 209 | ioport32_t *clksel = (void*) km_map(0x48004C40, 4, PAGE_NOT_CACHEABLE);
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| 210 | *clksel &= ~1;
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| 211 | km_unmap((uintptr_t)clksel, 4);
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| 212 |
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| 213 | ASSERT(timer);
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| 214 | /* Map control register */
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| 215 | timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
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| 216 |
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| 217 | /* Reset the timer */
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| 218 | timer->regs->tiocp_cfg |= AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG;
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| 219 |
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| 220 | while (timer->regs->tistat & AMDM37x_GPT_TISTAT_RESET_DONE_FLAG);
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| 221 |
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| 222 | /* Set autoreload */
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| 223 | timer->regs->tclr |= AMDM37x_GPT_TCLR_AR_FLAG;
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| 224 |
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| 225 | timer->special_available = (
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| 226 | (ioregs == AMDM37x_GPT1_BASE_ADDRESS) ||
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| 227 | (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
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| 228 | (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
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| 229 | /* Select reload value */
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| 230 | timer->regs->tldr = 0xffffffff - (32768 / hz) + 1;
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| 231 | /* Set current counter value */
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| 232 | timer->regs->tccr = 0xffffffff - (32768 / hz) + 1;
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| 233 |
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| 234 | if (timer->special_available) {
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| 235 | /* Set values according to formula (manual p. 2733) */
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| 236 | /* Use temporary variables for easier debugging */
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| 237 | const uint32_t tpir =
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| 238 | ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz));
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| 239 | const uint32_t tnir =
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| 240 | ((32768 / hz) * 1000000) - (32768000L * (1000 / hz));
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| 241 | timer->regs->tpir = tpir;
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| 242 | timer->regs->tnir = tnir;
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| 243 | }
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| 244 |
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| 245 | }
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| 246 |
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| 247 | static inline void amdm37x_gpt_timer_ticks_start(amdm37x_gpt_t* timer)
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| 248 | {
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| 249 | ASSERT(timer);
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| 250 | ASSERT(timer->regs);
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| 251 | /* Enable overflow interrupt */
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| 252 | timer->regs->tier |= AMDM37x_GPT_TIER_OVF_IRQ_FLAG;
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| 253 | /* Start timer */
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| 254 | timer->regs->tclr |= AMDM37x_GPT_TCLR_ST_FLAG;
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| 255 | }
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| 256 |
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| 257 | static inline bool amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
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| 258 | {
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| 259 | ASSERT(timer);
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| 260 | ASSERT(timer->regs);
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| 261 | /* Clear all pending interrupts */
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| 262 | const uint32_t tisr = timer->regs->tisr;
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| 263 | timer->regs->tisr = tisr;
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| 264 | return tisr != 0;
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| 265 | }
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| 266 |
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| 267 | #endif
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| 268 |
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| 269 | /**
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| 270 | * @}
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| 271 | */
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