source: mainline/kernel/genarch/include/drivers/via-cuda/cuda.h@ 450448d

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 450448d was 450448d, checked in by Jiri Svoboda <jirik.svoboda@…>, 16 years ago

Implement data transmission to CUDA, use to enable autopolling. Now the driver works both in PearPC and Qemu -M g3beige.

  • Property mode set to 100644
File size: 2.7 KB
Line 
1/*
2 * Copyright (c) 2006 Martin Decky
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @addtogroup genarch
30 * @{
31 */
32/** @file
33 */
34
35#ifndef KERN_CUDA_H_
36#define KERN_CUDA_H_
37
38#include <ddi/irq.h>
39#include <arch/types.h>
40#include <console/chardev.h>
41#include <synch/spinlock.h>
42
43typedef struct {
44 uint8_t b;
45 uint8_t pad0[0x1ff];
46
47 uint8_t a;
48 uint8_t pad1[0x1ff];
49
50 uint8_t dirb;
51 uint8_t pad2[0x1ff];
52
53 uint8_t dira;
54 uint8_t pad3[0x1ff];
55
56 uint8_t t1cl;
57 uint8_t pad4[0x1ff];
58
59 uint8_t t1ch;
60 uint8_t pad5[0x1ff];
61
62 uint8_t t1ll;
63 uint8_t pad6[0x1ff];
64
65 uint8_t t1lh;
66 uint8_t pad7[0x1ff];
67
68 uint8_t t2cl;
69 uint8_t pad8[0x1ff];
70
71 uint8_t t2ch;
72 uint8_t pad9[0x1ff];
73
74 uint8_t sr;
75 uint8_t pad10[0x1ff];
76
77 uint8_t acr;
78 uint8_t pad11[0x1ff];
79
80 uint8_t pcr;
81 uint8_t pad12[0x1ff];
82
83 uint8_t ifr;
84 uint8_t pad13[0x1ff];
85
86 uint8_t ier;
87 uint8_t pad14[0x1ff];
88
89 uint8_t anh;
90 uint8_t pad15[0x1ff];
91} cuda_t;
92
93enum {
94 CUDA_RCV_BUF_SIZE = 5
95};
96
97enum cuda_xfer_state {
98 cx_listen,
99 cx_receive,
100 cx_rcv_end,
101 cx_send_start,
102 cx_send
103};
104
105typedef struct {
106 irq_t irq;
107 cuda_t *cuda;
108 indev_t *kbrdin;
109 uint8_t rcv_buf[CUDA_RCV_BUF_SIZE];
110 uint8_t snd_buf[CUDA_RCV_BUF_SIZE];
111 size_t bidx;
112 size_t snd_bytes;
113 enum cuda_xfer_state xstate;
114 SPINLOCK_DECLARE(dev_lock);
115} cuda_instance_t;
116
117extern cuda_instance_t *cuda_init(cuda_t *, inr_t, cir_t, void *);
118extern void cuda_wire(cuda_instance_t *, indev_t *);
119
120#endif
121
122/** @}
123 */
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