| 1 | /*
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| 2 | * Copyright (c) 2012 Jan Vesely
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| 3 | * All rights reserved.
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| 4 | *
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| 5 | * Redistribution and use in source and binary forms, with or without
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| 6 | * modification, are permitted provided that the following conditions
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| 7 | * are met:
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| 8 | *
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| 9 | * - Redistributions of source code must retain the above copyright
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| 10 | * notice, this list of conditions and the following disclaimer.
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| 11 | * - Redistributions in binary form must reproduce the above copyright
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| 12 | * notice, this list of conditions and the following disclaimer in the
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| 13 | * documentation and/or other materials provided with the distribution.
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| 14 | * - The name of the author may not be used to endorse or promote products
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| 15 | * derived from this software without specific prior written permission.
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| 16 | *
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| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 | /** @addtogroup genarch
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| 29 | * @{
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| 30 | */
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| 31 | /**
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| 32 | * @file
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| 33 | * @brief Texas Instruments AMDM37x UART memory mapped registers.
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| 34 | */
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| 35 |
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| 36 | #ifndef KERN_AMDM37x_UART_H_
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| 37 | #define KERN_AMDM37x_UART_H_
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| 38 |
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| 39 | #include <typedefs.h>
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| 40 | #include <console/chardev.h>
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| 41 | #include <ddi/irq.h>
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| 42 |
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| 43 | typedef struct {
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| 44 | union {
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| 45 | /** Stores lower part of the 14-bit baud divisor */
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| 46 | ioport32_t dll;
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| 47 | #define AMDM37x_UART_DLL_MASK (0xff)
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| 48 |
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| 49 | /** Receive holding register */
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| 50 | const ioport32_t rhr;
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| 51 | #define AMDM37x_UART_RHR_MASK (0xff)
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| 52 |
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| 53 | /** Transmit holding register */
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| 54 | ioport32_t thr;
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| 55 | #define AMDM37x_UART_THR_MASK (0xff)
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| 56 | };
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| 57 |
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| 58 | union {
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| 59 | /** Stores higher part of the 14-bit baud divisor */
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| 60 | ioport32_t dlh;
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| 61 | #define AMDM37x_UART_DLH_MASK (0x1f)
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| 62 |
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| 63 | /** Interrupt enable registers */
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| 64 | ioport32_t ier;
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| 65 | #define AMDM37x_UART_IER_RHR_IRQ_FLAG (1 << 0)
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| 66 | #define AMDM37x_UART_IER_THR_IRQ_FLAG (1 << 1)
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| 67 | #define AMDM37x_UART_IER_LINE_STS_IRQ_FLAG (1 << 2)
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| 68 | #define AMDM37x_UART_IER_MODEM_STS_IRQ_FLAG (1 << 3)
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| 69 | #define AMDM37x_UART_IER_SLEEP_MODE_FLAG (1 << 4)
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| 70 | #define AMDM37x_UART_IER_XOFF_IRQ_FLAG (1 << 5)
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| 71 | #define AMDM37x_UART_IER_RTS_IRQ_FLAG (1 << 6)
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| 72 | #define AMDM37x_UART_IER_CTS_IRQ_FLAG (1 << 7)
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| 73 |
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| 74 | #define AMDM37x_CIR_IER_RHR_IRQ_FLAG (1 << 0)
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| 75 | #define AMDM37x_CIR_IER_THR_IRQ_FLAG (1 << 1)
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| 76 | #define AMDM37x_CIR_IER_RX_STOP_IRQ_FLAG (1 << 2)
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| 77 | #define AMDM37x_CIR_IER_RX_OVERRUN_IRQ_FLAG (1 << 3)
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| 78 | #define AMDM37x_CIR_IER_TX_STS_IRQ_FLAG (1 << 5)
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| 79 |
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| 80 | #define AMDM37x_IRDA_IER_RHR_IRQ_FLAG (1 << 0)
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| 81 | #define AMDM37x_IRDA_IER_THR_IRQ_FLAG (1 << 1)
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| 82 | #define AMDM37x_IRDA_IER_LAST_RX_BYTE_IRQ_FLAG (1 << 2)
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| 83 | #define AMDM37x_IRDA_IER_RX_OVERRUN_IRQ_FLAG (1 << 3)
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| 84 | #define AMDM37x_IRDA_IER_STS_FIFO_TRIG_IRQ_FLAG (1 << 4)
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| 85 | #define AMDM37x_IRDA_IER_TX_STS_IRQ_FLAG (1 << 5)
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| 86 | #define AMDM37x_IRDA_IER_LINE_STS_IRQ_FLAG (1 << 6)
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| 87 | #define AMDM37x_IRDA_IER_EOF_IRQ_FLAG (1 << 7)
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| 88 | };
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| 89 |
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| 90 | union {
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| 91 | /** Interrupt identification register */
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| 92 | const ioport32_t iir;
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| 93 | #define AMDM37x_UART_IIR_IRQ_PENDING_FLAG (1 << 0)
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| 94 | #define AMDM37x_UART_IIR_TYPE_MASK (0x1f)
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| 95 | #define AMDM37x_UART_IIR_TYPE_SHIFT (1)
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| 96 | #define AMDM37x_UART_IIR_FCR_MASK (0x3)
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| 97 | #define AMDM37x_UART_IIR_FCR_SHIFT (6)
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| 98 |
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| 99 | #define AMDM37x_CIR_IIR_RHR_IRQ_FLAG (1 << 0)
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| 100 | #define AMDM37x_CIR_IIR_THR_IRQ_FLAG (1 << 1)
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| 101 | #define AMDM37x_CIR_IIR_RX_STOP_IRQ_FLAG (1 << 2)
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| 102 | #define AMDM37x_CIR_IIR_RX_OE_IRQ_FLAG (1 << 3)
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| 103 | #define AMDM37x_CIR_IIR_TX_STS_IRQ_FLAG (1 << 5)
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| 104 |
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| 105 | #define AMDM37x_IRDA_IIR_RHR_IRQ_FLAG (1 << 0)
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| 106 | #define AMDM37x_IRDA_IIR_THR_IRQ_FLAG (1 << 1)
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| 107 | #define AMDM37x_IRDA_IIR_RX_FIFO_LB_IRQ_FLAG (1 << 2)
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| 108 | #define AMDM37x_IRDA_IIR_RX_OE_IRQ_FLAG (1 << 3)
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| 109 | #define AMDM37x_IRDA_IIR_STS_FIFO_IRQ_FLAG (1 << 4)
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| 110 | #define AMDM37x_IRDA_IIR_TX_STS_IRQ_FLAG (1 << 5)
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| 111 | #define AMDM37x_IRDA_IIR_LINE_STS_IRQ_FLAG (1 << 6)
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| 112 | #define AMDM37x_IRDA_IIR_EOF_IRQ_FLAG (1 << 7)
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| 113 |
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| 114 | /** FIFO control register */
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| 115 | ioport32_t fcr;
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| 116 | #define AMDM37x_UART_FCR_FIFO_EN_FLAG (1 << 0)
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| 117 | #define AMDM37x_UART_FCR_RX_FIFO_CLR_FLAG (1 << 1)
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| 118 | #define AMDM37x_UART_FCR_TX_FIFO_CLR_FLAG (1 << 3)
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| 119 | #define AMDM37x_UART_FCR_DMA_MODE_FLAG (1 << 4)
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| 120 |
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| 121 | #define AMDM37x_UART_FCR_TX_FIFO_TRIG_MASK (0x3)
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| 122 | #define AMDM37x_UART_FCR_TX_FIFO_TRIG_SHIFT (4)
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| 123 |
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| 124 | #define AMDM37x_UART_FCR_RX_FIFO_TRIG_MASK (0x3)
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| 125 | #define AMDM37x_UART_FCR_RX_FIFO_TRIG_SHIFT (6)
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| 126 |
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| 127 | /** Enhanced feature register */
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| 128 | ioport32_t efr;
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| 129 | #define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_MASK (0x3)
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| 130 | #define AMDM37x_UART_EFR_SW_FLOW_CTRL_RX_SHIFT (0)
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| 131 | #define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_MASK (0x3)
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| 132 | #define AMDM37x_UART_EFR_SW_FLOW_CTRL_TX_SHIFT (2)
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| 133 |
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| 134 | #define AMDM37x_UART_EFR_SW_FLOW_CTRL_NONE (0x0)
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| 135 | #define AMDM37x_UART_EFR_SW_FLOW_CTRL_X2 (0x1)
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| 136 | #define AMDM37x_UART_EFR_SW_FLOW_CTRL_X1 (0x2)
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| 137 | #define AMDM37x_UART_EFR_SW_FLOW_CTRL_XBOTH (0x3)
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| 138 |
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| 139 | #define AMDM37x_UART_EFR_ENH_FLAG (1 << 4)
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| 140 | #define AMDM37x_UART_EFR_SPEC_CHAR_FLAG (1 << 5)
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| 141 | #define AMDM37x_UART_EFR_AUTO_RTS_EN_FLAG (1 << 6)
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| 142 | #define AMDM37x_UART_EFR_AUTO_CTS_EN_FLAG (1 << 7)
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| 143 | };
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| 144 |
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| 145 | /** Line control register */
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| 146 | ioport32_t lcr;
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| 147 | #define AMDM37x_UART_LCR_CHAR_LENGTH_MASK (0x3)
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| 148 | #define AMDM37x_UART_LCR_CHAR_LENGTH_SHIFT (0)
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| 149 | #define AMDM37x_UART_LCR_CHAR_LENGTH_5BITS (0x0)
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| 150 | #define AMDM37x_UART_LCR_CHAR_LENGTH_6BITS (0x1)
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| 151 | #define AMDM37x_UART_LCR_CHAR_LENGTH_7BITS (0x2)
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| 152 | #define AMDM37x_UART_LCR_CHAR_LENGTH_8BITS (0x3)
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| 153 | #define AMDM37x_UART_LCR_NB_STOP_FLAG (1 << 2)
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| 154 | #define AMDM37x_UART_LCR_PARITY_EN_FLAG (1 << 3)
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| 155 | #define AMDM37x_UART_LCR_PARITY_TYPE1_FLAG (1 << 4)
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| 156 | #define AMDM37x_UART_LCR_PARITY_TYPE2_FLAG (1 << 5)
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| 157 | #define AMDM37x_UART_LCR_BREAK_EN_FLAG (1 << 6)
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| 158 | #define AMDM37x_UART_LCR_DIV_EN_FLAG (1 << 7)
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| 159 |
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| 160 |
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| 161 | union {
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| 162 | /** Modem control register */
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| 163 | ioport32_t mcr;
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| 164 | #define AMDM37x_UART_MCR_DTR_FLAG (1 << 0)
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| 165 | #define AMDM37x_UART_MCR_RTS_FLAG (1 << 1)
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| 166 | #define AMDM37x_UART_MCR_RI_STS_CH_FLAG (1 << 2)
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| 167 | #define AMDM37x_UART_MCR_CD_STS_CH_FLAG (1 << 3)
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| 168 | #define AMDM37x_UART_MCR_LOOPBACK_EN_FLAG (1 << 4)
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| 169 | #define AMDM37x_UART_MCR_XON_EN_FLAG (1 << 5)
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| 170 | #define AMDM37x_UART_MCR_TCR_TLR_FLAG (1 << 6)
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| 171 |
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| 172 | /** UART: XON1 char, IRDA: ADDR1 address */
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| 173 | ioport32_t xon1_addr1;
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| 174 | #define AMDM37x_UART_XON1_ADDR1_MASK (0xff)
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| 175 | };
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| 176 |
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| 177 | union {
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| 178 | /** Line status register */
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| 179 | const ioport32_t lsr;
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| 180 | #define AMDM37x_UART_LSR_RX_FIFO_E_FLAG (1 << 0)
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| 181 | #define AMDM37x_UART_LSR_RX_OE_FLAG (1 << 1)
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| 182 | #define AMDM37x_UART_LSR_RX_PE_FLAG (1 << 2)
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| 183 | #define AMDM37x_UART_LSR_RX_FE_FLAG (1 << 3)
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| 184 | #define AMDM37x_UART_LSR_RX_BI_FLAG (1 << 4)
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| 185 | #define AMDM37x_UART_LSR_TX_FIFO_E_FLAG (1 << 5)
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| 186 | #define AMDM37x_UART_LSR_TX_SR_E_FLAG (1 << 6)
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| 187 | #define AMDM37x_UART_LSR_RX_FIFO_STS_FLAG (1 << 7)
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| 188 |
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| 189 | #define AMDM37x_CIR_LSR_RX_FIFO_E_FLAG (1 << 0)
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| 190 | #define AMDM37x_CIR_LSR_RX_STOP_FLAG (1 << 5)
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| 191 | #define AMDM37x_CIR_LSR_THR_EMPTY_FLAG (1 << 7)
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| 192 |
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| 193 | #define AMDM37x_IRDA_LSR_RX_FIFO_E_FLAG (1 << 0)
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| 194 | #define AMDM37x_IRDA_LSR_STS_FIFO_E_FLAG (1 << 1)
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| 195 | #define AMDM37x_IRDA_LSR_CRC_FLAG (1 << 2)
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| 196 | #define AMDM37x_IRDA_LSR_ABORT_FLAG (1 << 3)
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| 197 | #define AMDM37x_IRDA_LSR_FTL_FLAG (1 << 4)
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| 198 | #define AMDM37x_IRDA_LSR_RX_LAST_FLAG (1 << 5)
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| 199 | #define AMDM37x_IRDA_LSR_STS_FIFO_FULL_FLAG (1 << 6)
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| 200 | #define AMDM37x_IRDA_LSR_THR_EMPTY_FLAG (1 << 7)
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| 201 |
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| 202 | /** UART: XON2 char, IRDA: ADDR2 address */
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| 203 | ioport32_t xon2_addr2;
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| 204 | };
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| 205 |
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| 206 | union {
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| 207 | /** Modem status register */
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| 208 | const ioport32_t msr;
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| 209 | #define AMDM37x_UART_MSR_CTS_STS_FLAG (1 << 0)
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| 210 | #define AMDM37x_UART_MSR_DSR_STS_FLAG (1 << 1)
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| 211 | #define AMDM37x_UART_MSR_RI_STS_FLAG (1 << 2)
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| 212 | #define AMDM37x_UART_MSR_DCD_STS_FLAG (1 << 3)
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| 213 | #define AMDM37x_UART_MSR_NCTS_STS_FLAG (1 << 4)
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| 214 | #define AMDM37x_UART_MSR_NDSR_STS_FLAG (1 << 5)
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| 215 | #define AMDM37x_UART_MSR_NRI_STS_FLAG (1 << 6)
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| 216 | #define AMDM37x_UART_MSR_NCD_STS_FLAG (1 << 7)
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| 217 |
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| 218 | /** Transmission control register */
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| 219 | ioport32_t tcr;
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| 220 | #define AMDM37x_UART_TCR_FIFO_TRIG_MASK (0xf)
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| 221 | #define AMDM37x_UART_TCR_FIFO_TRIG_HALT_SHIFT (0)
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| 222 | #define AMDM37x_UART_TCR_FIFO_TRIG_START_SHIFT (4)
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| 223 |
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| 224 | /** UART: XOFF1 char */
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| 225 | ioport32_t xoff1;
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| 226 | #define AMDM37x_UART_XOFF1_MASK (0xff)
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| 227 | };
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| 228 |
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| 229 | union {
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| 230 | /* Scratchpad register, does nothing */
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| 231 | ioport32_t spr;
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| 232 | #define AMDM37x_UART_SPR_MASK (0xff)
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| 233 |
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| 234 | /* Trigger level register */
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| 235 | ioport32_t tlr;
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| 236 | #define AMDM37x_UART_TLR_LEVEL_MASK (0xf)
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| 237 | #define AMDM37x_UART_TLR_TX_FIFO_TRIG_SHIFT (0)
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| 238 | #define AMDM37x_UART_TLR_RX_FIFO_TRIG_SHIFT (4)
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| 239 |
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| 240 | /** UART: XOFF2 char */
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| 241 | ioport32_t xoff2;
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| 242 | #define AMDM37x_UART_XOFF2_MASK (0xff)
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| 243 | };
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| 244 |
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| 245 | /** Mode definition register. */
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| 246 | ioport32_t mdr1;
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| 247 | #define AMDM37x_UART_MDR_MS_MASK (0x7)
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| 248 | #define AMDM37x_UART_MDR_MS_SHIFT (0)
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| 249 | #define AMDM37x_UART_MDR_MS_UART16 (0x0)
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| 250 | #define AMDM37x_UART_MDR_MS_SIR (0x1)
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| 251 | #define AMDM37x_UART_MDR_MS_UART16_AUTO (0x2)
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| 252 | #define AMDM37x_UART_MDR_MS_UART13 (0x3)
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| 253 | #define AMDM37x_UART_MDR_MS_MIR (0x4)
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| 254 | #define AMDM37x_UART_MDR_MS_FIR (0x5)
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| 255 | #define AMDM37x_UART_MDR_MS_CIR (0x6)
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| 256 | #define AMDM37x_UART_MDR_MS_DISABLE (0x7)
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| 257 |
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| 258 | #define AMDM37x_UART_MDR_IR_SLEEP_FLAG (1 << 3)
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| 259 | #define AMDM37x_UART_MDR_SET_TXIR_FLAG (1 << 4)
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| 260 | #define AMDM37x_UART_MDR_SCT_FLAG (1 << 5)
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| 261 | #define AMDM37x_UART_MDR_SIP_FLAG (1 << 6)
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| 262 | #define AMDM37x_UART_MDR_FRAME_END_MODE_FLAG (1 << 7)
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| 263 |
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| 264 | /** Mode definition register */
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| 265 | ioport32_t mdr2;
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| 266 | #define AMDM37x_UART_MDR_IRTX_UNDERRUN_FLAG (1 << 0)
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| 267 | #define AMDM37x_UART_MDR_STS_FIFO_TRIG_MASK (0x3)
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| 268 | #define AMDM37x_UART_MDR_STS_FIFO_TRIG_SHIFT (1)
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| 269 | #define AMDM37x_UART_MDR_PULSE_SHAPING_FLAG (1 << 3)
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| 270 | #define AMDM37x_UART_MDR_CIR_PULSE_MODE_MASK (0x3)
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| 271 | #define AMDM37x_UART_MDR_CIR_PULSE_MODE_SHIFT (4)
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| 272 | #define AMDM37x_UART_MDR_IRRXINVERT_FLAG (1 << 6)
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| 273 |
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| 274 |
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| 275 | /* UART3 specific */
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| 276 | union {
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| 277 | /** Status FIFO line status register (IrDA only) */
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| 278 | const ioport32_t sflsr;
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| 279 | #define AMDM37x_IRDA_SFLSR_CRC_ERROR_FLAG (1 << 1)
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| 280 | #define AMDM37x_IRDA_SFLSR_ABORT_FLAG (1 << 2)
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| 281 | #define AMDM37x_IRDA_SFLSR_FTL_FLAG (1 << 3)
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| 282 | #define AMDM37x_IRDA_SFLSR_OE_FLAG (1 << 4)
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| 283 |
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| 284 | /** Transmit frame length low (IrDA only) */
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| 285 | ioport32_t txfll;
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| 286 | #define AMDM37x_UART_TXFLL_MASK (0xff)
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| 287 | };
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| 288 |
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| 289 | /* UART3 specific */
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| 290 | union {
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| 291 | /** Dummy register to restart TX or RX (IrDA only) */
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| 292 | const ioport32_t resume;
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| 293 | /** Transmit frame length high (IrDA only) */
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| 294 | ioport32_t txflh;
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| 295 | #define AMDM37x_UART_TXFLH_MASK (0xff)
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| 296 | };
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| 297 |
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| 298 | /* UART3 specific */
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| 299 | union {
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| 300 | /** Status FIFO register low (IrDA only) */
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| 301 | const ioport32_t sfregl;
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| 302 | #define AMDM37x_UART_SFREGL_MASK (0xff)
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| 303 | /** Received frame length low (IrDA only) */
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| 304 | ioport32_t rxfll;
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| 305 | #define AMDM37x_UART_RXFLL_MASK (0xff)
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| 306 | };
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| 307 |
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| 308 | /* UART3 specific */
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| 309 | union {
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| 310 | /** Status FIFO register high (IrDA only) */
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| 311 | const ioport32_t sfregh;
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| 312 | #define AMDM37x_UART_SFREGH_MASK (0xf)
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| 313 | /** Received frame length high (IrDA only) */
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| 314 | ioport32_t rxflh;
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| 315 | #define AMDM37x_UART_RXFLH_MASK (0xf)
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| 316 | };
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| 317 |
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| 318 | union {
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| 319 | /** UART autobauding status register */
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| 320 | const ioport32_t uasr;
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| 321 | #define AMDM37x_UART_UASR_SPEED_MASK (0x1f)
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| 322 | #define AMDM37x_UART_UASR_SPEED_SHIFT (0)
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| 323 | #define AMDM37x_UART_UASR_8BIT_CHAR_FLAG (1 << 5)
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| 324 | #define AMDM37x_UART_UASR_PARITY_MASK (0x3)
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| 325 | #define AMDM37x_UART_UASR_PARITY_SHIFT (6)
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| 326 |
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| 327 | /** BOF control register (IrDA only) */
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| 328 | ioport32_t blr; /* UART3 specific */
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| 329 | #define AMDM37x_IRDA_BLR_XBOF_TYPE_FLAG (1 << 6)
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| 330 | #define AMDM37x_IRDA_BLR_STS_FIFO_RESET (1 << 7)
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| 331 | };
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| 332 |
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| 333 | /** Auxiliary control register (IrDA only) */
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| 334 | ioport32_t acreg; /* UART3 specific */
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| 335 | #define AMDM37x_IRDA_ACREG_EOT_EN_FLAG (1 << 0)
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| 336 | #define AMDM37x_IRDA_ACREG_ABORT_EN_FLAG (1 << 1)
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| 337 | #define AMDM37x_IRDA_ACREG_SCTX_EN_FLAG (1 << 2)
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| 338 | #define AMDM37x_IRDA_ACREG_SEND_SIP_FLAG (1 << 3)
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| 339 | #define AMDM37x_IRDA_ACREG_DIS_TX_UNDERRUN_FLAG (1 << 4)
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| 340 | #define AMDM37x_IRDA_ACREG_DIS_IR_RX_FLAG (1 << 5)
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| 341 | #define AMDM37x_IRDA_ACREG_SD_MOD_FLAG (1 << 6)
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| 342 | #define AMDM37x_IRDA_ACREG_PULSE_TYPE_FLAG (1 << 7)
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| 343 |
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| 344 | /** Supplementary control register */
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| 345 | ioport32_t scr;
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| 346 | #define AMDM37x_UART_SCR_DMA_MODE_CTL_FLAG (1 << 0)
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| 347 | #define AMDM37x_UART_SCR_DMA_MODE_MASK (0x3)
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| 348 | #define AMDM37x_UART_SCR_DMA_MODE_SHIFT (1)
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| 349 | #define AMDM37x_UART_SCR_TX_EMPTY_CTL_IRQ_FLAG (1 << 3)
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| 350 | #define AMDM37x_UART_SCR_RX_CTS_WU_EN_FLAG (1 << 4)
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| 351 | #define AMDM37x_UART_SCR_TX_TRIG_GRANU1_FLAG (1 << 6)
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| 352 | #define AMDM37x_UART_SCR_RX_TRIG_GRANU1_FLAG (1 << 7)
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| 353 |
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| 354 | /** Supplementary status register */
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| 355 | const ioport32_t ssr;
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| 356 | #define AMDM37x_UART_SSR_TX_FIFO_FULL_FLAG (1 << 0)
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| 357 | #define AMDM37x_UART_SSR_RX_CTS_WU_STS_FLAG (1 << 1)
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| 358 | #define AMDM37x_UART_SSR_DMA_COUNTER_RESET_FLAG (1 << 2)
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| 359 |
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| 360 | /** BOF Length register (IrDA only)*/
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| 361 | ioport32_t eblr; /* UART3 specific */
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| 362 | #define AMDM37x_IRDA_EBLR_DISABLED (0x00)
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| 363 | #define AMDM37x_IRDA_EBLR_RX_STOP_BITS(bits) (bits & 0xff)
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| 364 |
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| 365 | uint32_t padd0_;
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| 366 |
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| 367 | /** Module version register */
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| 368 | const ioport32_t mvr;
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| 369 | #define AMDM37x_UART_MVR_MINOR_MASK (0xf)
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| 370 | #define AMDM37x_UART_MVR_MINOR_SHIFT (0)
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| 371 | #define AMDM37x_UART_MVR_MAJOR_MASK (0xf)
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| 372 | #define AMDM37x_UART_MVR_MAJOR_SHIFT (4)
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| 373 |
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| 374 | /** System configuration register */
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| 375 | ioport32_t sysc;
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| 376 | #define AMDM37x_UART_SYSC_AUTOIDLE_FLAG (1 << 0)
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| 377 | #define AMDM37x_UART_SYSC_SOFTRESET_FLAG (1 << 1)
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| 378 | #define AMDM37x_UART_SYSC_ENWAKEUP_FLAG (1 << 2)
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| 379 | #define AMDM37x_UART_SYSC_IDLE_MODE_MASK (0x3)
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| 380 | #define AMDM37x_UART_SYSC_IDLE_MODE_SHIFT (3)
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| 381 | #define AMDM37x_UART_SYSC_IDLE_MODE_FORCE (0x0)
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| 382 | #define AMDM37x_UART_SYSC_IDLE_MODE_NO (0x1)
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| 383 | #define AMDM37x_UART_SYSC_IDLE_MODE_SMART (0x2)
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| 384 |
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| 385 | /** System status register */
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| 386 | const ioport32_t syss;
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| 387 | #define AMDM37x_UART_SYSS_RESETDONE_FLAG (1 << 0)
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| 388 |
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| 389 | /** Wake-up enable register */
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| 390 | ioport32_t wer;
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| 391 | #define AMDM37x_UART_WER_CTS_ACTIVITY_FLAG (1 << 0)
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| 392 | #define AMDM37x_UART_WER_RI_ACTIVITY_FLAG (1 << 2)
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| 393 | #define AMDM37x_UART_WER_RX_ACTIVITY_FLAG (1 << 4)
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| 394 | #define AMDM37x_UART_WER_RHR_IRQ_FLAG (1 << 5)
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| 395 | #define AMDM37x_UART_WER_RLS_IRQ_FLAG (1 << 6)
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| 396 | #define AMDM37x_UART_WER_TX_WAKEUP_EN_FLAG (1 << 7)
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| 397 |
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| 398 | /** Carrier frequency prescaler */
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| 399 | ioport32_t cfps; /* UART3 specific */
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| 400 | #define AMDM37x_UART_CFPS_MASK (0xff)
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| 401 |
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| 402 | /** Number of bytes in RX fifo */
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| 403 | const ioport32_t rx_fifo_lvl;
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| 404 | #define AMDM37x_UART_RX_FIFO_LVL_MASK (0xff)
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| 405 |
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| 406 | /** Number of bytes in TX fifo */
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| 407 | const ioport32_t tx_fifo_lvl;
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| 408 | #define AMDM37x_UART_TX_FIFO_LVL_MASK (0xff)
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| 409 |
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| 410 | /** RX/TX empty interrupts */
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| 411 | ioport32_t ier2;
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| 412 | #define AMDM37x_UART_IER2_RX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 0)
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| 413 | #define AMDM37x_UART_IER2_TX_FIFO_EMPTY_IRQ_EN_FLAG (1 << 1)
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| 414 |
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| 415 | /** RX/TX empty status */
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| 416 | ioport32_t isr2;
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| 417 | #define AMDM37x_UART_ISR2_RX_FIFO_EMPTY_FLAG (1 << 0)
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| 418 | #define AMDM37x_UART_ISR2_TX_FIFO_EMPTY_FLAG (1 << 1)
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| 419 |
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| 420 | uint32_t padd2_[3];
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| 421 |
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| 422 | /** Mode definition register 3 */
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| 423 | ioport32_t mdr3;
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| 424 | #define AMDM37x_UART_MDR3_DIS_CIR_RX_DEMOD_FLAG (1 << 0)
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| 425 | } amdm37x_uart_regs_t;
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| 426 |
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| 427 | #endif
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| 428 |
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| 429 | /**
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| 430 | * @}
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| 431 | */
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