source: mainline/kernel/genarch/include/drivers/amdm37x/gpt.h@ 4c754f6

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since 4c754f6 was 0fb70e1, checked in by Maurizio Lombardi <m.lombardi85@…>, 13 years ago

kernel drivers directory layout reorganization and UART improvements:

  • Put AM335x and AMDM37 specific code under the appropriate directories.

Beaglebone specific changes:

  • Initialize the UART0 when bbone_init() is called.
  • Property mode set to 100644
File size: 8.0 KB
Line 
1/*
2 * Copyright (c) 2012 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup genarch
29 * @{
30 */
31/**
32 * @file
33 * @brief Texas Instruments AM/DM37x MPU general purpose timer driver.
34 */
35
36#ifndef KERN_AMDM37x_GPT_H_
37#define KERN_AMDM37x_GPT_H_
38
39#include <typedefs.h>
40#include <mm/km.h>
41
42/* AMDM37x TRM p. 2740 */
43#define AMDM37x_GPT1_BASE_ADDRESS 0x48318000
44#define AMDM37x_GPT1_SIZE 4096
45#define AMDM37x_GPT1_IRQ 37
46#define AMDM37x_GPT2_BASE_ADDRESS 0x49032000
47#define AMDM37x_GPT2_SIZE 4096
48#define AMDM37x_GPT2_IRQ 38
49#define AMDM37x_GPT3_BASE_ADDRESS 0x49034000
50#define AMDM37x_GPT3_SIZE 4096
51#define AMDM37x_GPT3_IRQ 39
52#define AMDM37x_GPT4_BASE_ADDRESS 0x49036000
53#define AMDM37x_GPT4_SIZE 4096
54#define AMDM37x_GPT4_IRQ 40
55#define AMDM37x_GPT5_BASE_ADDRESS 0x49038000
56#define AMDM37x_GPT5_SIZE 4096
57#define AMDM37x_GPT5_IRQ 41
58#define AMDM37x_GPT6_BASE_ADDRESS 0x4903a000
59#define AMDM37x_GPT6_SIZE 4096
60#define AMDM37x_GPT6_IRQ 42
61#define AMDM37x_GPT7_BASE_ADDRESS 0x4903c000
62#define AMDM37x_GPT7_SIZE 4096
63#define AMDM37x_GPT7_IRQ 43
64#define AMDM37x_GPT8_BASE_ADDRESS 0x4903e000
65#define AMDM37x_GPT8_SIZE 4096
66#define AMDM37x_GPT8_IRQ 44
67#define AMDM37x_GPT9_BASE_ADDRESS 0x49040000
68#define AMDM37x_GPT9_SIZE 4096
69#define AMDM37x_GPT9_IRQ 45
70#define AMDM37x_GPT10_BASE_ADDRESS 0x48086000
71#define AMDM37x_GPT10_SIZE 4096
72#define AMDM37x_GPT10_IRQ 46
73#define AMDM37x_GPT11_BASE_ADDRESS 0x48088000
74#define AMDM37x_GPT11_SIZE 4096
75#define AMDM37x_GPT11_IRQ 47
76
77
78/** GPT register map AMDM37x TRM p. 2740 */
79typedef struct {
80 /** IP revision */
81 const ioport32_t tidr;
82#define AMDM37x_GPT_TIDR_MINOR_MASK (0xf)
83#define AMDM37x_GPT_TIDR_MINOR_SHIFT (0)
84#define AMDM37x_GPT_TIDR_MAJOR_MASK (0xf)
85#define AMDM37x_GPT_TIDR_MAJOR_SHIFT (4)
86 uint32_t padd0_[3];
87
88 /** L4 Interface parameters */
89 ioport32_t tiocp_cfg;
90#define AMDM37x_GPT_TIOCP_CFG_AUTOIDLE_FLAG (1 << 0)
91#define AMDM37x_GPT_TIOCP_CFG_SOFTRESET_FLAG (1 << 1)
92#define AMDM37x_GPT_TIOCP_CFG_ENWAKEUP_FLAG (1 << 2)
93#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_MASK (0x3)
94#define AMDM37x_GPT_TIOCP_CFG_IDLEMODE_SHIFT (3)
95#define AMDM37x_GPT_TIOCP_CFG_EMUFREE_FlAG (1 << 5)
96#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_MASK (0x3)
97#define AMDM37x_GPT_TIOCP_CFG_CLOCKACTIVITY_SHIFT (8)
98
99 /** Module status information, excluding irq */
100 const ioport32_t tistat;
101#define AMDM37x_GPT_TISTAT_RESET_DONE_FLAG (1 << 0)
102
103 /** Interrupt status register */
104 ioport32_t tisr;
105#define AMDM37x_GPT_TISR_MAT_IRQ_FLAG (1 << 0)
106#define AMDM37x_GPT_TISR_OVF_IRQ_FLAG (1 << 1)
107#define AMDM37x_GPT_TISR_TCAR_IRQ_FLAG (1 << 2)
108
109 /* Interrupt enable register */
110 ioport32_t tier;
111#define AMDM37x_GPT_TIER_MAT_IRQ_FLAG (1 << 0)
112#define AMDM37x_GPT_TIER_OVF_IRQ_FLAG (1 << 1)
113#define AMDM37x_GPT_TIER_TCAR_IRQ_FLAG (1 << 2)
114
115 /** Wakeup enable register */
116 ioport32_t twer;
117#define AMDM37x_GPT_TWER_MAT_IRQ_FLAG (1 << 0)
118#define AMDM37x_GPT_TWER_OVF_IRQ_FLAG (1 << 1)
119#define AMDM37x_GPT_TWER_TCAR_IRQ_FLAG (1 << 2)
120
121 /** Optional features control register */
122 ioport32_t tclr;
123#define AMDM37x_GPT_TCLR_ST_FLAG (1 << 0)
124#define AMDM37x_GPT_TCLR_AR_FLAG (1 << 1)
125#define AMDM37x_GPT_TCLR_PTV_MASK (0x7)
126#define AMDM37x_GPT_TCLR_PTV_SHIFT (2)
127#define AMDM37x_GPT_TCLR_PRE_FLAG (1 << 5)
128#define AMDM37x_GPT_TCLR_CE_FLAG (1 << 6)
129#define AMDM37x_GPT_TCLR_SCPWM (1 << 7)
130#define AMDM37x_GPT_TCLR_TCM_MASK (0x3)
131#define AMDM37x_GPT_TCLR_TCM_SHIFT (8)
132#define AMDM37x_GPT_TCLR_TRG_MASK (0x3)
133#define AMDM37x_GPT_TCLR_TRG_SHIFT (10)
134#define AMDM37x_GPT_TCLR_PT_FLAG (1 << 12)
135#define AMDM37x_GPT_TCLR_CAPT_MODE_FLAG (1 << 13)
136#define AMDM37x_GPT_TCLR_GPO_CFG_FLAG (1 << 14)
137
138 /** Value of timer counter */
139 ioport32_t tccr;
140
141 /** Timer load register */
142 ioport32_t tldr;
143
144 /** Timer trigger register */
145 ioport32_t ttgr;
146
147 /** Write-posted pending register */
148 const ioport32_t twps;
149#define AMDM37x_GPT_TWPS_TCLR_FLAG (1 << 0)
150#define AMDM37x_GPT_TWPS_TCRR_FLAG (1 << 1)
151#define AMDM37x_GPT_TWPS_TLDR_FLAG (1 << 2)
152#define AMDM37x_GPT_TWPS_TTGR_FLAG (1 << 3)
153#define AMDM37x_GPT_TWPS_TMAR_FLAG (1 << 4)
154#define AMDM37x_GPT_TWPS_TPIR_FLAG (1 << 5)
155#define AMDM37x_GPT_TWPS_TNIR_FLAG (1 << 6)
156#define AMDM37x_GPT_TWPS_TCVR_FLAG (1 << 7)
157#define AMDM37x_GPT_TWPS_TOCR_FLAG (1 << 8)
158#define AMDM37x_GPT_TWPS_TOWR_FLAG (1 << 9)
159
160 /** Timer match register */
161 ioport32_t tmar;
162
163 /** Capture value 1 register */
164 const ioport32_t tcar1;
165
166 /** Software interface control register */
167 ioport32_t tsicr;
168#define AMDM37x_GPT_TSICR_SFT_FLAG (1 << 1)
169#define AMDM37x_GPT_TSICR_POSTED_FLAG (1 << 2)
170
171 /** Capture value 2 register */
172 const ioport32_t tcar2;
173
174 /* GPT1,2,10 only (used for 1ms time period generation)*/
175
176 /** Positive increment register */
177 ioport32_t tpir;
178
179 /** Negative increment register */
180 ioport32_t tnir;
181
182 /** Counter value register */
183 ioport32_t tcvr;
184
185 /** Mask the tick interrupt for selected number of ticks */
186 ioport32_t tocr;
187
188 /** Number of masked overflow interrupts */
189 ioport32_t towr;
190} amdm37x_gpt_regs_t;
191
192typedef struct {
193 amdm37x_gpt_regs_t *regs;
194 bool special_available;
195} amdm37x_gpt_t;
196
197static inline void amdm37x_gpt_timer_ticks_init(
198 amdm37x_gpt_t* timer, uintptr_t ioregs, size_t iosize, unsigned hz)
199{
200 /* Set 32768 Hz clock as source */
201 // TODO find a nicer way to setup 32kHz clock source for timer1
202 // reg 0x48004C40 is CM_CLKSEL_WKUP see page 485 of the manual
203 ioport32_t *clksel = (void*) km_map(0x48004C40, 4, PAGE_NOT_CACHEABLE);
204 *clksel &= ~1;
205 km_unmap((uintptr_t)clksel, 4);
206
207 ASSERT(timer);
208 /* Map control register */
209 timer->regs = (void*) km_map(ioregs, iosize, PAGE_NOT_CACHEABLE);
210
211 /* Set autoreload */
212 timer->regs->tclr = AMDM37x_GPT_TCLR_AR_FLAG;
213
214 timer->special_available = (
215 (ioregs == AMDM37x_GPT1_BASE_ADDRESS) ||
216 (ioregs == AMDM37x_GPT2_BASE_ADDRESS) ||
217 (ioregs == AMDM37x_GPT10_BASE_ADDRESS));
218 timer->regs->tldr = 0xffffffff - (32768 / hz) + 1;
219 timer->regs->tccr = 0xffffffff - (32768 / hz) + 1;
220 if (timer->special_available) {
221 /* Set values for according to formula (manual p. 2733) */
222 /* Use temporary variables for easier debugging */
223 const uint32_t tpir =
224 ((32768 / hz + 1) * 1000000) - (32768000L * (1000 / hz));
225 const uint32_t tnir =
226 ((32768 / hz) * 1000000) - (32768000 * (1000 / hz));
227 timer->regs->tpir = tpir;
228 timer->regs->tnir = tnir;
229 }
230
231}
232
233static inline void amdm37x_gpt_timer_ticks_start(amdm37x_gpt_t* timer)
234{
235 ASSERT(timer);
236 ASSERT(timer->regs);
237 /* Enable overflow interrupt */
238 timer->regs->tier |= AMDM37x_GPT_TIER_OVF_IRQ_FLAG;
239 /* Start timer */
240 timer->regs->tclr |= AMDM37x_GPT_TCLR_ST_FLAG;
241}
242
243static inline void amdm37x_gpt_irq_ack(amdm37x_gpt_t* timer)
244{
245 ASSERT(timer);
246 ASSERT(timer->regs);
247 /* Clear all pending interrupts */
248 timer->regs->tisr = timer->regs->tisr;
249}
250
251#endif
252
253/**
254 * @}
255 */
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