source: mainline/kernel/genarch/include/drivers/amdm37x/dispc.h@ b933ec2

lfn serial ticket/834-toolchain-update topic/msim-upgrade topic/simplify-dev-export
Last change on this file since b933ec2 was 0fb70e1, checked in by Maurizio Lombardi <m.lombardi85@…>, 13 years ago

kernel drivers directory layout reorganization and UART improvements:

  • Put AM335x and AMDM37 specific code under the appropriate directories.

Beaglebone specific changes:

  • Initialize the UART0 when bbone_init() is called.
  • Property mode set to 100644
File size: 14.2 KB
Line 
1/*
2 * Copyright (c) 2012 Jan Vesely
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * - Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * - Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * - The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28/** @addtogroup genarch
29 * @{
30 */
31/**
32 * @file
33 * @brief Texas Instruments AM/DM37x SDRAM Memory Scheduler.
34 */
35
36#ifndef KERN_AMDM37x_DISPC_H_
37#define KERN_AMDM37x_DISPC_H_
38
39/* AMDM37x TRM p. 1813 */
40#define AMDM37x_DISPC_BASE_ADDRESS 0x48050400
41#define AMDM37x_DISPC_SIZE 1024
42
43#define __paddname(line) PADD32_ ## line
44#define _paddname(line) __paddname(line)
45#define PADD32(count) uint32_t _paddname(__LINE__)[count]
46
47#include <typedefs.h>
48
49typedef struct {
50 const ioport32_t revision;
51#define AMDM37X_DISPC_REVISION_MASK 0xff
52
53 PADD32(3);
54 ioport32_t sysconfig;
55#define AMDM37X_DISPC_SYSCONFIG_AUTOIDLE_FLAG (1 << 0)
56#define AMDM37X_DISPC_SYSCONFIG_SOFTRESET_FLAG (1 << 1)
57#define AMDM37X_DISPC_SYSCONFIG_ENWAKEUP_FLAG (1 << 2)
58#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_MASK 0x3
59#define AMDM37X_DISPC_SYSCONFIG_SIDLEMODE_SHIFT 3
60#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_MASK 0x3
61#define AMDM37X_DISPC_SYSCONFIG_CLOCKACTIVITY_SHIFT 8
62#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_MASK 0x3
63#define AMDM37X_DISPC_SYSCONFIG_MIDLEMODE_SHIFT 12
64
65 const ioport32_t sysstatus;
66#define AMDM37X_DISPC_SYSSTATUS_RESETDONE_FLAG (1 << 0)
67
68 ioport32_t irqstatus;
69 ioport32_t irqenable;
70#define AMDM37X_DISPC_IRQ_FRAMEDONE_FLAG (1 << 0)
71#define AMDM37X_DISPC_IRQ_VSYNC_FLAG (1 << 1)
72#define AMDM37X_DISPC_IRQ_EVSYNCEVEN_FLAG (1 << 2)
73#define AMDM37X_DISPC_IRQ_EVSYNCODD_FLAG (1 << 3)
74#define AMDM37X_DISPC_IRQ_ACBIASCOUNTSTATUS_FLAG (1 << 4)
75#define AMDM37X_DISPC_IRQ_PROGRAMMEDLINENUMBER_FLAG (1 << 5)
76#define AMDM37X_DISPC_IRQ_GFXFIFOUNDERFLOW_FLAG (1 << 6)
77#define AMDM37X_DISPC_IRQ_GFXENDWINDOW_FLAG (1 << 7)
78#define AMDM37X_DISPC_IRQ_PALETTEGAMMALOADING_FLAG (1 << 8)
79#define AMDM37X_DISPC_IRQ_OPCERROR_FLAG (1 << 9)
80#define AMDM37X_DISPC_IRQ_VID1FIFOUNDERFLOW_FLAG (1 << 10)
81#define AMDM37X_DISPC_IRQ_VID1ENDWINDOW_FLAG (1 << 11)
82#define AMDM37X_DISPC_IRQ_VID2FIFOUNDERFLOW_FLAG (1 << 12)
83#define AMDM37X_DISPC_IRQ_VID2ENDWINDOW_FLAG (1 << 13)
84#define AMDM37X_DISPC_IRQ_SYNCLOST_FLAG (1 << 14)
85#define AMDM37X_DISPC_IRQ_SYNCLOSTDIGITAL_FLAG (1 << 15)
86#define AMDM37X_DISPC_IRQ_WAKEUP_FLAG (1 << 16)
87
88 PADD32(8);
89 ioport32_t control;
90#define AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG (1 << 0)
91#define AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG (1 << 1)
92#define AMDM37X_DISPC_CONTROL_MONOCOLOR_FLAG (1 << 2)
93#define AMDM37X_DISPC_CONTROL_STNTFT_FLAG (1 << 3)
94#define AMDM37X_DISPC_CONTROL_M8B_FLAG (1 << 4)
95#define AMDM37X_DISPC_CONTROL_GOLCD_FLAG (1 << 5)
96#define AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG (1 << 6)
97#define AMDM37X_DISPC_CONTROL_STDITHERENABLE_FLAG (1 << 7)
98#define AMDM37X_DISPC_CONTROL_TFTDATALINES_MASK 0x3
99#define AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT 8
100#define AMDM37X_DISPC_CONTROL_TFTDATALINES_12B 0
101#define AMDM37X_DISPC_CONTROL_TFTDATALINES_16B 1
102#define AMDM37X_DISPC_CONTROL_TFTDATALINES_18B 2
103#define AMDM37X_DISPC_CONTROL_TFTDATALINES_24B 3
104#define AMDM37X_DISPC_CONTROL_STALLMODE_FLAG (1 << 11)
105#define AMDM37X_DISPC_CONTROL_OVERLAYOPTIMIZATION_FLAG (1 << 12)
106#define AMDM37X_DISPC_CONTROL_GPIN0_FLAG (1 << 13)
107#define AMDM37X_DISPC_CONTROL_GPIN1_FLAG (1 << 14)
108#define AMDM37X_DISPC_CONTROL_GPOUT0_FLAG (1 << 15)
109#define AMDM37X_DISPC_CONTROL_GPOUT1_FLAG (1 << 16)
110#define AMDM37X_DISPC_CONTROL_HT_MASK 0x7
111#define AMDM37X_DISPC_CONTROL_HT_SHIFT 17
112#define AMDM37X_DISPC_CONTROL_TDMENABLE_FLAG (1 << 20)
113#define AMDM37X_DISPC_CONTROL_TDMPARALLELMODE_MASK 0x3
114#define AMDM37X_DISPC_CONTROL_TDMPARELLELMODE_SHIFT 21
115#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_MASK 0x3
116#define AMDM37X_DISPC_CONTROL_TDMCYCLEFORMAT_SHIFT 23
117#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_MASK 0x3
118#define AMDM37X_DISPC_CONTROL_TDMUNUSEDBITS_SHIFT 25
119#define AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG (1 << 27)
120#define AMDM37X_DISPC_CONTROL_LCDENABLESIGNAL_FLAG (1 << 28)
121#define AMDM37X_DISPC_CONTROL_KCDENABLEPOL_FLAG (1 << 29)
122#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK 0x3
123#define AMDM37X_DISPC_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT 30
124
125 ioport32_t config;
126#define AMDM37X_DISPC_CONFIG_PIXELGATED_FLAG (1 << 0)
127#define AMDM37X_DISPC_CONFIG_LOADMODE_MASK 0x3
128#define AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT 1
129#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDATAEVERYFRAME 0x0
130#define AMDM37X_DISPC_CONFIG_LOADMODE_PGUSER 0x1
131#define AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME 0x2
132#define AMDM37X_DISPC_CONFIG_LOADMODE_PGDFIRSTFRAME 0x3
133#define AMDM37X_DISPC_CONFIG_PALETTEGAMMATABLE_FLAG (1 << 3)
134#define AMDM37X_DISPC_CONFIG_PIXELDATAGATED_FLAG (1 << 4)
135#define AMDM37X_DISPC_CONFIG_PIXELCLOCKGATED_FLAG (1 << 5)
136#define AMDM37X_DISPC_CONFIG_HSYNCGATED_FLAG (1 << 6)
137#define AMDM37X_DISPC_CONFIG_VSYNCGATED_FLAG (1 << 7)
138#define AMDM37X_DISPC_CONFIG_ACBIASGATED_FLAG (1 << 8)
139#define AMDM37X_DISPC_CONFIG_FUNCGATED_FLAG (1 << 9)
140#define AMDM37X_DISPC_CONFIG_TCKLCDENABLE_FLAG (1 << 10)
141#define AMDM37X_DISPC_CONFIG_TCKLCDSELECTION_FLAG (1 << 11)
142#define AMDM37X_DISPC_CONFIG_TCKDIGENABLE_FLAG (1 << 12)
143#define AMDM37X_DISPC_CONFIG_TCKDIGSELECTION_FLAG (1 << 13)
144#define AMDM37X_DISPC_CONFIG_FIFOMERGE_FLAG (1 << 14)
145#define AMDM37X_DISPC_CONFIG_CPR_FLAG (1 << 15)
146#define AMDM37X_DISPC_CONFIG_FIFOHANDCHECK_FLAG (1 << 16)
147#define AMDM37X_DISPC_CONFIG_FIFOFILLING_FLAG (1 << 17)
148#define AMDM37X_DISPC_CONFIG_LCDPALPHABLENDERENABLDE_FLAG (1 << 18)
149#define AMDM37X_DISPC_CONFIG_TVALPHABLENDERENABLE_FLAG (1 << 19)
150
151 PADD32(1);
152 ioport32_t default_color[2];
153 ioport32_t trans_color[2];
154#define AMDM37X_DISPC_COLOR_MASK 0xffffff
155
156 const ioport32_t line_status;
157 ioport32_t line_number;
158#define AMDM37X_DISPC_LINE_NUMBER_MASK 0x3ff
159
160 ioport32_t timing_h;
161#define AMDM37X_DISPC_TIMING_H_HSW_MASK 0xff
162#define AMDM37X_DISPC_TIMING_H_HSW_SHIFT 0
163#define AMDM37X_DISPC_TIMING_H_HFP_MASK 0xfff
164#define AMDM37X_DISPC_TIMING_H_HFP_SHIFT 8
165#define AMDM37X_DISPC_TIMING_H_HBP_MASK 0xfff
166#define AMDM37X_DISPC_TIMING_H_HBP_SHIFT 20
167
168 ioport32_t timing_v;
169#define AMDM37X_DISPC_TIMING_V_VSW_MASK 0xff
170#define AMDM37X_DISPC_TIMING_V_VSW_SHIFT 0
171#define AMDM37X_DISPC_TIMING_V_VFP_MASK 0xfff
172#define AMDM37X_DISPC_TIMING_V_VFP_SHIFT 8
173#define AMDM37X_DISPC_TIMING_V_VBP_MASK 0xfff
174#define AMDM37X_DISPC_TIMING_V_VBP_SHIFT 20
175
176 ioport32_t pol_freq;
177#define AMDM37X_DISPC_POL_FREQ_ACB_MASK 0xff
178#define AMDM37X_DISPC_POL_FREQ_ACB_SHIFT 0
179#define AMDM37X_DISPC_POL_FREQ_ACBI_MASK 0xf
180#define AMDM37X_DISPC_POL_FREQ_ACBI_SHIFT 8
181#define AMDM37X_DISPC_POL_FREQ_IVS_FLAG (1 << 12)
182#define AMDM37X_DISPC_POL_FREQ_IHS_FLAG (1 << 13)
183#define AMDM37X_DISPC_POL_FREQ_IPC_FLAG (1 << 14)
184#define AMDM37X_DISPC_POL_FREQ_IEO_FLAG (1 << 15)
185#define AMDM37X_DISPC_POL_FREQ_RF_FLAG (1 << 16)
186#define AMDM37X_DISPC_POL_FREQ_ONOFF_FLAG (1 << 17)
187
188 ioport32_t divisor;
189#define AMDM37X_DISPC_DIVISOR_PCD_MASK 0xff
190#define AMDM37X_DISPC_DIVISOR_PCD_SHIFT 0
191#define AMDM37X_DISPC_DIVISOR_LCD_MASK 0xff
192#define AMDM37X_DISPC_DIVISOR_LCD_SHIFT 16
193
194 ioport32_t global_alpha;
195#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_MASK 0xff
196#define AMDM37X_DISPC_GLOBAL_ALPHA_GFXGLOBALALPHA_SHIFT 0
197#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_MASK 0xff
198#define AMDM37X_DISPC_GLOBAL_ALPHA_VID2GLOBALALPHA_SHIFT 16
199
200 ioport32_t size_dig;
201 ioport32_t size_lcd;
202
203 struct {
204 ioport32_t ba[2];
205 ioport32_t position;
206#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_MASK 0x7ff
207#define AMDM37X_DISPC_GFX_POSITION_GFXPOSX_SHIFT 0
208#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_MASK 0x7ff
209#define AMDM37X_DISPC_GFX_POSITION_GFXPOSY_SHIFT 16
210
211 ioport32_t size;
212#define AMDM37X_DISPC_SIZE_WIDTH_MASK 0x7ff
213#define AMDM37X_DISPC_SIZE_WIDTH_SHIFT 0
214#define AMDM37X_DISPC_SIZE_HEIGHT_MASK 0x7ff
215#define AMDM37X_DISPC_SIZE_HEIGHT_SHIFT 16
216
217 PADD32(4);
218 ioport32_t attributes;
219#define AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG (1 << 0)
220#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_MASK 0xf
221#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT 1
222#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB16 0x5
223#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16 0x6
224#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24_32 0x8
225#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24 0x9
226#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_ARGB 0xc
227#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBA 0xd
228#define AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX 0xe
229#define AMDM37X_DISPC_GFX_ATTRIBUTES_REPLICATIONENABLE_FLAG (1 << 5)
230#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_MASK 0x3
231#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXBURSTSIZE_SHIFT 6
232#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXCHANNELOUT_FLAG (1 << 8)
233#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXNIBBLEMODE_FLAG (1 << 9)
234#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXENDIANNES_FLAG (1 << 10)
235#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXFIFOPRELOAD_FLAG (1 << 11)
236#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_MASK 0x3
237#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXROTATION_SHIFT 12
238#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXARBITRATION_FLAG (1 << 14)
239#define AMDM37X_DISPC_GFX_ATTRIBUTES_GFXSELFREFRESH_FLAG (1 << 15)
240#define AMDM37X_DISPC_GFX_ATTRIBUTES_PREMULTIALPHA_FLAG (1 << 28)
241
242
243 ioport32_t fifo_threshold;
244 const ioport32_t fifo_size_status;
245 ioport32_t row_inc;
246 ioport32_t pixel_inc;
247 ioport32_t window_skip;
248 ioport32_t table_ba;
249 } gfx;
250
251 struct {
252 ioport32_t ba[2];
253 ioport32_t position;
254 ioport32_t size;
255 ioport32_t attributes;
256 ioport32_t fifo_threshold;
257 const ioport32_t fifo_size_status;
258 ioport32_t row_inc;
259 ioport32_t pixel_inc;
260 ioport32_t fir;
261 ioport32_t picture_size;
262 ioport32_t accui[2];
263 struct {
264 ioport32_t hi;
265 ioport32_t hvi;
266 } fir_coef[8];
267 ioport32_t conv_coef[5];
268 PADD32(2);
269 } vid[2];
270 /* 0x1d4 */
271 ioport32_t data_cycle[3];
272 /* 0x1e0 */
273 ioport32_t vid_fir_coef_v[8];
274 /* 0x200 */
275 PADD32(8);
276 /* 0x220 */
277 ioport32_t cpr_coef_r;
278 ioport32_t cpr_coef_g;
279 ioport32_t cpr_coef_b;
280 ioport32_t gfx_preload;
281
282 /* 0x230 */
283 ioport32_t vid_preload[2];
284
285} __attribute__((packed)) amdm37x_dispc_regs_t;
286
287
288static inline void amdm37x_dispc_setup_fb(amdm37x_dispc_regs_t *regs,
289 unsigned x, unsigned y, unsigned bpp, uintptr_t pa)
290{
291 ASSERT(regs);
292 /* Init sequence for dispc is in chapter 7.6.5.1.4 p. 1810,
293 * no idea what parts of that work. */
294
295 /* Disable all interrupts */
296 regs->irqenable = 0;
297
298 /* Pixel format specifics*/
299 uint32_t attrib_pixel_format = 0;
300 uint32_t control_data_lanes = 0;
301 switch (bpp)
302 {
303 case 32:
304 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGBX;
305 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
306 break;
307 case 24:
308 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB24;
309 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_24B;
310 break;
311 case 16:
312 attrib_pixel_format = AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_RGB16;
313 control_data_lanes = AMDM37X_DISPC_CONTROL_TFTDATALINES_16B;
314 break;
315 default:
316 ASSERT(false);
317 }
318
319 /* Prepare sizes */
320 const uint32_t size_reg =
321 (((x - 1) & AMDM37X_DISPC_SIZE_WIDTH_MASK)
322 << AMDM37X_DISPC_SIZE_WIDTH_SHIFT) |
323 (((y - 1) & AMDM37X_DISPC_SIZE_HEIGHT_MASK)
324 << AMDM37X_DISPC_SIZE_HEIGHT_SHIFT);
325
326 /* modes taken from u-boot, for 1024x768 */
327 // TODO replace magic values with actual correct values
328// regs->timing_h = 0x1a4024c9;
329// regs->timing_v = 0x02c00509;
330// regs->pol_freq = 0x00007028;
331// regs->divisor = 0x00010001;
332
333 /* setup output */
334 regs->size_lcd = size_reg;
335 regs->size_dig = size_reg;
336
337 /* Nice blue default color */
338 regs->default_color[0] = 0x0000ff;
339 regs->default_color[1] = 0x0000ff;
340
341 /* Setup control register */
342 uint32_t control = 0 |
343 AMDM37X_DISPC_CONTROL_PCKFREEENABLE_FLAG |
344 (control_data_lanes << AMDM37X_DISPC_CONTROL_TFTDATALINES_SHIFT) |
345 AMDM37X_DISPC_CONTROL_GPOUT0_FLAG |
346 AMDM37X_DISPC_CONTROL_GPOUT1_FLAG;
347 regs->control = control;
348
349 /* No gamma stuff only data */
350 uint32_t config = (AMDM37X_DISPC_CONFIG_LOADMODE_DATAEVERYFRAME
351 << AMDM37X_DISPC_CONFIG_LOADMODE_SHIFT);
352 regs->config = config;
353
354
355 /* Set framebuffer base address */
356 regs->gfx.ba[0] = pa;
357 regs->gfx.ba[1] = pa;
358 regs->gfx.position = 0;
359
360 /* Setup fb size */
361 regs->gfx.size = size_reg;
362
363 /* Set pixel format */
364 uint32_t attribs = 0 |
365 (attrib_pixel_format << AMDM37X_DISPC_GFX_ATTRIBUTES_FORMAT_SHIFT);
366 regs->gfx.attributes = attribs;
367
368 /* 0x03ff03c0 is the default */
369 regs->gfx.fifo_threshold = 0x03ff03c0;
370 /* This value should be stride - width, 1 means next pixel i.e.
371 * stride == width */
372 regs->gfx.row_inc = 1;
373 /* number of bytes to next pixel in BPP multiples */
374 regs->gfx.pixel_inc = 1;
375 /* only used if video is played over fb */
376 regs->gfx.window_skip = 0;
377 /* Gamma and palette table */
378 regs->gfx.table_ba = 0;
379
380 /* enable frame buffer graphics */
381 regs->gfx.attributes |= AMDM37X_DISPC_GFX_ATTRIBUTES_ENABLE_FLAG;
382 /* Update register values */
383 regs->control |= AMDM37X_DISPC_CONTROL_GOLCD_FLAG;
384 regs->control |= AMDM37X_DISPC_CONTROL_GODIGITAL_FLAG;
385 /* Enable output */
386 regs->control |= AMDM37X_DISPC_CONTROL_LCD_ENABLE_FLAG;
387 regs->control |= AMDM37X_DISPC_CONTROL_DIGITAL_ENABLE_FLAG;
388}
389
390
391#endif
392/**
393 * @}
394 */
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