| 1 | Memory management
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| 2 | =================
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| 3 |
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| 4 | 1. Virtual Address Translation
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| 5 |
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| 6 | 1.1 Hierarchical 4-level per address space page tables
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| 7 |
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| 8 | SPARTAN kernel deploys generic interface for 4-level page tables for these
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| 9 | architectures: amd64, arm32, ia32, mips32 and ppc32. In this setting, page
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| 10 | tables are hierarchical and are not shared by address spaces (i.e. one set of
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| 11 | page tables per address space).
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| 12 |
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| 13 |
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| 14 | VADDR
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| 15 | +-----------------------------------------------------------------------------+
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| 16 | | PTL0_INDEX | PTL1_INDEX | PTL2_INDEX | PTL3_INDEX | OFFSET |
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| 17 | +-----------------------------------------------------------------------------+
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| 18 |
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| 19 |
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| 20 | PTL0 PTL1 PTL2 PTL3
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| 21 | +--------+ +--------+ +--------+ +--------+
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| 22 | | | | | | PTL3 | -----\ | |
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| 23 | | | | | +--------+ | | |
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| 24 | | | +--------+ | | | | |
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| 25 | | | | PTL2 | -----\ | | | | |
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| 26 | | | +--------+ | | | | | |
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| 27 | | | | | | | | | +--------+
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| 28 | +--------+ | | | | | | | FRAME |
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| 29 | | PTL1 | -----\ | | | | | | +--------+
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| 30 | +--------+ | | | | | | | | |
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| 31 | | | | | | | | | | | |
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| 32 | | | | | | | | | | | |
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| 33 | +--------+ \----> +--------+ \----> +--------+ \----> +--------+
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| 34 | ^
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| 35 | |
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| 36 | |
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| 37 | +--------+
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| 38 | | PTL0 |
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| 39 | +--------+
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| 40 |
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| 41 |
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| 42 | PTL0 Page Table Level 0 (Page Directory)
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| 43 | PTL1 Page Table Level 1
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| 44 | PTL2 Page Table Level 2
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| 45 | PTL3 Page Table Level 3
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| 46 |
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| 47 | PTL0_INDEX Index into PTL0
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| 48 | PTL1_INDEX Index into PTL1
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| 49 | PTL2_INDEX Index into PTL2
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| 50 | PTL3_INDEX Index into PTL3
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| 51 |
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| 52 | VADDR Virtual address for which mapping is looked up
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| 53 | FRAME Physical address of memory frame to which VADDR is mapped
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| 54 |
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| 55 |
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| 56 | On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are
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| 57 | left out. TLB-only architectures are to define custom format for software page
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| 58 | tables.
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| 59 |
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| 60 | 1.2 Single global page hash table
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| 61 |
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| 62 | Generic page hash table interface is deployed on 64-bit architectures without
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| 63 | implied hardware support for hierarchical page tables, i.e. ia64 and sparc64.
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| 64 | There is only one global page hash table in the system shared by all address
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| 65 | spaces.
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| 66 |
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| 67 |
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| 68 | 2. Memory allocators
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| 69 |
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| 70 | 2.1 General allocator
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| 71 |
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| 72 | 'malloc' function accepts flags as a second argument. The flags are directly
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| 73 | passed to the underlying frame_alloc function.
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| 74 |
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| 75 | 1) If the flags parameter contains FRAME_ATOMIC, the allocator will not sleep.
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| 76 | The allocator CAN return NULL, when memory is not directly available.
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| 77 | The caller MUST check if NULL was not returned
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| 78 |
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| 79 | 2) If the flags parameter does not contain FRAME_ATOMIC, the allocator
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| 80 | will never return NULL, but it CAN sleep indefinitely. The caller
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| 81 | does not have to check the return value.
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| 82 |
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| 83 | 3) The maximum size that can be allocated using malloc is 256K
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| 84 |
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| 85 | Rules 1) and 2) apply to slab_alloc as well. Using SLAB allocator
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| 86 | to allocate too large values is not recommended.
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| 87 |
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