source:
mainline/kernel/arch@
c1b455e
Name | Size | Rev | Age | Author | Last Change |
---|---|---|---|---|---|
../ | |||||
amd64 | f2ef7fd | 17 years | Support for SYSENTER on ia32. | ||
arm32 | 4f8a0c0 | 17 years | Merge changeset 3122 from tracing to trunk. (Add missing include) | ||
ia32 | f2ef7fd | 17 years | Support for SYSENTER on ia32. | ||
ia32xen | ddb0df5 | 17 years | configurable cross-compiler prefix (using CROSS_PREFIX) | ||
ia64 | 1025d28 | 17 years | IA64: Support for real frequency | ||
mips32 | c867756e | 17 years | Write protection fault should not panic the mips32 kernel if it … | ||
ppc32 | c1b455e | 17 years | Fix bug #67. It was obviously all my fault - I allocated r3 for … | ||
ppc64 | ddb0df5 | 17 years | configurable cross-compiler prefix (using CROSS_PREFIX) | ||
sparc64 | ff3b7da7 | 17 years | Accesses to memory mapped registers should use volatile pointers so … |
|
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