source:
mainline/kernel/arch/sparc64/src@
9a8baed
| Name | Size | Rev | Age | Author | Last Change |
|---|---|---|---|---|---|
| ../ | |||||
| trap | f8ddd17 | 19 years | Rework support for virtually indexed cache. Instead of repeatedly … | ||
| smp | f8ddd17 | 19 years | Rework support for virtually indexed cache. Instead of repeatedly … | ||
| proc | 91d6d28 | 19 years | Take the possible difference between kernel and physical address into … | ||
| mm | b82a13c | 19 years | The D-cache line size is actually 32 bytes on UltraSPARC II, IIi (and … | ||
| drivers | 2a0cda72 | 19 years | On sparc64's tick interrupt, adjust the TICK_COMPARE register instead … | ||
| ddi | ed166f7 | 19 years | A lot of untested sparc64 stuff: - Write ASID to hardware when a … | ||
| cpu | cd896e2 | 19 years | Remove old stuff. | ||
| start.S | 10.0 KB | 92778f2 | 19 years | Initial support for handling illegal virtual aliases on sparc64. | |
| sparc64.c | 3.8 KB | aeaebcc | 19 years | Make the sparc64 kernel compile again. | |
| panic.S | 1.5 KB | 11675207 | 17 years | Move everything to kernel/. | |
| fpu_context.c | 5.0 KB | da02e69 | 19 years | Unfortunatelly, the sparc64's FPRS register is writable by … | |
| dummy.s | 1.6 KB | 7ba7c6d | 19 years | A quote from from SPARC V9 specification: The Y register is … | |
| context.S | 3.2 KB | f0f05ad | 19 years | sparc64 context does not have to include the CLEANWIN register. | |
| console.c | 3.8 KB | 8513ad7 | 19 years | Add support for IPC notifications even for polled ns16550 based keyboard. | |
| asm.S | 6.2 KB | 6eabb6e6 | 19 years | Support for sparc64 FPU context. | |
|
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