| 1 | #
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| 2 | # Copyright (C) 2005 Jakub Jermar
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| 3 | # All rights reserved.
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| 4 | #
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| 5 | # Redistribution and use in source and binary forms, with or without
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| 6 | # modification, are permitted provided that the following conditions
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| 7 | # are met:
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| 8 | #
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| 9 | # - Redistributions of source code must retain the above copyright
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| 10 | # notice, this list of conditions and the following disclaimer.
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| 11 | # - Redistributions in binary form must reproduce the above copyright
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| 12 | # notice, this list of conditions and the following disclaimer in the
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| 13 | # documentation and/or other materials provided with the distribution.
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| 14 | # - The name of the author may not be used to endorse or promote products
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| 15 | # derived from this software without specific prior written permission.
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| 16 | #
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| 17 | # THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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| 18 | # IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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| 19 | # OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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| 20 | # IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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| 21 | # INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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| 22 | # NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | #
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| 28 |
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| 29 | /**
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| 30 | * This file contains kernel trap table.
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| 31 | */
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| 32 |
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| 33 | .register %g2, #scratch
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| 34 | .register %g3, #scratch
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| 35 | .register %g6, #scratch
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| 36 | .register %g7, #scratch
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| 37 |
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| 38 | .text
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| 39 |
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| 40 | #include <arch/trap/trap_table.h>
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| 41 | #include <arch/trap/regwin.h>
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| 42 | #include <arch/trap/interrupt.h>
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| 43 | #include <arch/trap/exception.h>
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| 44 | #include <arch/trap/mmu.h>
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| 45 | #include <arch/stack.h>
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| 46 |
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| 47 | #define TABLE_SIZE TRAP_TABLE_SIZE
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| 48 | #define ENTRY_SIZE TRAP_TABLE_ENTRY_SIZE
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| 49 |
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| 50 | /*
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| 51 | * Kernel trap table.
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| 52 | */
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| 53 | .align TABLE_SIZE
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| 54 | .global trap_table
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| 55 | trap_table:
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| 56 |
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| 57 | /* TT = 0x08, TL = 0, instruction_access_exception */
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| 58 | .org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE
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| 59 | .global instruction_access_exception
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| 60 | instruction_access_exception:
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| 61 | SIMPLE_HANDLER do_instruction_access_exc
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| 62 |
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| 63 | /* TT = 0x10, TL = 0, illegal_instruction */
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| 64 | .org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE
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| 65 | .global illegal_instruction
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| 66 | illegal_instruction:
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| 67 | SIMPLE_HANDLER do_illegal_instruction
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| 68 |
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| 69 | /* TT = 0x24, TL = 0, clean_window handler */
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| 70 | .org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE
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| 71 | .global clean_window_handler
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| 72 | clean_window_handler:
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| 73 | CLEAN_WINDOW_HANDLER
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| 74 |
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| 75 | /* TT = 0x32, TL = 0, data_access_error */
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| 76 | .org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE
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| 77 | .global data_access_error
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| 78 | data_access_error:
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| 79 | SIMPLE_HANDLER do_data_access_error
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| 80 |
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| 81 | /* TT = 0x34, TL = 0, mem_address_not_aligned */
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| 82 | .org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
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| 83 | .global mem_address_not_aligned
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| 84 | mem_address_not_aligned:
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| 85 | SIMPLE_HANDLER do_mem_address_not_aligned
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| 86 |
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| 87 | /* TT = 0x41, TL = 0, interrupt_level_1 handler */
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| 88 | .org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE
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| 89 | .global interrupt_level_1_handler
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| 90 | interrupt_level_1_handler:
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| 91 | INTERRUPT_LEVEL_N_HANDLER 1
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| 92 |
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| 93 | /* TT = 0x42, TL = 0, interrupt_level_2 handler */
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| 94 | .org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE
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| 95 | .global interrupt_level_2_handler
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| 96 | interrupt_level_2_handler:
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| 97 | INTERRUPT_LEVEL_N_HANDLER 2
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| 98 |
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| 99 | /* TT = 0x43, TL = 0, interrupt_level_3 handler */
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| 100 | .org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE
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| 101 | .global interrupt_level_3_handler
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| 102 | interrupt_level_3_handler:
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| 103 | INTERRUPT_LEVEL_N_HANDLER 3
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| 104 |
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| 105 | /* TT = 0x44, TL = 0, interrupt_level_4 handler */
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| 106 | .org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE
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| 107 | .global interrupt_level_4_handler
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| 108 | interrupt_level_4_handler:
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| 109 | INTERRUPT_LEVEL_N_HANDLER 4
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| 110 |
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| 111 | /* TT = 0x45, TL = 0, interrupt_level_5 handler */
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| 112 | .org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE
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| 113 | .global interrupt_level_5_handler
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| 114 | interrupt_level_5_handler:
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| 115 | INTERRUPT_LEVEL_N_HANDLER 5
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| 116 |
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| 117 | /* TT = 0x46, TL = 0, interrupt_level_6 handler */
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| 118 | .org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE
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| 119 | .global interrupt_level_6_handler
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| 120 | interrupt_level_6_handler:
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| 121 | INTERRUPT_LEVEL_N_HANDLER 6
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| 122 |
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| 123 | /* TT = 0x47, TL = 0, interrupt_level_7 handler */
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| 124 | .org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE
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| 125 | .global interrupt_level_7_handler
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| 126 | interrupt_level_7_handler:
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| 127 | INTERRUPT_LEVEL_N_HANDLER 7
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| 128 |
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| 129 | /* TT = 0x48, TL = 0, interrupt_level_8 handler */
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| 130 | .org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE
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| 131 | .global interrupt_level_8_handler
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| 132 | interrupt_level_8_handler:
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| 133 | INTERRUPT_LEVEL_N_HANDLER 8
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| 134 |
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| 135 | /* TT = 0x49, TL = 0, interrupt_level_9 handler */
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| 136 | .org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE
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| 137 | .global interrupt_level_9_handler
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| 138 | interrupt_level_9_handler:
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| 139 | INTERRUPT_LEVEL_N_HANDLER 9
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| 140 |
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| 141 | /* TT = 0x4a, TL = 0, interrupt_level_10 handler */
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| 142 | .org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE
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| 143 | .global interrupt_level_10_handler
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| 144 | interrupt_level_10_handler:
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| 145 | INTERRUPT_LEVEL_N_HANDLER 10
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| 146 |
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| 147 | /* TT = 0x4b, TL = 0, interrupt_level_11 handler */
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| 148 | .org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE
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| 149 | .global interrupt_level_11_handler
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| 150 | interrupt_level_11_handler:
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| 151 | INTERRUPT_LEVEL_N_HANDLER 11
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| 152 |
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| 153 | /* TT = 0x4c, TL = 0, interrupt_level_12 handler */
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| 154 | .org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE
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| 155 | .global interrupt_level_12_handler
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| 156 | interrupt_level_12_handler:
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| 157 | INTERRUPT_LEVEL_N_HANDLER 12
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| 158 |
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| 159 | /* TT = 0x4d, TL = 0, interrupt_level_13 handler */
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| 160 | .org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE
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| 161 | .global interrupt_level_13_handler
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| 162 | interrupt_level_13_handler:
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| 163 | INTERRUPT_LEVEL_N_HANDLER 13
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| 164 |
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| 165 | /* TT = 0x4e, TL = 0, interrupt_level_14 handler */
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| 166 | .org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE
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| 167 | .global interrupt_level_14_handler
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| 168 | interrupt_level_14_handler:
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| 169 | INTERRUPT_LEVEL_N_HANDLER 14
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| 170 |
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| 171 | /* TT = 0x4f, TL = 0, interrupt_level_15 handler */
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| 172 | .org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE
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| 173 | .global interrupt_level_15_handler
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| 174 | interrupt_level_15_handler:
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| 175 | INTERRUPT_LEVEL_N_HANDLER 15
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| 176 |
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| 177 | /* TT = 0x60, TL = 0, interrupt_vector_trap handler */
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| 178 | .org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE
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| 179 | .global interrupt_vector_trap_handler
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| 180 | interrupt_vector_trap_handler:
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| 181 | INTERRUPT_VECTOR_TRAP_HANDLER
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| 182 |
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| 183 | /* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
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| 184 | .org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
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| 185 | .global fast_instruction_access_mmu_miss_handler
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| 186 | fast_instruction_access_mmu_miss_handler:
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| 187 | FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
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| 188 |
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| 189 | /* TT = 0x68, TL = 0, fast_data_access_MMU_miss */
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| 190 | .org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
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| 191 | .global fast_data_access_mmu_miss_handler
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| 192 | fast_data_access_mmu_miss_handler:
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| 193 | FAST_DATA_ACCESS_MMU_MISS_HANDLER
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| 194 |
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| 195 | /* TT = 0x6c, TL = 0, fast_data_access_protection */
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| 196 | .org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE
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| 197 | .global fast_data_access_protection_handler
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| 198 | fast_data_access_protection_handler:
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| 199 | FAST_DATA_ACCESS_PROTECTION_HANDLER
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| 200 |
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| 201 | /* TT = 0x80, TL = 0, spill_0_normal handler */
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| 202 | .org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE
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| 203 | .global spill_0_normal
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| 204 | spill_0_normal:
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| 205 | SPILL_NORMAL_HANDLER
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| 206 |
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| 207 | /* TT = 0xc0, TL = 0, fill_0_normal handler */
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| 208 | .org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE
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| 209 | .global fill_0_normal
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| 210 | fill_0_normal:
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| 211 | FILL_NORMAL_HANDLER
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| 212 |
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| 213 | /*
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| 214 | * Handlers for TL>0.
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| 215 | */
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| 216 |
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| 217 | /* TT = 0x08, TL > 0, instruction_access_exception */
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| 218 | .org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE
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| 219 | .global instruction_access_exception_high
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| 220 | instruction_access_exception_high:
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| 221 | SIMPLE_HANDLER do_instruction_access_exc
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| 222 |
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| 223 | /* TT = 0x10, TL > 0, illegal_instruction */
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| 224 | .org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE
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| 225 | .global illegal_instruction_high
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| 226 | illegal_instruction_high:
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| 227 | SIMPLE_HANDLER do_illegal_instruction
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| 228 |
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| 229 | /* TT = 0x24, TL > 0, clean_window handler */
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| 230 | .org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
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| 231 | .global clean_window_handler_high
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| 232 | clean_window_handler_high:
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| 233 | CLEAN_WINDOW_HANDLER
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| 234 |
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| 235 | /* TT = 0x32, TL > 0, data_access_error */
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| 236 | .org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE
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| 237 | .global data_access_error_high
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| 238 | data_access_error_high:
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| 239 | SIMPLE_HANDLER do_data_access_error
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| 240 |
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| 241 | /* TT = 0x34, TL > 0, mem_address_not_aligned */
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| 242 | .org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE
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| 243 | .global mem_address_not_aligned_high
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| 244 | mem_address_not_aligned_high:
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| 245 | SIMPLE_HANDLER do_mem_address_not_aligned
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| 246 |
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| 247 | /* TT = 0x64, TL > 0, fast_instruction_access_MMU_miss */
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| 248 | .org trap_table + (TT_FAST_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE
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| 249 | .global fast_instruction_access_mmu_miss_handler_high
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| 250 | fast_instruction_access_mmu_miss_handler_high:
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| 251 | FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
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| 252 |
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| 253 | /* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
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| 254 | .org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
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| 255 | .global fast_data_access_mmu_miss_handler_high
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| 256 | fast_data_access_mmu_miss_handler_high:
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| 257 | FAST_DATA_ACCESS_MMU_MISS_HANDLER
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| 258 |
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| 259 | /* TT = 0x6c, TL > 0, fast_data_access_protection */
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| 260 | .org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE
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| 261 | .global fast_data_access_protection_handler_high
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| 262 | fast_data_access_protection_handler_high:
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| 263 | FAST_DATA_ACCESS_PROTECTION_HANDLER
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| 264 |
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| 265 | /* TT = 0x80, TL > 0, spill_0_normal handler */
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| 266 | .org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE
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| 267 | .global spill_0_normal_high
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| 268 | spill_0_normal_high:
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| 269 | SPILL_NORMAL_HANDLER
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| 270 |
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| 271 | /* TT = 0xc0, TL > 0, fill_0_normal handler */
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| 272 | .org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE
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| 273 | .global fill_0_normal_high
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| 274 | fill_0_normal_high:
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| 275 | FILL_NORMAL_HANDLER
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| 276 |
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| 277 |
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| 278 | /* Preemptible trap handler.
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| 279 | *
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| 280 | * This trap handler makes arrangements to
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| 281 | * make calling scheduler() possible.
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| 282 | *
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| 283 | * The caller is responsible for doing save
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| 284 | * and allocating PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE
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| 285 | * bytes on stack.
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| 286 | *
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| 287 | * Input registers:
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| 288 | * %l0 Address of function to call.
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| 289 | * Output registers:
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| 290 | * %l1 - %l7 Copy of %g1 - %g7
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| 291 | */
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| 292 | .global preemptible_handler
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| 293 | preemptible_handler:
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| 294 | /*
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| 295 | * Save TSTATE, TPC, TNPC and PSTATE aside.
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| 296 | */
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| 297 | rdpr %tstate, %g1
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| 298 | rdpr %tpc, %g2
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| 299 | rdpr %tnpc, %g3
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| 300 | rdpr %pstate, %g4
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| 301 |
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| 302 | stx %g1, [%fp + STACK_BIAS + SAVED_TSTATE]
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| 303 | stx %g2, [%fp + STACK_BIAS + SAVED_TPC]
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| 304 | stx %g3, [%fp + STACK_BIAS + SAVED_TNPC]
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| 305 | stx %g4, [%fp + STACK_BIAS + SAVED_PSTATE]
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| 306 |
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| 307 | /*
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| 308 | * Write 0 to TL.
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| 309 | */
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| 310 | wrpr %g0, 0, %tl
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| 311 |
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| 312 | /*
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| 313 | * Alter PSTATE.
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| 314 | * - switch to normal globals.
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| 315 | */
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| 316 | and %g4, ~1, %g4 ! mask alternate globals
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| 317 | wrpr %g4, 0, %pstate
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| 318 |
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| 319 | /*
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| 320 | * Save the normal globals.
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| 321 | */
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| 322 | SAVE_GLOBALS
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| 323 |
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| 324 | /*
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| 325 | * Call the higher-level handler.
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| 326 | */
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| 327 | call %l0
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| 328 | nop
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| 329 |
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| 330 | /*
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| 331 | * Restore the normal global register set.
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| 332 | */
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| 333 | RESTORE_GLOBALS
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| 334 |
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| 335 | /*
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| 336 | * Restore PSTATE from saved copy.
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| 337 | * Alternate globals become active.
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| 338 | */
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| 339 | ldx [%fp + STACK_BIAS + SAVED_PSTATE], %l4
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| 340 | wrpr %l4, 0, %pstate
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| 341 |
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| 342 | /*
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| 343 | * Write 1 to TL.
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| 344 | */
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| 345 | wrpr %g0, 1, %tl
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| 346 |
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| 347 | /*
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| 348 | * Read TSTATE, TPC and TNPC from saved copy.
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| 349 | */
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| 350 | ldx [%fp + STACK_BIAS + SAVED_TSTATE], %g1
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| 351 | ldx [%fp + STACK_BIAS + SAVED_TPC], %g2
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| 352 | ldx [%fp + STACK_BIAS + SAVED_TNPC], %g3
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| 353 |
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| 354 | /*
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| 355 | * Do restore to match the save instruction from the top-level handler.
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| 356 | */
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| 357 | restore
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| 358 |
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| 359 | /*
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| 360 | * On execution of retry instruction, CWP will be restored from TSTATE register.
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| 361 | * However, because of scheduling, it is possible that CWP in saved TSTATE
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| 362 | * is different from current CWP. The following chunk of code fixes CWP
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| 363 | * in the saved copy of TSTATE.
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| 364 | */
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| 365 | rdpr %cwp, %g4 ! read current CWP
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| 366 | and %g1, ~0x1f, %g1 ! clear CWP field in saved TSTATE
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| 367 | or %g1, %g4, %g1 ! write current CWP to TSTATE
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| 368 |
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| 369 | /*
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| 370 | * Restore TSTATE, TPC and TNPC from saved copies.
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| 371 | */
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| 372 | wrpr %g1, 0, %tstate
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| 373 | wrpr %g2, 0, %tpc
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| 374 | wrpr %g3, 0, %tnpc
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| 375 |
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| 376 | /*
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| 377 | * Return from interrupt.
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| 378 | */
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| 379 | retry
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